Compact Low-Power Impedance-to-Digital Converter for Sensor Array ...
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Compact Low-Power Impedance-to-Digital Converter for Sensor Array Microsystems Chao Yang, Sachin R. Jadhav, R. Mark Worden, and Andrew J. Mason, Senior Member, IEEE
Abstract—With the rapid progress in CMOS compatible microfabrication of biosensors, there is an emerging need to miniaturize biosensor arrays onto the surface of silicon chips that acquire and process sensor data, permitting improved sensitivity, cost and throughput. In this paper, a low power circuit that extracts and digitizes sensor impedance information is presented. Composed of a novel multiplying integrator and a unique bidirectional counter/shifter, the circuit shares resources for impedance extraction and digitization to maximize hardware efficiency. The extremely compact size of the circuit enables the implementation of sensor array microsystems with simultaneous multi-channel readout. Fabricated in 0.5 m CMOS, the circuit consumes 6 at 3 V and occupies only 0.06 mm2 , permitting over 100 readout channels within a 3 3 mm die. Circuit performance has been verified with a biosensor for gramicidin ion channel embedded in a tethered bilayer lipid membrane.
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Index Terms—Biosensor array, electrochemical instrumentation, impedance spectroscopy, impedance-to-digital converter.
I. INTRODUCTION
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INIATURIZED sensor arrays enable parallel analysis of multiple parameters. With advances in CMOS compatible fabrication of microelectrodes [1], [2], there is a trend to build sensor array microsystems that realize miniaturized sensor elements on the surface of silicon chips and interrogate these elements with on-chip electronics [3]–[6]. By eliminating the need for bulky bench-top instruments, a sensor array microsystem not only lowers cost but also enables many applications outside of highly specialized laboratories, revolutionizing numerous sensor platforms, such as DNA testing, drug screening, and security monitoring. Many new and emerging sensor technologies, particularly those based on bio- and nano-materials rely on impedance spectroscopy (IS) to elucidate the information contained within its impedance response over a range of stimulus frequencies. For example, ion channel membrane protein biosensors require IS [7], [8]; some gas sensors [9] and humidity sensors [10] are also interrogated through IS; even DNA sensors can be analyzed by tracking the capacitive component of impedance [4] These technologies are Manuscript received September 04, 2008; revised January 18, 2009. Current version published September 28, 2009. This paper was approved by Associate Editor Kari Halonen. This work was supported by the Engineering Research Centers Program of the National Science Foundation (NSF) under Award Number EEC-9986866 and by NSF Award Number DBI-0649847. C. Yang was with Michigan State University, East Lansing, MI 48824 USA, and is now with Marvell Semiconductor, Austin, TX 78746 USA (e-mail: [email protected]). S. R. Jadhav, R. M. Worden, and A. J. Mason are with Michigan State University, East Lansing, MI 48824 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2009.2028054
Fig. 1. Conceptual structure of an integrated impedance-based sensor array microsystem.
ideally suited for miniaturized arrays that permit multi-parameter sensor fusion and improve measurement accuracy [11]. However, neither commercial impedance extraction systems nor those recently reported for biomedical and biochemical measurement [12]–[14] support multi-channel sensor arrays. Furthermore, existing IS systems do not permit miniaturization to the scale necessary for hand-held, point-of-care, or even smaller devices required for implantable applications. Although there is a clear need for chip-scale integration of sensor arrays and impedance readout electronics, this realization is challenged by the heavy signal processing load associated with multi-channel impedance extraction [15]. To overcome this obstacle, highly efficient hardware structures must be developed. This paper presents a compact, high-sensitivity impedanceto-digital converter (IDC) developed to extract sensor information in array microsystems. An example impedance array microsystem is shown in Fig. 1, where a sensor array is formed on the surface of an integrated circuit chip equipped for IS measurement. Ideally, each element of the array would have its own front-end IS circuit to allow simultaneous multi-channel measurement, as illustrated in Fig. 2. Compared to the alternative of a single time-multiplexed readout circuit for the entire array, this approach enables rapid interrogation of the array, improves sensor throughput, eliminates leakage due to analog multiplexers (potentially larger than a sensor’s small response), and permits the simultaneous measurements necessary to correlate data from multiple sensors. To realize such a platform, each IDC block must: 1) be implemented with minimum silicon footprint to sustain tens to hundreds of sensors per chip; 2) be capable of locally extracting impedance information from raw data to distribute the heavy signal processing workload and reduce data transmission bandwidth requirements; 3) digitize
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The lock-in IDC measures and digitizes the sensors’ admittance information, and , one at a time in sequential cycles. To accomplish this, the lock-in IDC requires a square wave reference signal, which is either in phase with the stimulus (for extracting the real component, ), or in quadrature phase with the stimulus (for extracting the imaginary component, ). Digital counters are employed within the lock-in IDC to assist in the signal processing and store digital output values. These counters can also be reconfigured to operate as output shifters, recycling the counter hardware during serial data output. B. Hardware Efficient Impedance Extraction Algorithm Fig. 2. Block diagram of a multi-channel impedance spectroscopy microsystem. Each sensor element has an IS readout circuit digitalizes the sensor response and stores it onto a shift register chain.
data locally to facilitate system integration; 4) consume low power to avoid overheating sensor materials and extend battery life in portable applications; and 5) accept a wide input current dynamic range (sub-picoampere to tens of nanoamperes) to accommodate a diversity of miniaturized sensors. The new IDC circuit that overcomes the challenges and achieves the objectives outlined above is described in this paper. Section II describes the function of the IDC circuit and explains the algorithm for the new impedance extraction approach. The IDC architecture and VLSI realization are described in Sections III and IV. Test and characterization results for the IDC circuit are presented in Section V, and test results from a prototype miniaturized biosensor system are discussed Section VI. II. PRINCIPLES OF IMPEDANCE EXTRACTION A. Principles The newly developed circuit extracts and digitizes a sensor’s impedance response over frequency, up to 10 kHz to suit a wide range of sensor materials. Because the circuit utilizes a reference signal of the same frequency as the stimulus, it is similar in function to a lock-in amplifier [16] and will be referred to as a lock-in impedance-to-digital converter. As shown in Fig. 3, this lock-in IDC converts the real and imaginary portions of a sinusoidal current into a digital value. A digital clock is required to synchronize the internal signal processing. The input current, , is the response of a sensor to a sinusoid voltage stimulus of . The amplitude, , and phase, , of the input response current contain the sensor’s impedance information. can also be represented as the sum of cosine and sine components given by
Several approaches are available to perform the IS. They can be sorted into two primary categories: Fast Fourier Transform (FFT) IS and Frequency Response Analyzer (FRA) IS [15], [17]. FFT-based methods rely on digital signal processing to extract frequency components from a broadband (e.g., pulse) stimulus. They are hardware intensive and not suitable for compact, single-chip realization FRA-based methods measure impedance for a single frequency point at a time, and the required hardware can more readily be reduced to chip scale. Thus, lock-in IDC is based on the FRA algorithm. A functional block diagram of the IDC is shown in Fig. 3. The lock-in IDC performs the multiplication and integration required for the FRA algorithm as well as the digitization of the result. The main difference between a traditional FRA IS system and the lock-in IDC is that, instead of using an analog sinusoid reference input, the IDC uses square waves of the same phase and frequency to perform the lock-in detection [15], [17]. This modification is key to permitting a compact VLSI implementation. There are several methods the square wave signal could readily be generated, including zero crossing detection of a reference sinusoid signal [18]. Zero crossing detecting could introduce delay (phase error), but within the frequency range of interest for biosensors (less than 10 kHz), the error due to this delay is negligible. After the integration operation, the real or imaginary portion (selectable) of the input sinusoid response current appears at the integrator’s output as a DC signal. (Fig. 3), the multiplier square wave reference When , signal, , is in phase with the sensor stimulus signal, and is described by (3) where is the period of the stimulus and is a integer. Ascan be represented by suming the sensor’s response current , the integrator’s output at the end of continuous stimulus cycles is
(1) where coefficients and represent the real and imaginary portion of the sensor’s admittance (the reciprocal of impedance), respectively. The relationship between these coefficients and information is (2)
(4) When compared with (2), it can be seen that the result is proportional to the real portion of the sensor’s admittance. Alterna-
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Fig. 3. Functional block diagram of a lock-in IDC block illustrating its impedance extraction algorithm.
Fig. 4. Principal schematic of the lock-in IDC circuit.
tively, when , the square wave reference is in phase with and its function is given by else For the same result at the end of
(5) sensor response, the integrator’s continuous stimulus cycles is
(6) Based on (2), this result is proportional to the imaginary portion of the sensor’s admittance. This adaptation of the FRA algorithm enables a compact mixed-signal VLSI realization. In particular, the analog multiplier implementation can be significantly simplified because multiplication is performed between an analog current and a digital signal.
III. ARCHITECTURE OF THE LOCK-IN IDC Realizing the algorithm shown in Fig. 3 in a chip-area efficient manner is necessary to support simultaneous multi-channel readout of a sensor array. This can only be achieved by a lock-in IDC that shares hardware resources among different functions. A multiplying integrator was developed to share hardware between multiplication and integration functions. In addition, a bidirectional digital counter was designed that could share the functions of extending the output range of the multiplying integrator, storing the digitized result, and shifting digital data out after the readout cycle. A. Multiplying Integrator Many analog multiplier structures have been developed, including CMOS analog multipliers utilizing the drain current square law [19]–[22] or subthreshold trans-linear principles [23], [24], and modulation based analog multipliers [25]. All of these multiplier circuits require dedicated hardware including related bias or control circuits. To minimize the footprint of the IDC circuit, a new multiplier structure, shown in Fig. 4, has been implemented that shares the hardware resources necessary to implement the integration function. In Fig. 3, the lock-in IDC reference signal is a digital square wave with values between 1 and , and the sensor’s response
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is an analog current . To implement the impedance extraction algorithm, these two signals must be multiplied. Multiplication of a current with the digital square wave could be realized by frequently changing the direction of the current according the digital square wave value. Although the direction of sensor response current can not be reversed directly, a reverse-direction copy could be generated through current mirroring. However, resolution would be lost due to mirroring mismatch. To avoid this detrimental effect, the polarity of the following integrator stage could be changed, which has the same effect as flipping the current direction. As a result, this flipping integrator realizes the multiplication function without a dedicated multiplier. Because analog integrators have a limited output range, two comparators and counters are employed to extend the output range and digitize integrating results. This approach was found to be effective and efficient and was adopted. This square-wave multiplication concept is similar to the up-converting or demodulation operation in chopper stabilization techniques [26], where two square-wave multipliers are employed to up-convert the input signal to higher frequency noise and op-amp and later demodulate it to eliminate offset of. With chopper stabilization, to accurately recover the signal after demodulation with a simple filter, the square-wave clock frequency has to be much higher than signal bandwidth. However, in the lock-in IDC, the square-wave clock has to be the same as the input signal frequency, and we only need one square-wave multiplier. The resulting architecture resembles a first order sigma delta modulator [27], where an integrator, comparator and counters are also employed, with several differences including the need to flip the integrator, use of two comparator, and inclusion of counters. B. Hardware Sharing Architecture A simplified schematic of the new lock-in IDC is shown in Fig. 4, where is the reference square wave (see Fig. 3) and CLK is an external clock that synchronizes the system operation. In Fig. 4, the circuit in shaded area is the multiplying integrator that can change its polarity according to . Portions of this circuit are also shared with other blocks to realize the digitization function. Two comparators are employed to monitor the ) are integrator output. The results of the comparators ( and stored in two -type flip flops (DFF) at each rising edge of the CLK signal. Once the integrator output is outside of a predefined , either or becomes high and draws the range set by or integrator output back within range by feeding either into the input. and are designed to be equal in magnitude with opposite polarity, and any mismatch in magnitude can be accounted for in calibration, as discussed below. To store the digitized value, two multi-mode bidirectional counters are employed. Their counting mode (up/down counting) is controlled by ; the counter is in up counting mode when is high and in down counting mode when is low. At the end of the readout operation, the contents of these two counters are the digitized results. The signal waveforms shown in Fig. 5 may be helpful to understand the description of operation that follows. 1) Operation Principles: To improve accuracy, the switch in Fig. 4) was denetwork around the DFFs (shaded area signed in a unique manner. To explain the switch network op-
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eration, let us first consider just one stimulus signal cycle (the principle is the same for multiple cycles) and initially assume are low. The other that at any transition edge both and cases will be discussed later. Assume is in phase with , as in (3). The counters and integrating capacitor are reset at time , is 1, and just before ’s edge at time 0. From time 0 to , applying charge conservation at the input node, we have (7) is the residue value at the integrator output, is where the updating clock period, is the number of clock cycles from time 0 to . Here, the counters are set to up-counting mode , the contents of the positive because is high. At time is the summation of ’s, and the negative counter counter holds the summation of since they were reset at time 0. Both summations are represented in the right-hand side of (7). , the integrator capacitor is flipped and the inteAt time . From time to (just begrator output becomes fore and ’s rising edge), integrator operation is defined by
(8) represents the integrator output voltage at time where (before ’s rising edge). At time , goes high, the integrator capacitor is flipped back, and the integrator output becomes . For the second half cycle, while is low, the counters are set to down-counting mode. The initial value in the and counters are and , respectively. At time , and counter concounter contains . tains The result over the entire period from 0 to can be determined by subtracting (8) from (7), yielding
(9) which shows that the result is determined by the residue value on the integrator and the contents in the two counters. When design parameters ( , , and ) are chosen such that
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Fig. 5. Simulated waveforms of control signals in the lock-in IDC. The interrogation frequency is 1 kHz. The interval around '’s transition edge is magnified below.
, the analog residue can be ignored and treated as noise, and the result is represented digitally by the values in the counters. Referring to (4), notice also ) is, proportional that this result (where is in phase with to the real portion of the input signal. The value of the real portion can be retrieved from the digitized results by evaluating (10) and are the digital values where stored in the two counters and accounts for any mismatch of and ). The value of can the two reference currents ( be determined by calibration, as discussed below. . The results above assumed that was in phase with , it can be shown Alternatively, if is in phase with in a similar derivation that the counter results will contain the digitized imaginary portion of the input signal. The value of the imaginary portion can also be recovered using (10). Thus, the circuit can extract both the real and imaginary components of the response current simply by setting the digital value of in Fig. 3. Thus far, operation of the lock-in IDC has been explained for a single stimulus cycle only. The digital output dynamic range is controlled by in (9), which is given by (11)
are the periods of the stimulus and updating where and clock, respectively. For many of the biosensor applications, 8-bit resolution is more than sufficient. Thus, we choose such . In this design, the update clock rate was chosen that to be 100 kHz so that a 100 nA input current (maximum supported) will not saturate the integrator (with a 1 pF capacitor) over a clock period. Within the targeted reference frequency range(1 mHz to 10 kHz), this update clock can only guarantee 8-bit or higher resolution in one stimulus cycle for the refer. For ence frequency of 390 Hz and below, where frequencies above the 390 Hz, after an initial reset, the circuit is operated for multiple consecutive stimulus cycles ( cycles). In this case, the analog residue term in (9) retains (roughly) its single cycle magnitude, but the digital value stored in the counters is magnified by M. Thus, the digital output dynamic range is improved. The value of M can be chosen to obtain the desired resolution at the maximum frequency of interest. At the maximum reference frequency (10 kHz), with update clock of 100 kHz, M must be greater than 26 to achieve 8-bit resolution. 2) Reference Current Exchange: In the derivation above, were assumed to be low at the transition edge both and of . To analyze the other potential cases, consider that, when either or is high, they switch in the reference current to inject a compensating charge at a constant rate (defined by magnior ), thus forcing the integrator tude reference current voltage output back within range. If the integrating capacitor’s
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polarity is changed (due to ’s edge) while or is high, the compensating current must also been reversed; otherwise, it will produce an error of up to one digitization step for each stimulus cycle. This error will accumulate for multiple stimulus cycles. To eliminate this error, the multiplexing switches at the inputs and outputs of the two DFFs (shaded area in Fig. 4) have been inserted to appropriately adjust the reference current polarity. If or is high when ’s edge arrives, these switches either to exchange their status (values), thus changing force and the polarity of charge injection by the reference currents for the remainder of the clock cycle. Fig. 5 shows the simulated waveforms of the signals responsible for this feature along with the in Fig. 4). Here, the input siintegrator’s analog output ( frequency is 1 kHz, the system is reset at nusoid current time 100 s, and is in phase with the sine stimulus signal. In this example, right before goes low, is high and the inte. When goes low, and grator is being charged by exchange their status; thus becomes high, and the integrator for rest of the cycle. Without this reference is charged by current exchange during the flipping of the integrator, an error up to one digitization step (one counter step) can be generated. This exchange improves the accurate significantly. This feature and having the same magnitude. Although relies on fabrication will generate some mismatch between these two currents, it can easily be controlled within 1%, which permits the error associated with flipping the integrator to be less than 1% of one digitization step using this reference current exchange feature.
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Fig. 6. Operational amplifier schematic for the multiplying integrator.
charge from both plates of the capacitor. Because the voltage at the op-amp’s negative input is set by the feedback loop, the leakage current is constant. Thus, the same amount of current will leak from both sides of the capacitor, and the leakage effect will be canceled at the end of the integration. This technique is similar to chopper stabilization [26]; however, here the chopping and signal frequencies are the same, precluding use of a filter to remove undesirable signal components. In the IDC, switch timing must be accurately controlled to ensure leakage is balanced on the integrating capacitor. IV. CIRCUIT IMPLEMENTATION
C. Calibration of Reference Current Mismatch The constant in (10) accounts for the mismatch between and . A value for is needed to accurately recover the impedance information. Notice that if a constant DC current were injected into the system ( in Fig. 4), both plates of the integrating capacitor will charge, given has a 50% duty cycle. Thus, as described by (4) and (6), the output should be zero after cycles. Applying these conditions multiple reference clock during a calibration phase, from (10) becomes zero and , the desired calibration parameter, can be found by evaluating (12) where the counter values are readily obtained at the end of the calibration cycle. D. Integrator Leakage Tolerance The multiplying integrator not only realizes the multiplication function without a dedicated multiplier block, but it also eliminates the current leakage effect of the integrator through the source/drain contacts of the CMOS switches connected to it. For a typical analog integrator, leakage current at the op-amp’s negative input node steals charge from the integrating capacitor, and the integrator will lose information over time during integration. Thus, calibration is required to suppress this error in a typical integrator. However, in the new multiplying integrator, the integration capacitor is flipped back and forth by a square wave with a 50% duty cycle. Thus, the leakage current steals
A. Multiplying Integrator Amplifier At the heart of the multiplying integrator is an operational amplifier that must provide sufficient gain and bandwidth while adhering to the goals of compact size and low power consumption. The folded cascade op-amp structure shown in Fig. 6 was chosen to meet these requirements while provided a flexible input common mode range to support different sensors. This single stage amplifier does not require a Miller compensation capacitor, thus maintaining compact size. The circuit is designed to operate in the subthreshold region with a total current consumption of 1 A from a 3 V supply. This compact low-power op-amp is able to achieve a DC gain of 76 dB and a unity gain bandwidth of 800 kHz for a nominal 1 pF load, which is adequate for this application where the maximum clock rate is 100 kHz. The load capacitor value is set to 1 pF, which is large enough to suppress charge injected from the transistor switches connected to it but small enough that a 100 nA peak current can not saturate the integrator at maximum clock rate (100 kHz). B. Comparator To minimize the area impact of the two comparators in Fig. 4, the circuit shown in Fig. 7(a) was designed, combining the two comparator functions into one dual-level amplifier-based comparator. The two output stages utilize the same tail current and share a common input transistor to minimize hardware resources. The DC simulation in Fig. 7(b) shows the non-overlapping comparator output logic as a function of the sweeping
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Fig. 8. Schematic of a 1-bit bidirectional counter/shifter cell with bit inversion control for down counting.
Fig. 7. (a) Schematic of the dual-level comparator amplifier, and (b) DC sweep simulation result.
input voltage. Because the comparator operates at low speeds (maximum clock of 100 kHz), it was also designed to work in the subthreshold region to minimize power consumption. Dynamic comparators [28], [29] are also a good option for this application because they do not have static current consumption. However, they will require more hardware for switches and/or capacitors and thus were not chosen for this compact design.
imize hardware demands, an new algorithm-based counter was developed for the asynchronous bidirectional counter/shifter in the lock-in IDC. This circuit utilizes hardware that performs only single-direction counting along with an algorithm designed to control the up/down count direction. To describe the operation of the new algorithm-based bidirectional counter, consider an example of a 4-bit counter that must count down (minus 1) times. This can be expressed as (13) is the initial value of the counter. Equation (12) where can be rewritten as (14) Using 2’s complement representation, a negative sign operation can be performed by bitwise inversion and adding 1, such as
C. Bidirectional Counter/Shifter The final building block of the lock-in IDC is the bidirectional counter that tabulates and stores digitized results. This block must additionally permit the serial transfer of its stored results in order to accommodate implementation within a large array of IDC readout cells, as discussed in Section II. To realize these functions under the constraints of compact size and low power consumption, a counter/shifter structure [30], [31] was chosen. Because the maximum update clock rate is 100 kHz, an asynchronous counter was selected to save area and avoid unnecessary dynamic power consumption. A compact single-direction counter/shifter has been demonstrated [4] that achieves hardware efficiency by sharing hardware between the counter and shifter. However, IDC operation requires a dynamically configurable bidirectional counter, and adapting the structure in [4] would require significantly more complex control logic, especially for the number of bits needed by the IDC circuit. To min-
(15) Thus, using 2’s complements, (13) becomes
(16) where steps with show substitution with 2’s complement notation. Notice that the final result of (16) shows that counting down by can be achieved by two inversions and counting up by . A unit cell of the asynchronous bidirectional counter/shifter developed for the lock-in IDC is shown in Fig. 8, where all nMOS transistors are set to minimum size, 1.5 m/0.6 m. Based on the compact counter/shifter in [4], this new circuit
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Fig. 9. Waveform of the control signals for the bidirectional counter/shifter.
Fig. 10. Block diagram of a 20-bit up/down counter using the bidirectional counter/shifter cell.
TABLE I PERFORMANCE SUMMARY OF THE LOCK-IN IDC CIRCUIT
2
Fig. 11. Die photo of a 1.5 mm 1.5 mm prototype chip containing two lock-in IDC blocks and some test circuits.
also realizes the inversions necessary to implement the downcounting algorithm described by the 4-bit example in (15). In shifting mode, cnt_en is low and the non-overlapping shift_ph1 and shift_ph2 signals toggle to shift data through the cell. In up or down counting mode, both shift-ph1 and shift_ph2 are held low. nMOS transistors M1 and M2 realize the bit inversion necessary for down counting mode, where non-overlapping square pulses on inv_ph1 and inv_ph2 forced the latches and to invert their states. The pulse of inv_ph1 comes first to invert latch
, then the pulse of inv_ph2 lets latch invert. A timing diagram for the control signals of the bidirectional counter/shifter is shown in Fig. 9, which illustrates an up count, a down count, and a shift operation, in sequence. As described by (15), a down counting operation requires a bit inversion both before and after the counting step, as shown in the middle of Fig. 9. The complete 1-bit cell for the bidirectional counter/shifter requires only 22 transistors, fewer than a 28-transistor DFF from a typical standard cell library [32]. Furthermore, most of the transistors in Fig. 9 are NMOS, which helps to reduce the circuit size in an n-well CMOS process. This very compact 1-bit cell was used to construct a 20-bit bidirectional counters/shifters as shown in Fig. 11. Two of these 20-bit blocks are employed in the lock-in IDC (Fig. 4). The size of the counter is set to 20-bit so that the counter will not overflow at the low end of the target stimulus frequency. V. EXPERIMENTAL RESULTS The lock-in IDC circuit was implemented in a foundry 0.5 m CMOS process with a 3 V supply. As shown in Fig. 11,
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Fig. 12. Normalized IDC output values versus input signal initial phase () for 1 kHz 30 nA sinusoid current. This plot demonstrates the proper response of the IDC to variable input signal phase.
a full IDC cell occupies only 100 m 600 m. Therefore, in a 3 mm 3 mm silicon chip, this circuit could be instantiated more than 100 times, which is suitable for most existing and anticipated impedance sensor array platforms. In its operational mode, the IDC circuit consumes only 2 A, thus permitting very low power consumption even in high density arrays. These results are summarized in Table I along with other lock-in IDC performance characteristics described below. The IDC was designed for low frequency impedance measurements and has been tested over a 1 mHz to 10 kHz range; the design could readily be adapted to higher frequency applications by extending the op-amp’s bandwidth and increasing the updating clock rate. The IDC analyzes a sensor’s response current and extracts the real and imaginary portions of its admittance, which are related at certain frequency by (1) to signal phase and amplitude. To characterize the response of the IDC to input phase and amplitude variations, separate measurements were performed where one parameter was swept while the other was held constant. The phase response and the amplitude response of the IDC are described below. As described by (1) and (2), for a current input with a constant and frequency , the relationship between the amplitude and the real (a) or imaginary (b) response relative phase shift components should be a sinusoid waveform. To characterize this relationship, sinusoid current signals with constant amplitude and variable initial phase (relative to the square wave reference) were fed into the lock-in IDC. The IDC’s outputs, normalized to the peak value, were recorded as a function of the initial phase of the input signals. With the lock-in IDC configured to measure the imaginary component, the results for a 1 kHz sinusoid input current with a 30 nA amplitude are plotted in Fig. 12. The theoretically predicted curve from (2) is also plotted in Fig. 13. The measured results were observed to fit the theoretical curve very well, with an RMS error of only 0.027, demonstrating the IDC accurately extracts the imaginary portion of the response current. Inherently, in terms of the circuit operation, the operation to generate the real component is the same as that of the imaginary component. The only difference is that the square wave reference is phase shifted by 90 degrees between real and imaginary component extractions. Therefore, the results for the real component generate a curve that is shifted by 90 degrees from
Fig. 13. Lock-in IDC amplitude transfer performance with respect to the maximum output: (a) DNL; (b) INL. 1024 data points were taken from 0–100 nA amplitude. These results demonstrate the proper response of the IDC to variable input signal amplitude.
the Fig. 12 plot. No obvious dependency between the RMS error and the reference frequency was observed. To demonstrate the IDC’s response to variable input amplitude, notice that (1) and (2) show a linear relationship should exist between the input amplitude and the real or imaginary component output, given the input has constant frequency and phase. Thus, the linearity and accuracy of the lock-in IDC’s amplitude conversion can be quantified by the integral nonlinearity (INL) and differential nonlinearity (DNL) parameters commonly analyzed for high performance analog-to-digital converters. A 10 Hz sinusoid signal with zero phase delay was injected into the IDC, and the amplitude of the sinusoid current input was swept from 100 nA to 0 nA in 1024 steps. With a 100 kHz updating clock, there are 10,000 clock cycles for the measurement. With the lock-in IDC set to extract the real component, the measured INL and DNL are plotted in Fig. 13. These results demonstrate a 50 dB dynamic range (8-bit) for the 100 nA input range. Although several factors impact the accuracy of the lock-in IDC, our observations suggest that the two major limitations are charge injection of the switches and signal coupling at the input nodes. The lock-in IDC can be configured to accommodate a wide dynamic range of input signal strengths in order to support a
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Fig. 15. Test setup for the biosensor measurements using the prototype lock-in IDC chip.
Fig. 14. Amplitude conversion characteristics for a zero phase sinewave input. The lock-in IDC can be configured to accommodate a wide range of input signal strengths, two of which are shown here.
variety of sensors. The signal range is determined by on chip settings that control the magnitude of the two reference currents and the frequency of the updating clock. To test the achievable dynamic range, an input test current was generated by applying a sinusoidal voltage to a capacitor and sweeping its amplitude. In order to generate appropriate inputs using available off-theshelf capacitors, the sinusoidal voltage was set to 0.1 Hz for the lowest current range. For the largest current range, it was set to 1 Hz. Fig. 14 plots the IDC output codes as a function of the input current amplitude for these two boundary ranges of input signal strength. The results show that currents ranging from below 100 fA to 100 nA can be converted, with a maximum sensitivity (minimum linear response) at 78 fA. VI. BIOSENSOR MEASUREMENTS The IDC circuit was designed to enable the development of a monolithic microsystem that extracts the impedance of an on-chip sensor array. To demonstrate the IDC circuit’s capabilities in such a system, a hybrid impedance sensor platform described by Fig. 15 was implemented for rapid prototyping. A data acquisition card (Agilent E3630A) was connected to a computer and employed to generate the sensor stimulus sinusoid and collect output data from the IDC. Here, we demonstrate the use of the IDC circuit for electrochemical biosensing via ion transport activity of a membrane protein incorporated in an artificial bilayer lipid membrane (BLM) interface. BLM interfaces are useful in functional proteomics research to characterize novel membrane proteins and can be used to develop membrane protein biosensors for many applications including high-throughput drug screening. In our sensor, tethered BLMs (tBLM) embedded with gramicidin ion channel protein are deposited on gold electrodes patterned on a glass chip [33], [34]. Briefly described, a self-assembled monolayer (SAM) of 1,2-dipalmitoyl-sn-glycero-3-phosphothioethanol (DPPTE) tether lipid was formed on a clean gold electrode patterned on the glass chip. The upper leaflet of bilayer membrane was deposited by fusion of liposome vesicles made of
1,2-dioleoyl-sn-glycero-3-phosphocholine (DOPC) mobile lipids. Bilayer lipid membrane acts as an insulating dielectric barrier for ion transport, thereby increasing the impedance of gramicidin the bio-interface. After tBLM formation, 1 ion channel protein was introduced to the electrolyte solution to incorporate gramicidin ion channels in tBLM. Gramicidin selectively transports alkali metal ions through the tBLM and therefore lowers the impedance of the modified tBLM in the presence of alkali metal ions in the electrolyte solution. Impedance measurements were conducted with the IDC chip over the frequency range of 10 mHz to 100 Hz while the biosensor was being formed; first the DPPTE monolayer, then the tBLM, and finally the gramicidin modified tBLM in 100 mM sodium chloride solution, immediately after their formations.Fig. 16 shows the impedance data obtained from the IDC chip for one biosensor element as a function of frequency. The impedance data was fit using ZView software (Scribner Associates, Inc.) to the modified Randle’s equivalent circuit shown in Fig. 17. The equivalent circuit is a combination of resistors and capacitors that can be related to the physical properties of the biosensor interface. The membrane capacitance and resistance were modeled in parallel to represent the properties of the bilayer membrane. For a DPPTE monolayer, and values were measured to be 0.635 F cm the and 20 K cm respectively. For the tBLM, a and of 0.505 F cm and 425 K cm were obtained. The capacitance value for the tBLM is in good agreement with the reported values for high quality BLMs [33]. Fig. 16 also shows that incorporation of gramicidin in the tBLM decreased the membrane resistance from 425 to 59 K cm due to the gramicidin mediated passage of sodium (alkali metal) ions through the tBLM. These measurements demonstrate that the compact IDC circuit can successfully characterize the impedance spectra of sensor materials. The drop in membrane resistance is a direct measure of the ion transport activity of gramicidin channels. The measurements of electrochemical properties of tBLM and ion transport activity of gramicidin are in agreement with those made by commercial instruments [34]. The measurement of ion transport activity of a channel membrane protein on an array using the IDC chip provides an efficient design for high throughput screening platforms. A future generation of the chip containing a large array of IDC cells would be capable of measuring many sensor elements simultaneously, rapidly extracting
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instantiated with each element of a sensor array. The circuit locally extracts and digitizes sensor impedance information using mixed-mode signal processing, eliminating the cost, power, and size of the external hardware typically employed to analyze raw sensor data. The circuit was fabricated in a with standard 0.5 m CMOS process. It consumes only 6 a 3 V supply and occupies only 0.06 mm per cell, permitting over 100 cells within a 3 3 mm chip. Tests show that the impedance-to-digital converter provides over 50 dB of amplitude conversion linearity and exhibits less than 2.7% RMS phase conversion error. It can accommodate sensor current inputs ranging from 78 fA to 100 nA, suitable for a diversity of bio- and nano-materials. The capabilities of the new circuit were verified in a prototype microsystem where it successfully measured the impedance spectrum of a miniaturized membrane protein (gramicidin) biosensor. The current design supports impedance extraction up to 10 kHz, and the architecture is adaptable to higher frequency applications with adjustments to op-amp bandwidth and updating clock frequencies. The lock-in IDC circuit demonstrates that high density impedance sensor arrays can feasibly be implemented on a single chip. ACKNOWLEDGMENT The authors would like to thank Y. Huang for preparing the microelectrodes in the biosensor experiment and D. Rairigh for consulting on design issues. REFERENCES
Fig. 16. Biosensor impedance as a function of frequency measured by the lock-in IDC: (a) impedance amplitude and (b) phase angle. Measurements were performed at three phases of the biosensor self assembly; the DPPTE tethering lipid monolayer (diamonds), tBLM (squares), and tBLM after gramicidin incorporation (rectangles). As expected, the membrane resistance increases after bilayer formation (relative to the DPPTE monolayer) and then decreases after gramicidin incorporation due to the transport of sodium ions across the bilayer membrane.
[1] Y. Huang and A. Mason, “Post CMOS compatible microfabrication of a multi-analyte bioelectrochemcial sensor array microsystem,” in Proc. IEEE Int. Conf. Sensors, Dageu, Korea, 2006, pp. 612–615. [2] A. Hassibi and T. H. Lee, “A programmble 0.18 m CMOS electrochemcial sensor microarray for biomolecuar detection,” IEEE Sensors J., vol. 6, pp. 1380–1388, Dec. 2006. [3] K. S. Yun, H. J. Kim, S. Joo, J. Kwak, and E. Yoon, “Analysis of heavymetal ions using mercury microelectrodes and a solid-state reference electrode on a Si wafer,” Jpn. J. Appl. Phys. Part 1-Reg. Papers, Short Notes and Review Papers, vol. 39, pp. 7159–7163, Dec. 2000. [4] M. Schienle et al., “A fully electronic DNA sensor with 128 positions and in-pixel A/D conversion,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2438–2445, Dec. 2004. [5] B. Eversmann et al., “A 128 128 CMOS biosensor array for extracellular recording of neural activity,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2306–2317, Dec. 2003. [6] X. Zhu and C. H. Ahn, “On-chip electrochemical analysis system using nanoelectrodes and bioelectronic CMOS chip,” IEEE Sensors J., vol. 6, pp. 1280–1287, May 2006. [7] M. Trojanowicz, “Miniaturized biochemical sensing devices based on planar bilayer lipid membranes,” Fresenius’ J. Analyt. Chem., vol. 371, pp. 246–260, Feb. 2001. [8] B. Hassler et al., “Biomimetic interfaces for a multifunctional biosensor array microsystem,” in Proc. IEEE Int. Conf. Sensors, Vienna, Austria, 2004, pp. 991–994. [9] G. Hagen, A. Dubbe, G. Fischerauer, and R. Moos, “Thick-film impedance based hydrocarbon detection based on chromium (III) oxide/zeolite interfaces,” Sens. Actuators B, Chem., vol. 118, pp. 73–77, Oct. 2006. [10] K. Ogura, T. Tonosaki, and H. Shiigi, “AC impedance spectroscopy of humidity sensor using poly (o-phenylenediamine)/poly (vinyl alcohol) composite film,” J. Electrochem. Soc., vol. 148, pp. H21–H27, Mar. 2001. [11] J. S. Daniels and N. Pourmand, “Label-free impedance biosensors: Opportunities and challenges,” Electroanalysis, vol. 19, pp. 1239–1257, May 2007. [12] G. S. Popkirov and R. N. Schindler, “A new impedance spectrometer for the investigation of electrochemical systems,” Rev. Sci. Instrum., vol. 61, pp. 5366–5372, Nov. 1992.
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Fig. 17. Modified Randle’s equivalent circuit for a tBLM electrochemical biosensor: C represents the capacitance of membrane, R represents the resistance of membrane, and C represents the capacitance of double layer that includes the Hemholtz capacitance.
their characteristic impedance and generating a digital result at each desired frequency. VII. CONCLUSION A very compact, low power, impedance-to-digital converter circuit has been introduced. Tailored for on-chip sensor array microsystems, the impedance spectroscopy circuit can be
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[13] M. Min, O. Martens, and T. Parve, “Lock-in measurement of bio-impedance variations,” Measurement, vol. 27, pp. 21–28, Jan. 2000. [14] M. Min and T. Parve, “Improvement of lock-in bio-impedance analyzer for implantable medical devices,” IEEE Trans. Instrum. Meas., vol. 56, pp. 968–974, Jun. 2007. [15] D. Rairigh, C. Yang, and A. Mason, “Analysis of on-chip impedance spectroscopy methodologies for sensor arrays,” Sensor Lett., vol. 4, pp. 398–402, Apr. 2006. [16] M. L. Meade, Lock-in Amplifiers: Principles and Applications. London, U.K.: Peter Peregrinus, 1983. [17] C. Yang, D. Rairigh, and A. Mason, “Fully integrated impedance spectroscopy for biochemical sensor arrays,” presented at the IEEE Biomedical Circuits and Systems Conf., Montreal, Canada, 2007. [18] C. Yang and A. Mason, “Fully integrated 7-order frequency range quadrature sinusoid signal generator,” IEEE Trans. Instrum. Meas., 2009, to be published. [19] U. Gatti, F. Maloberti, and G. Torelli, “CMOS triode-transistor transconductor for high-frequency continuous-time filters,” in Proc. IEE Circuits, Devices and Systems, Dec. 1994, vol. 141, pp. 462–468. [20] Z. Wang, “A four-transistor four-quadrant analog multiplier using MOS transistors operating in the saturation region,” IEEE Trans. Instrum. Meas., vol. 42, pp. 75–77, Feb. 1993. [21] Z. Hong and H. Melchior, “Four-quadrant CMOS analog multiplier,” Electron. Lett., vol. 20, pp. 1015–1016, Nov. 1984. [22] K. Kimura, “An MOS four-quadrant analog multiplier based on the multitail technique using a quadritail cell as a multiplier core,” IEEE Trans. Circuits Syst. I, vol. 42, pp. 448–454, Aug. 1995. [23] T. Serrano-Gotarredona, B. Linares-Barranco, and A. G. Andreou, “A general translinear principle for subthreshold MOS transistors,” IEEE Trans. Circuits Syst. I, Fundam. Theory Applicat., vol. 46, pp. 607–616, May 1999. [24] A. Pesavento and C. Koch, “A wide linear range four quadrant multiplier in subthreshold CMOS,” in IEEE Int. Conf. Circuits and Systems, San Francisco, CA, 1999, pp. 240–243. [25] B. A. D. Cock, D. Maurissens, and J. Cornelis, “A CMOS pulse-width modulator/pluse-amplitude modulator for four-quadrant analog multipliers,” IEEE J. Solid-State Circuits, vol. 27, no. 9, pp. 1289–1293, Sep. 1992. [26] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: Autozeroing, correlated double sampling, and chopper stabilization,” Proc. IEEE, vol. 84, no. 11, pp. 1584–1614, Nov. 1996. [27] J. Candy and G. Temes, “Oversampling methods for A/D and D/A conversion,” in Oversampling Delta-Sigma Data Converters. New York: IEEE Press, 1992. [28] T. Cho and P. Gray, “10 bit 20 Msamples/s, 35 mW pipeline A/D converter,” IEEE J. Solid-State Circuits, pp. 166–172, Mar. 1995. [29] L. Sumanen, M. Waltari, V. Hakkarainen, and K. Halonen, “CMOS dynamic comparators for pipeline A/D converters,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), Scottsdale, AZ, 2002, pp. 157–160. [30] G. E. Hack, “Binary up/down counter,” IBM Tech. Discl. Bull., vol. 24, pp. 4399–4400, Aug. 1982. [31] X. D. Lu and P. C. Treleaven, “A special-purpose VLSI chip: A dynamic pipeline up-down counter,” Microprocess. Microprogram., vol. 10, pp. 1–10, Aug. 1982. [32] “Digital Low Power Standard Cell Library for MOSIS AMI 0.5 m Sub-Micro Process,” Tanner Research, Inc. [Online]. Available: http:// www.mosis.com/cell-libraries/scn05-std-cells/mAMIs05DLs.pdf [33] B. Raguse et al., “Tethered lipid bilayer membranes: Formation and ionic reservoir characterization,” Langmuir, vol. 14, pp. 648–659, Feb. 1998. [34] V. Atanasov et al., “Membrane on a chip: A functional tethered lipid bilayer membrane on silicon oxide surfaces,” Biophys. J., vol. 89, pp. 1780–1788, Sep. 2005.
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Chao Yang received the B.S. and M.S. degrees in electrical engineering from Tsinghua University, Beijing, China, in 1999 and 2002, and the Ph.D. degree in electrical engineering from Michigan State University, East Lansing, MI, in 2008. Currently, he is with Marvell Semiconductor, Inc., Austin, TX. His research focus is the RF/analog/mixed-signal IC design, the biomedical and biochemical instrumentation microsystem. Dr. Yang was the recipient of the Excellence Scholarships from Tsinghua University from 1996 to 1998 and that of the VLSI/SOC Fellowship from Michigan State University in 2007. He won the third (out of 40) Place Awards in both phase-1 and phase-2 SRC (Semiconductor Research Corporation)/SIA (Semiconductor Industry Association) SoC Design Challenge.
Sachin R. Jadhav received the B.S. degree in pharmaceutical sciences from Amravati University, Amravati, India, in 2002, and the M.S. degree in bioprocess technology from the University of Mumbai, Mumbai, India, in 2004. He is currently pursuing the Ph.D. degree in chemical engineering at Michigan State University, East Lansing, MI. His research interests include protein purification, proteins’ functional characterization, and high-throughput biosensing.
R. Mark Worden received the B.A. degree with a double major in chemistry and cell biology in 1979, the M.S. degree in chemical engineering in 1982, and the Ph.D. degree in chemical engineering in 1986, all from the University of Tennessee in Knoxville. The research for his M.S. and Ph.D. degrees was conducted in the Bioprocess Engineering group at Oak Ridge National Laboratory in Oak Ridge, TN. He became an Assistant Professor in the Department of Chemical Engineering and Materials Science at Michigan State University in East Lansing, MI, in 1986, and was promoted to Associate Professor in 1991, and then Professor in 1998. His research program integrates recombinant-protein production, biocatalysis, and nanotechnology to develop new systems for bioproduction, biosensing, and bioremediation. His current projects include use of electrochemical sensor arrays for high-throughput biosensor systems and functional proteomics.
Andrew J. Mason (S’90–M’99–SM’06) received the B.S. degree in physics with highest distinction from Western Kentucky University, Bowling Green, in 1991, the B.S.E.E. degree with honors from the Georgia Institute of Technology, Atlanta, in 1992, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 1994 and 2000, respectively. From 1999 to 2001, he was an Assistant Professor at the University of Kentucky. In 2001, he joined the Department of Electrical and Computer Engineering at Michigan State University in East Lansing, Michigan, where he is currently an Associate Professor. His research addresses many areas of mixed-signal circuit design and the fabrication of integrated microsystems. His current projects include compact low-power bioelectrochemical interrogation circuits, adaptive chemical sensor interface circuits, post-CMOS fabrication of electrochemical sensor arrays, and mixed-signal integrated circuits for signal processing in neural implants. Dr. Mason serves on the Sensory Systems and Biomedical Circuits and Systems Technical Committees of the IEEE Circuits and Systems Society and on the technical program committee for several IEEE conferences and workshops. During 2008–2009, he was a guest Associate Editor of the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS. He is a recipient of the 2006 Michigan State University Teacher-Scholar Award.
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Compact Low-Power Impedance-to-Digital Converter for Sensor Array Microsystems Chao Yang, Sachin R. Jadhav, R. Mark Worden, and Andrew J. Mason, Senior Member, IEEE
Abstract—With the rapid progress in CMOS compatible microfabrication of biosensors, there is an emerging need to miniaturize biosensor arrays onto the surface of silicon chips that acquire and process sensor data, permitting improved sensitivity, cost and throughput. In this paper, a low power circuit that extracts and digitizes sensor impedance information is presented. Composed of a novel multiplying integrator and a unique bidirectional counter/shifter, the circuit shares resources for impedance extraction and digitization to maximize hardware efficiency. The extremely compact size of the circuit enables the implementation of sensor array microsystems with simultaneous multi-channel readout. Fabricated in 0.5 m CMOS, the circuit consumes 6 at 3 V and occupies only 0.06 mm2 , permitting over 100 readout channels within a 3 3 mm die. Circuit performance has been verified with a biosensor for gramicidin ion channel embedded in a tethered bilayer lipid membrane.
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Index Terms—Biosensor array, electrochemical instrumentation, impedance spectroscopy, impedance-to-digital converter.
I. INTRODUCTION
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INIATURIZED sensor arrays enable parallel analysis of multiple parameters. With advances in CMOS compatible fabrication of microelectrodes [1], [2], there is a trend to build sensor array microsystems that realize miniaturized sensor elements on the surface of silicon chips and interrogate these elements with on-chip electronics [3]–[6]. By eliminating the need for bulky bench-top instruments, a sensor array microsystem not only lowers cost but also enables many applications outside of highly specialized laboratories, revolutionizing numerous sensor platforms, such as DNA testing, drug screening, and security monitoring. Many new and emerging sensor technologies, particularly those based on bio- and nano-materials rely on impedance spectroscopy (IS) to elucidate the information contained within its impedance response over a range of stimulus frequencies. For example, ion channel membrane protein biosensors require IS [7], [8]; some gas sensors [9] and humidity sensors [10] are also interrogated through IS; even DNA sensors can be analyzed by tracking the capacitive component of impedance [4] These technologies are Manuscript received September 04, 2008; revised January 18, 2009. Current version published September 28, 2009. This paper was approved by Associate Editor Kari Halonen. This work was supported by the Engineering Research Centers Program of the National Science Foundation (NSF) under Award Number EEC-9986866 and by NSF Award Number DBI-0649847. C. Yang was with Michigan State University, East Lansing, MI 48824 USA, and is now with Marvell Semiconductor, Austin, TX 78746 USA (e-mail: [email protected]). S. R. Jadhav, R. M. Worden, and A. J. Mason are with Michigan State University, East Lansing, MI 48824 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2009.2028054
Fig. 1. Conceptual structure of an integrated impedance-based sensor array microsystem.
ideally suited for miniaturized arrays that permit multi-parameter sensor fusion and improve measurement accuracy [11]. However, neither commercial impedance extraction systems nor those recently reported for biomedical and biochemical measurement [12]–[14] support multi-channel sensor arrays. Furthermore, existing IS systems do not permit miniaturization to the scale necessary for hand-held, point-of-care, or even smaller devices required for implantable applications. Although there is a clear need for chip-scale integration of sensor arrays and impedance readout electronics, this realization is challenged by the heavy signal processing load associated with multi-channel impedance extraction [15]. To overcome this obstacle, highly efficient hardware structures must be developed. This paper presents a compact, high-sensitivity impedanceto-digital converter (IDC) developed to extract sensor information in array microsystems. An example impedance array microsystem is shown in Fig. 1, where a sensor array is formed on the surface of an integrated circuit chip equipped for IS measurement. Ideally, each element of the array would have its own front-end IS circuit to allow simultaneous multi-channel measurement, as illustrated in Fig. 2. Compared to the alternative of a single time-multiplexed readout circuit for the entire array, this approach enables rapid interrogation of the array, improves sensor throughput, eliminates leakage due to analog multiplexers (potentially larger than a sensor’s small response), and permits the simultaneous measurements necessary to correlate data from multiple sensors. To realize such a platform, each IDC block must: 1) be implemented with minimum silicon footprint to sustain tens to hundreds of sensors per chip; 2) be capable of locally extracting impedance information from raw data to distribute the heavy signal processing workload and reduce data transmission bandwidth requirements; 3) digitize
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The lock-in IDC measures and digitizes the sensors’ admittance information, and , one at a time in sequential cycles. To accomplish this, the lock-in IDC requires a square wave reference signal, which is either in phase with the stimulus (for extracting the real component, ), or in quadrature phase with the stimulus (for extracting the imaginary component, ). Digital counters are employed within the lock-in IDC to assist in the signal processing and store digital output values. These counters can also be reconfigured to operate as output shifters, recycling the counter hardware during serial data output. B. Hardware Efficient Impedance Extraction Algorithm Fig. 2. Block diagram of a multi-channel impedance spectroscopy microsystem. Each sensor element has an IS readout circuit digitalizes the sensor response and stores it onto a shift register chain.
data locally to facilitate system integration; 4) consume low power to avoid overheating sensor materials and extend battery life in portable applications; and 5) accept a wide input current dynamic range (sub-picoampere to tens of nanoamperes) to accommodate a diversity of miniaturized sensors. The new IDC circuit that overcomes the challenges and achieves the objectives outlined above is described in this paper. Section II describes the function of the IDC circuit and explains the algorithm for the new impedance extraction approach. The IDC architecture and VLSI realization are described in Sections III and IV. Test and characterization results for the IDC circuit are presented in Section V, and test results from a prototype miniaturized biosensor system are discussed Section VI. II. PRINCIPLES OF IMPEDANCE EXTRACTION A. Principles The newly developed circuit extracts and digitizes a sensor’s impedance response over frequency, up to 10 kHz to suit a wide range of sensor materials. Because the circuit utilizes a reference signal of the same frequency as the stimulus, it is similar in function to a lock-in amplifier [16] and will be referred to as a lock-in impedance-to-digital converter. As shown in Fig. 3, this lock-in IDC converts the real and imaginary portions of a sinusoidal current into a digital value. A digital clock is required to synchronize the internal signal processing. The input current, , is the response of a sensor to a sinusoid voltage stimulus of . The amplitude, , and phase, , of the input response current contain the sensor’s impedance information. can also be represented as the sum of cosine and sine components given by
Several approaches are available to perform the IS. They can be sorted into two primary categories: Fast Fourier Transform (FFT) IS and Frequency Response Analyzer (FRA) IS [15], [17]. FFT-based methods rely on digital signal processing to extract frequency components from a broadband (e.g., pulse) stimulus. They are hardware intensive and not suitable for compact, single-chip realization FRA-based methods measure impedance for a single frequency point at a time, and the required hardware can more readily be reduced to chip scale. Thus, lock-in IDC is based on the FRA algorithm. A functional block diagram of the IDC is shown in Fig. 3. The lock-in IDC performs the multiplication and integration required for the FRA algorithm as well as the digitization of the result. The main difference between a traditional FRA IS system and the lock-in IDC is that, instead of using an analog sinusoid reference input, the IDC uses square waves of the same phase and frequency to perform the lock-in detection [15], [17]. This modification is key to permitting a compact VLSI implementation. There are several methods the square wave signal could readily be generated, including zero crossing detection of a reference sinusoid signal [18]. Zero crossing detecting could introduce delay (phase error), but within the frequency range of interest for biosensors (less than 10 kHz), the error due to this delay is negligible. After the integration operation, the real or imaginary portion (selectable) of the input sinusoid response current appears at the integrator’s output as a DC signal. (Fig. 3), the multiplier square wave reference When , signal, , is in phase with the sensor stimulus signal, and is described by (3) where is the period of the stimulus and is a integer. Ascan be represented by suming the sensor’s response current , the integrator’s output at the end of continuous stimulus cycles is
(1) where coefficients and represent the real and imaginary portion of the sensor’s admittance (the reciprocal of impedance), respectively. The relationship between these coefficients and information is (2)
(4) When compared with (2), it can be seen that the result is proportional to the real portion of the sensor’s admittance. Alterna-
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Fig. 3. Functional block diagram of a lock-in IDC block illustrating its impedance extraction algorithm.
Fig. 4. Principal schematic of the lock-in IDC circuit.
tively, when , the square wave reference is in phase with and its function is given by else For the same result at the end of
(5) sensor response, the integrator’s continuous stimulus cycles is
(6) Based on (2), this result is proportional to the imaginary portion of the sensor’s admittance. This adaptation of the FRA algorithm enables a compact mixed-signal VLSI realization. In particular, the analog multiplier implementation can be significantly simplified because multiplication is performed between an analog current and a digital signal.
III. ARCHITECTURE OF THE LOCK-IN IDC Realizing the algorithm shown in Fig. 3 in a chip-area efficient manner is necessary to support simultaneous multi-channel readout of a sensor array. This can only be achieved by a lock-in IDC that shares hardware resources among different functions. A multiplying integrator was developed to share hardware between multiplication and integration functions. In addition, a bidirectional digital counter was designed that could share the functions of extending the output range of the multiplying integrator, storing the digitized result, and shifting digital data out after the readout cycle. A. Multiplying Integrator Many analog multiplier structures have been developed, including CMOS analog multipliers utilizing the drain current square law [19]–[22] or subthreshold trans-linear principles [23], [24], and modulation based analog multipliers [25]. All of these multiplier circuits require dedicated hardware including related bias or control circuits. To minimize the footprint of the IDC circuit, a new multiplier structure, shown in Fig. 4, has been implemented that shares the hardware resources necessary to implement the integration function. In Fig. 3, the lock-in IDC reference signal is a digital square wave with values between 1 and , and the sensor’s response
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is an analog current . To implement the impedance extraction algorithm, these two signals must be multiplied. Multiplication of a current with the digital square wave could be realized by frequently changing the direction of the current according the digital square wave value. Although the direction of sensor response current can not be reversed directly, a reverse-direction copy could be generated through current mirroring. However, resolution would be lost due to mirroring mismatch. To avoid this detrimental effect, the polarity of the following integrator stage could be changed, which has the same effect as flipping the current direction. As a result, this flipping integrator realizes the multiplication function without a dedicated multiplier. Because analog integrators have a limited output range, two comparators and counters are employed to extend the output range and digitize integrating results. This approach was found to be effective and efficient and was adopted. This square-wave multiplication concept is similar to the up-converting or demodulation operation in chopper stabilization techniques [26], where two square-wave multipliers are employed to up-convert the input signal to higher frequency noise and op-amp and later demodulate it to eliminate offset of. With chopper stabilization, to accurately recover the signal after demodulation with a simple filter, the square-wave clock frequency has to be much higher than signal bandwidth. However, in the lock-in IDC, the square-wave clock has to be the same as the input signal frequency, and we only need one square-wave multiplier. The resulting architecture resembles a first order sigma delta modulator [27], where an integrator, comparator and counters are also employed, with several differences including the need to flip the integrator, use of two comparator, and inclusion of counters. B. Hardware Sharing Architecture A simplified schematic of the new lock-in IDC is shown in Fig. 4, where is the reference square wave (see Fig. 3) and CLK is an external clock that synchronizes the system operation. In Fig. 4, the circuit in shaded area is the multiplying integrator that can change its polarity according to . Portions of this circuit are also shared with other blocks to realize the digitization function. Two comparators are employed to monitor the ) are integrator output. The results of the comparators ( and stored in two -type flip flops (DFF) at each rising edge of the CLK signal. Once the integrator output is outside of a predefined , either or becomes high and draws the range set by or integrator output back within range by feeding either into the input. and are designed to be equal in magnitude with opposite polarity, and any mismatch in magnitude can be accounted for in calibration, as discussed below. To store the digitized value, two multi-mode bidirectional counters are employed. Their counting mode (up/down counting) is controlled by ; the counter is in up counting mode when is high and in down counting mode when is low. At the end of the readout operation, the contents of these two counters are the digitized results. The signal waveforms shown in Fig. 5 may be helpful to understand the description of operation that follows. 1) Operation Principles: To improve accuracy, the switch in Fig. 4) was denetwork around the DFFs (shaded area signed in a unique manner. To explain the switch network op-
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eration, let us first consider just one stimulus signal cycle (the principle is the same for multiple cycles) and initially assume are low. The other that at any transition edge both and cases will be discussed later. Assume is in phase with , as in (3). The counters and integrating capacitor are reset at time , is 1, and just before ’s edge at time 0. From time 0 to , applying charge conservation at the input node, we have (7) is the residue value at the integrator output, is where the updating clock period, is the number of clock cycles from time 0 to . Here, the counters are set to up-counting mode , the contents of the positive because is high. At time is the summation of ’s, and the negative counter counter holds the summation of since they were reset at time 0. Both summations are represented in the right-hand side of (7). , the integrator capacitor is flipped and the inteAt time . From time to (just begrator output becomes fore and ’s rising edge), integrator operation is defined by
(8) represents the integrator output voltage at time where (before ’s rising edge). At time , goes high, the integrator capacitor is flipped back, and the integrator output becomes . For the second half cycle, while is low, the counters are set to down-counting mode. The initial value in the and counters are and , respectively. At time , and counter concounter contains . tains The result over the entire period from 0 to can be determined by subtracting (8) from (7), yielding
(9) which shows that the result is determined by the residue value on the integrator and the contents in the two counters. When design parameters ( , , and ) are chosen such that
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Fig. 5. Simulated waveforms of control signals in the lock-in IDC. The interrogation frequency is 1 kHz. The interval around '’s transition edge is magnified below.
, the analog residue can be ignored and treated as noise, and the result is represented digitally by the values in the counters. Referring to (4), notice also ) is, proportional that this result (where is in phase with to the real portion of the input signal. The value of the real portion can be retrieved from the digitized results by evaluating (10) and are the digital values where stored in the two counters and accounts for any mismatch of and ). The value of can the two reference currents ( be determined by calibration, as discussed below. . The results above assumed that was in phase with , it can be shown Alternatively, if is in phase with in a similar derivation that the counter results will contain the digitized imaginary portion of the input signal. The value of the imaginary portion can also be recovered using (10). Thus, the circuit can extract both the real and imaginary components of the response current simply by setting the digital value of in Fig. 3. Thus far, operation of the lock-in IDC has been explained for a single stimulus cycle only. The digital output dynamic range is controlled by in (9), which is given by (11)
are the periods of the stimulus and updating where and clock, respectively. For many of the biosensor applications, 8-bit resolution is more than sufficient. Thus, we choose such . In this design, the update clock rate was chosen that to be 100 kHz so that a 100 nA input current (maximum supported) will not saturate the integrator (with a 1 pF capacitor) over a clock period. Within the targeted reference frequency range(1 mHz to 10 kHz), this update clock can only guarantee 8-bit or higher resolution in one stimulus cycle for the refer. For ence frequency of 390 Hz and below, where frequencies above the 390 Hz, after an initial reset, the circuit is operated for multiple consecutive stimulus cycles ( cycles). In this case, the analog residue term in (9) retains (roughly) its single cycle magnitude, but the digital value stored in the counters is magnified by M. Thus, the digital output dynamic range is improved. The value of M can be chosen to obtain the desired resolution at the maximum frequency of interest. At the maximum reference frequency (10 kHz), with update clock of 100 kHz, M must be greater than 26 to achieve 8-bit resolution. 2) Reference Current Exchange: In the derivation above, were assumed to be low at the transition edge both and of . To analyze the other potential cases, consider that, when either or is high, they switch in the reference current to inject a compensating charge at a constant rate (defined by magnior ), thus forcing the integrator tude reference current voltage output back within range. If the integrating capacitor’s
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polarity is changed (due to ’s edge) while or is high, the compensating current must also been reversed; otherwise, it will produce an error of up to one digitization step for each stimulus cycle. This error will accumulate for multiple stimulus cycles. To eliminate this error, the multiplexing switches at the inputs and outputs of the two DFFs (shaded area in Fig. 4) have been inserted to appropriately adjust the reference current polarity. If or is high when ’s edge arrives, these switches either to exchange their status (values), thus changing force and the polarity of charge injection by the reference currents for the remainder of the clock cycle. Fig. 5 shows the simulated waveforms of the signals responsible for this feature along with the in Fig. 4). Here, the input siintegrator’s analog output ( frequency is 1 kHz, the system is reset at nusoid current time 100 s, and is in phase with the sine stimulus signal. In this example, right before goes low, is high and the inte. When goes low, and grator is being charged by exchange their status; thus becomes high, and the integrator for rest of the cycle. Without this reference is charged by current exchange during the flipping of the integrator, an error up to one digitization step (one counter step) can be generated. This exchange improves the accurate significantly. This feature and having the same magnitude. Although relies on fabrication will generate some mismatch between these two currents, it can easily be controlled within 1%, which permits the error associated with flipping the integrator to be less than 1% of one digitization step using this reference current exchange feature.
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Fig. 6. Operational amplifier schematic for the multiplying integrator.
charge from both plates of the capacitor. Because the voltage at the op-amp’s negative input is set by the feedback loop, the leakage current is constant. Thus, the same amount of current will leak from both sides of the capacitor, and the leakage effect will be canceled at the end of the integration. This technique is similar to chopper stabilization [26]; however, here the chopping and signal frequencies are the same, precluding use of a filter to remove undesirable signal components. In the IDC, switch timing must be accurately controlled to ensure leakage is balanced on the integrating capacitor. IV. CIRCUIT IMPLEMENTATION
C. Calibration of Reference Current Mismatch The constant in (10) accounts for the mismatch between and . A value for is needed to accurately recover the impedance information. Notice that if a constant DC current were injected into the system ( in Fig. 4), both plates of the integrating capacitor will charge, given has a 50% duty cycle. Thus, as described by (4) and (6), the output should be zero after cycles. Applying these conditions multiple reference clock during a calibration phase, from (10) becomes zero and , the desired calibration parameter, can be found by evaluating (12) where the counter values are readily obtained at the end of the calibration cycle. D. Integrator Leakage Tolerance The multiplying integrator not only realizes the multiplication function without a dedicated multiplier block, but it also eliminates the current leakage effect of the integrator through the source/drain contacts of the CMOS switches connected to it. For a typical analog integrator, leakage current at the op-amp’s negative input node steals charge from the integrating capacitor, and the integrator will lose information over time during integration. Thus, calibration is required to suppress this error in a typical integrator. However, in the new multiplying integrator, the integration capacitor is flipped back and forth by a square wave with a 50% duty cycle. Thus, the leakage current steals
A. Multiplying Integrator Amplifier At the heart of the multiplying integrator is an operational amplifier that must provide sufficient gain and bandwidth while adhering to the goals of compact size and low power consumption. The folded cascade op-amp structure shown in Fig. 6 was chosen to meet these requirements while provided a flexible input common mode range to support different sensors. This single stage amplifier does not require a Miller compensation capacitor, thus maintaining compact size. The circuit is designed to operate in the subthreshold region with a total current consumption of 1 A from a 3 V supply. This compact low-power op-amp is able to achieve a DC gain of 76 dB and a unity gain bandwidth of 800 kHz for a nominal 1 pF load, which is adequate for this application where the maximum clock rate is 100 kHz. The load capacitor value is set to 1 pF, which is large enough to suppress charge injected from the transistor switches connected to it but small enough that a 100 nA peak current can not saturate the integrator at maximum clock rate (100 kHz). B. Comparator To minimize the area impact of the two comparators in Fig. 4, the circuit shown in Fig. 7(a) was designed, combining the two comparator functions into one dual-level amplifier-based comparator. The two output stages utilize the same tail current and share a common input transistor to minimize hardware resources. The DC simulation in Fig. 7(b) shows the non-overlapping comparator output logic as a function of the sweeping
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Fig. 8. Schematic of a 1-bit bidirectional counter/shifter cell with bit inversion control for down counting.
Fig. 7. (a) Schematic of the dual-level comparator amplifier, and (b) DC sweep simulation result.
input voltage. Because the comparator operates at low speeds (maximum clock of 100 kHz), it was also designed to work in the subthreshold region to minimize power consumption. Dynamic comparators [28], [29] are also a good option for this application because they do not have static current consumption. However, they will require more hardware for switches and/or capacitors and thus were not chosen for this compact design.
imize hardware demands, an new algorithm-based counter was developed for the asynchronous bidirectional counter/shifter in the lock-in IDC. This circuit utilizes hardware that performs only single-direction counting along with an algorithm designed to control the up/down count direction. To describe the operation of the new algorithm-based bidirectional counter, consider an example of a 4-bit counter that must count down (minus 1) times. This can be expressed as (13) is the initial value of the counter. Equation (12) where can be rewritten as (14) Using 2’s complement representation, a negative sign operation can be performed by bitwise inversion and adding 1, such as
C. Bidirectional Counter/Shifter The final building block of the lock-in IDC is the bidirectional counter that tabulates and stores digitized results. This block must additionally permit the serial transfer of its stored results in order to accommodate implementation within a large array of IDC readout cells, as discussed in Section II. To realize these functions under the constraints of compact size and low power consumption, a counter/shifter structure [30], [31] was chosen. Because the maximum update clock rate is 100 kHz, an asynchronous counter was selected to save area and avoid unnecessary dynamic power consumption. A compact single-direction counter/shifter has been demonstrated [4] that achieves hardware efficiency by sharing hardware between the counter and shifter. However, IDC operation requires a dynamically configurable bidirectional counter, and adapting the structure in [4] would require significantly more complex control logic, especially for the number of bits needed by the IDC circuit. To min-
(15) Thus, using 2’s complements, (13) becomes
(16) where steps with show substitution with 2’s complement notation. Notice that the final result of (16) shows that counting down by can be achieved by two inversions and counting up by . A unit cell of the asynchronous bidirectional counter/shifter developed for the lock-in IDC is shown in Fig. 8, where all nMOS transistors are set to minimum size, 1.5 m/0.6 m. Based on the compact counter/shifter in [4], this new circuit
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Fig. 9. Waveform of the control signals for the bidirectional counter/shifter.
Fig. 10. Block diagram of a 20-bit up/down counter using the bidirectional counter/shifter cell.
TABLE I PERFORMANCE SUMMARY OF THE LOCK-IN IDC CIRCUIT
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Fig. 11. Die photo of a 1.5 mm 1.5 mm prototype chip containing two lock-in IDC blocks and some test circuits.
also realizes the inversions necessary to implement the downcounting algorithm described by the 4-bit example in (15). In shifting mode, cnt_en is low and the non-overlapping shift_ph1 and shift_ph2 signals toggle to shift data through the cell. In up or down counting mode, both shift-ph1 and shift_ph2 are held low. nMOS transistors M1 and M2 realize the bit inversion necessary for down counting mode, where non-overlapping square pulses on inv_ph1 and inv_ph2 forced the latches and to invert their states. The pulse of inv_ph1 comes first to invert latch
, then the pulse of inv_ph2 lets latch invert. A timing diagram for the control signals of the bidirectional counter/shifter is shown in Fig. 9, which illustrates an up count, a down count, and a shift operation, in sequence. As described by (15), a down counting operation requires a bit inversion both before and after the counting step, as shown in the middle of Fig. 9. The complete 1-bit cell for the bidirectional counter/shifter requires only 22 transistors, fewer than a 28-transistor DFF from a typical standard cell library [32]. Furthermore, most of the transistors in Fig. 9 are NMOS, which helps to reduce the circuit size in an n-well CMOS process. This very compact 1-bit cell was used to construct a 20-bit bidirectional counters/shifters as shown in Fig. 11. Two of these 20-bit blocks are employed in the lock-in IDC (Fig. 4). The size of the counter is set to 20-bit so that the counter will not overflow at the low end of the target stimulus frequency. V. EXPERIMENTAL RESULTS The lock-in IDC circuit was implemented in a foundry 0.5 m CMOS process with a 3 V supply. As shown in Fig. 11,
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Fig. 12. Normalized IDC output values versus input signal initial phase () for 1 kHz 30 nA sinusoid current. This plot demonstrates the proper response of the IDC to variable input signal phase.
a full IDC cell occupies only 100 m 600 m. Therefore, in a 3 mm 3 mm silicon chip, this circuit could be instantiated more than 100 times, which is suitable for most existing and anticipated impedance sensor array platforms. In its operational mode, the IDC circuit consumes only 2 A, thus permitting very low power consumption even in high density arrays. These results are summarized in Table I along with other lock-in IDC performance characteristics described below. The IDC was designed for low frequency impedance measurements and has been tested over a 1 mHz to 10 kHz range; the design could readily be adapted to higher frequency applications by extending the op-amp’s bandwidth and increasing the updating clock rate. The IDC analyzes a sensor’s response current and extracts the real and imaginary portions of its admittance, which are related at certain frequency by (1) to signal phase and amplitude. To characterize the response of the IDC to input phase and amplitude variations, separate measurements were performed where one parameter was swept while the other was held constant. The phase response and the amplitude response of the IDC are described below. As described by (1) and (2), for a current input with a constant and frequency , the relationship between the amplitude and the real (a) or imaginary (b) response relative phase shift components should be a sinusoid waveform. To characterize this relationship, sinusoid current signals with constant amplitude and variable initial phase (relative to the square wave reference) were fed into the lock-in IDC. The IDC’s outputs, normalized to the peak value, were recorded as a function of the initial phase of the input signals. With the lock-in IDC configured to measure the imaginary component, the results for a 1 kHz sinusoid input current with a 30 nA amplitude are plotted in Fig. 12. The theoretically predicted curve from (2) is also plotted in Fig. 13. The measured results were observed to fit the theoretical curve very well, with an RMS error of only 0.027, demonstrating the IDC accurately extracts the imaginary portion of the response current. Inherently, in terms of the circuit operation, the operation to generate the real component is the same as that of the imaginary component. The only difference is that the square wave reference is phase shifted by 90 degrees between real and imaginary component extractions. Therefore, the results for the real component generate a curve that is shifted by 90 degrees from
Fig. 13. Lock-in IDC amplitude transfer performance with respect to the maximum output: (a) DNL; (b) INL. 1024 data points were taken from 0–100 nA amplitude. These results demonstrate the proper response of the IDC to variable input signal amplitude.
the Fig. 12 plot. No obvious dependency between the RMS error and the reference frequency was observed. To demonstrate the IDC’s response to variable input amplitude, notice that (1) and (2) show a linear relationship should exist between the input amplitude and the real or imaginary component output, given the input has constant frequency and phase. Thus, the linearity and accuracy of the lock-in IDC’s amplitude conversion can be quantified by the integral nonlinearity (INL) and differential nonlinearity (DNL) parameters commonly analyzed for high performance analog-to-digital converters. A 10 Hz sinusoid signal with zero phase delay was injected into the IDC, and the amplitude of the sinusoid current input was swept from 100 nA to 0 nA in 1024 steps. With a 100 kHz updating clock, there are 10,000 clock cycles for the measurement. With the lock-in IDC set to extract the real component, the measured INL and DNL are plotted in Fig. 13. These results demonstrate a 50 dB dynamic range (8-bit) for the 100 nA input range. Although several factors impact the accuracy of the lock-in IDC, our observations suggest that the two major limitations are charge injection of the switches and signal coupling at the input nodes. The lock-in IDC can be configured to accommodate a wide dynamic range of input signal strengths in order to support a
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Fig. 15. Test setup for the biosensor measurements using the prototype lock-in IDC chip.
Fig. 14. Amplitude conversion characteristics for a zero phase sinewave input. The lock-in IDC can be configured to accommodate a wide range of input signal strengths, two of which are shown here.
variety of sensors. The signal range is determined by on chip settings that control the magnitude of the two reference currents and the frequency of the updating clock. To test the achievable dynamic range, an input test current was generated by applying a sinusoidal voltage to a capacitor and sweeping its amplitude. In order to generate appropriate inputs using available off-theshelf capacitors, the sinusoidal voltage was set to 0.1 Hz for the lowest current range. For the largest current range, it was set to 1 Hz. Fig. 14 plots the IDC output codes as a function of the input current amplitude for these two boundary ranges of input signal strength. The results show that currents ranging from below 100 fA to 100 nA can be converted, with a maximum sensitivity (minimum linear response) at 78 fA. VI. BIOSENSOR MEASUREMENTS The IDC circuit was designed to enable the development of a monolithic microsystem that extracts the impedance of an on-chip sensor array. To demonstrate the IDC circuit’s capabilities in such a system, a hybrid impedance sensor platform described by Fig. 15 was implemented for rapid prototyping. A data acquisition card (Agilent E3630A) was connected to a computer and employed to generate the sensor stimulus sinusoid and collect output data from the IDC. Here, we demonstrate the use of the IDC circuit for electrochemical biosensing via ion transport activity of a membrane protein incorporated in an artificial bilayer lipid membrane (BLM) interface. BLM interfaces are useful in functional proteomics research to characterize novel membrane proteins and can be used to develop membrane protein biosensors for many applications including high-throughput drug screening. In our sensor, tethered BLMs (tBLM) embedded with gramicidin ion channel protein are deposited on gold electrodes patterned on a glass chip [33], [34]. Briefly described, a self-assembled monolayer (SAM) of 1,2-dipalmitoyl-sn-glycero-3-phosphothioethanol (DPPTE) tether lipid was formed on a clean gold electrode patterned on the glass chip. The upper leaflet of bilayer membrane was deposited by fusion of liposome vesicles made of
1,2-dioleoyl-sn-glycero-3-phosphocholine (DOPC) mobile lipids. Bilayer lipid membrane acts as an insulating dielectric barrier for ion transport, thereby increasing the impedance of gramicidin the bio-interface. After tBLM formation, 1 ion channel protein was introduced to the electrolyte solution to incorporate gramicidin ion channels in tBLM. Gramicidin selectively transports alkali metal ions through the tBLM and therefore lowers the impedance of the modified tBLM in the presence of alkali metal ions in the electrolyte solution. Impedance measurements were conducted with the IDC chip over the frequency range of 10 mHz to 100 Hz while the biosensor was being formed; first the DPPTE monolayer, then the tBLM, and finally the gramicidin modified tBLM in 100 mM sodium chloride solution, immediately after their formations.Fig. 16 shows the impedance data obtained from the IDC chip for one biosensor element as a function of frequency. The impedance data was fit using ZView software (Scribner Associates, Inc.) to the modified Randle’s equivalent circuit shown in Fig. 17. The equivalent circuit is a combination of resistors and capacitors that can be related to the physical properties of the biosensor interface. The membrane capacitance and resistance were modeled in parallel to represent the properties of the bilayer membrane. For a DPPTE monolayer, and values were measured to be 0.635 F cm the and 20 K cm respectively. For the tBLM, a and of 0.505 F cm and 425 K cm were obtained. The capacitance value for the tBLM is in good agreement with the reported values for high quality BLMs [33]. Fig. 16 also shows that incorporation of gramicidin in the tBLM decreased the membrane resistance from 425 to 59 K cm due to the gramicidin mediated passage of sodium (alkali metal) ions through the tBLM. These measurements demonstrate that the compact IDC circuit can successfully characterize the impedance spectra of sensor materials. The drop in membrane resistance is a direct measure of the ion transport activity of gramicidin channels. The measurements of electrochemical properties of tBLM and ion transport activity of gramicidin are in agreement with those made by commercial instruments [34]. The measurement of ion transport activity of a channel membrane protein on an array using the IDC chip provides an efficient design for high throughput screening platforms. A future generation of the chip containing a large array of IDC cells would be capable of measuring many sensor elements simultaneously, rapidly extracting
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instantiated with each element of a sensor array. The circuit locally extracts and digitizes sensor impedance information using mixed-mode signal processing, eliminating the cost, power, and size of the external hardware typically employed to analyze raw sensor data. The circuit was fabricated in a with standard 0.5 m CMOS process. It consumes only 6 a 3 V supply and occupies only 0.06 mm per cell, permitting over 100 cells within a 3 3 mm chip. Tests show that the impedance-to-digital converter provides over 50 dB of amplitude conversion linearity and exhibits less than 2.7% RMS phase conversion error. It can accommodate sensor current inputs ranging from 78 fA to 100 nA, suitable for a diversity of bio- and nano-materials. The capabilities of the new circuit were verified in a prototype microsystem where it successfully measured the impedance spectrum of a miniaturized membrane protein (gramicidin) biosensor. The current design supports impedance extraction up to 10 kHz, and the architecture is adaptable to higher frequency applications with adjustments to op-amp bandwidth and updating clock frequencies. The lock-in IDC circuit demonstrates that high density impedance sensor arrays can feasibly be implemented on a single chip. ACKNOWLEDGMENT The authors would like to thank Y. Huang for preparing the microelectrodes in the biosensor experiment and D. Rairigh for consulting on design issues. REFERENCES
Fig. 16. Biosensor impedance as a function of frequency measured by the lock-in IDC: (a) impedance amplitude and (b) phase angle. Measurements were performed at three phases of the biosensor self assembly; the DPPTE tethering lipid monolayer (diamonds), tBLM (squares), and tBLM after gramicidin incorporation (rectangles). As expected, the membrane resistance increases after bilayer formation (relative to the DPPTE monolayer) and then decreases after gramicidin incorporation due to the transport of sodium ions across the bilayer membrane.
[1] Y. Huang and A. Mason, “Post CMOS compatible microfabrication of a multi-analyte bioelectrochemcial sensor array microsystem,” in Proc. IEEE Int. Conf. Sensors, Dageu, Korea, 2006, pp. 612–615. [2] A. Hassibi and T. H. Lee, “A programmble 0.18 m CMOS electrochemcial sensor microarray for biomolecuar detection,” IEEE Sensors J., vol. 6, pp. 1380–1388, Dec. 2006. [3] K. S. Yun, H. J. Kim, S. Joo, J. Kwak, and E. Yoon, “Analysis of heavymetal ions using mercury microelectrodes and a solid-state reference electrode on a Si wafer,” Jpn. J. Appl. Phys. Part 1-Reg. Papers, Short Notes and Review Papers, vol. 39, pp. 7159–7163, Dec. 2000. [4] M. Schienle et al., “A fully electronic DNA sensor with 128 positions and in-pixel A/D conversion,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2438–2445, Dec. 2004. [5] B. Eversmann et al., “A 128 128 CMOS biosensor array for extracellular recording of neural activity,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2306–2317, Dec. 2003. [6] X. Zhu and C. H. Ahn, “On-chip electrochemical analysis system using nanoelectrodes and bioelectronic CMOS chip,” IEEE Sensors J., vol. 6, pp. 1280–1287, May 2006. [7] M. Trojanowicz, “Miniaturized biochemical sensing devices based on planar bilayer lipid membranes,” Fresenius’ J. Analyt. Chem., vol. 371, pp. 246–260, Feb. 2001. [8] B. Hassler et al., “Biomimetic interfaces for a multifunctional biosensor array microsystem,” in Proc. IEEE Int. Conf. Sensors, Vienna, Austria, 2004, pp. 991–994. [9] G. Hagen, A. Dubbe, G. Fischerauer, and R. Moos, “Thick-film impedance based hydrocarbon detection based on chromium (III) oxide/zeolite interfaces,” Sens. Actuators B, Chem., vol. 118, pp. 73–77, Oct. 2006. [10] K. Ogura, T. Tonosaki, and H. Shiigi, “AC impedance spectroscopy of humidity sensor using poly (o-phenylenediamine)/poly (vinyl alcohol) composite film,” J. Electrochem. Soc., vol. 148, pp. H21–H27, Mar. 2001. [11] J. S. Daniels and N. Pourmand, “Label-free impedance biosensors: Opportunities and challenges,” Electroanalysis, vol. 19, pp. 1239–1257, May 2007. [12] G. S. Popkirov and R. N. Schindler, “A new impedance spectrometer for the investigation of electrochemical systems,” Rev. Sci. Instrum., vol. 61, pp. 5366–5372, Nov. 1992.
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Fig. 17. Modified Randle’s equivalent circuit for a tBLM electrochemical biosensor: C represents the capacitance of membrane, R represents the resistance of membrane, and C represents the capacitance of double layer that includes the Hemholtz capacitance.
their characteristic impedance and generating a digital result at each desired frequency. VII. CONCLUSION A very compact, low power, impedance-to-digital converter circuit has been introduced. Tailored for on-chip sensor array microsystems, the impedance spectroscopy circuit can be
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Chao Yang received the B.S. and M.S. degrees in electrical engineering from Tsinghua University, Beijing, China, in 1999 and 2002, and the Ph.D. degree in electrical engineering from Michigan State University, East Lansing, MI, in 2008. Currently, he is with Marvell Semiconductor, Inc., Austin, TX. His research focus is the RF/analog/mixed-signal IC design, the biomedical and biochemical instrumentation microsystem. Dr. Yang was the recipient of the Excellence Scholarships from Tsinghua University from 1996 to 1998 and that of the VLSI/SOC Fellowship from Michigan State University in 2007. He won the third (out of 40) Place Awards in both phase-1 and phase-2 SRC (Semiconductor Research Corporation)/SIA (Semiconductor Industry Association) SoC Design Challenge.
Sachin R. Jadhav received the B.S. degree in pharmaceutical sciences from Amravati University, Amravati, India, in 2002, and the M.S. degree in bioprocess technology from the University of Mumbai, Mumbai, India, in 2004. He is currently pursuing the Ph.D. degree in chemical engineering at Michigan State University, East Lansing, MI. His research interests include protein purification, proteins’ functional characterization, and high-throughput biosensing.
R. Mark Worden received the B.A. degree with a double major in chemistry and cell biology in 1979, the M.S. degree in chemical engineering in 1982, and the Ph.D. degree in chemical engineering in 1986, all from the University of Tennessee in Knoxville. The research for his M.S. and Ph.D. degrees was conducted in the Bioprocess Engineering group at Oak Ridge National Laboratory in Oak Ridge, TN. He became an Assistant Professor in the Department of Chemical Engineering and Materials Science at Michigan State University in East Lansing, MI, in 1986, and was promoted to Associate Professor in 1991, and then Professor in 1998. His research program integrates recombinant-protein production, biocatalysis, and nanotechnology to develop new systems for bioproduction, biosensing, and bioremediation. His current projects include use of electrochemical sensor arrays for high-throughput biosensor systems and functional proteomics.
Andrew J. Mason (S’90–M’99–SM’06) received the B.S. degree in physics with highest distinction from Western Kentucky University, Bowling Green, in 1991, the B.S.E.E. degree with honors from the Georgia Institute of Technology, Atlanta, in 1992, and the M.S. and Ph.D. degrees in electrical engineering from the University of Michigan, Ann Arbor, in 1994 and 2000, respectively. From 1999 to 2001, he was an Assistant Professor at the University of Kentucky. In 2001, he joined the Department of Electrical and Computer Engineering at Michigan State University in East Lansing, Michigan, where he is currently an Associate Professor. His research addresses many areas of mixed-signal circuit design and the fabrication of integrated microsystems. His current projects include compact low-power bioelectrochemical interrogation circuits, adaptive chemical sensor interface circuits, post-CMOS fabrication of electrochemical sensor arrays, and mixed-signal integrated circuits for signal processing in neural implants. Dr. Mason serves on the Sensory Systems and Biomedical Circuits and Systems Technical Committees of the IEEE Circuits and Systems Society and on the technical program committee for several IEEE conferences and workshops. During 2008–2009, he was a guest Associate Editor of the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS. He is a recipient of the 2006 Michigan State University Teacher-Scholar Award.
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