COPING WITH INTERCONNECT
COPING WITH INTERCONNECT
Interconnect
Impact of Interconnect Parasitics • Reduce Reliability • Affect Performance
Classes of Parasitics • Capacitive • Resistive • Inductive Interconnect
Nature of Interconnect Local Interconnect
Global Interconnect
SLocal = S Technology SGlobal = S Die Interconnect
INTERCONNECT
Dealing with Capacitance
Interconnect
Capacitance: The Parallel Plate Model
L W
H tox
SiO2 Substrate
Interconnect
Typical Wiring Capacitance Values
Interconnect
Fringing Capacitance
(a) H
W - H/2
+
(b) Interconnect
Fringing Capacitance: Values
Interconnect
How to counter Clock Skew?
(from [Bakoglu89]) Interconnect
Interwire Capacitance Level2 Insulator
Level1 SiO2 Substrate
Creates Cross-talk Interconnect
Interwire Capacitance
Interconnect
Impact of Interwire Capacitance
(from [Bakoglu89])
Interconnect
Capacitance Crosstalk VDD
φ
CXY X CX
In1
Y
PDN
In2
5V
In3
OV
φ
5x5 µm Overlap: 0.35 V Interference Interconnect
How to Battle Capacitive Crosstalk • Avoid parallel wires • Shielding Shielding wire GND
VDD GND
Substrate (GND) Interconnect
Shielding layer
Driving Large Capacitances tpHL = CL Vswing/2 Iav
VDD
Vin
Vout CL
Interconnect
Transistor Sizing
Using Cascaded Buffers
In
Out
Ci
u2
u
1 C1
u N-1
C2 CL
uopt = e Interconnect
tp in function of u and x
u/ln(u)
60.0
40.0
x=10,000 x=1000
20.0
x=100 x=10
0.0 1.0
3.0
Interconnect
u
5.0
7.0
Impact of Cascading Buffers
Interconnect
Output Driver Design
Interconnect
How to Design Large Transistors D(rain) S
Multiple Contacts
D G
S(ource) S G(ate) (a) small transistors in parallel Interconnect
(b) circular transistors
Bonding Pad Design Bonding Pad
GND
100 µm
Out
VDD
In
GND Interconnect
Out
Reducing the swing tpHL = CL Vs wing /2 Iav • Reducing
the swing potentially yields linear reduction in delay • Also results in reduction in power dissipation • Requires use of “sense amplifier” to restore signal level
Interconnect
INTERCONNECT
Dealing with Resistance
Interconnect
Wire Resistance R=ρ L HW Sheet Resistance Ro
L H
W
R1
Interconnect
R2
Interconnect Resistance
Interconnect
Dealing with Resistance • Selective Technology Scaling
• Use Better Interconnect Materials e.g. silicides, bypasses • More Interconnect Layers reduce average wire-length
Interconnect
Polycide Gate Mosfet Silicide PolySilicon SiO 2
n+
n+ p
Silicides: WSi2, TiSi 2, PtSi2 and TaSi Conductivity: 8-10 times better than Poly Interconnect
Modern Interconnect
Interconnect
RI Introduced Noise I
VDD
R’
φpr e
VDD - ∆V’
X I ∆V R
Interconnect
∆V
Power and Ground Distribution GND
VDD
Logic
Logic VDD
VDD
GND
GND
(a) Finger-shaped network
(b) Network with multiple supply pins Interconnect
Electromigration (1)
Limits dc-current to 1 mA/µm Interconnect
Electromigration (2)
Interconnect
RC-Delay
Interconnect
RC-Models
Interconnect
Reducing RC-delay
Repeater
Interconnect
The Ellmore Delay
Interconnect
Penfield-Rubinstein-Horowitz
Interconnect
Interconnect
Impact of Interconnect Parasitics • Reduce Reliability • Affect Performance
Classes of Parasitics • Capacitive • Resistive • Inductive Interconnect
Nature of Interconnect Local Interconnect
Global Interconnect
SLocal = S Technology SGlobal = S Die Interconnect
INTERCONNECT
Dealing with Capacitance
Interconnect
Capacitance: The Parallel Plate Model
L W
H tox
SiO2 Substrate
Interconnect
Typical Wiring Capacitance Values
Interconnect
Fringing Capacitance
(a) H
W - H/2
+
(b) Interconnect
Fringing Capacitance: Values
Interconnect
How to counter Clock Skew?
(from [Bakoglu89]) Interconnect
Interwire Capacitance Level2 Insulator
Level1 SiO2 Substrate
Creates Cross-talk Interconnect
Interwire Capacitance
Interconnect
Impact of Interwire Capacitance
(from [Bakoglu89])
Interconnect
Capacitance Crosstalk VDD
φ
CXY X CX
In1
Y
PDN
In2
5V
In3
OV
φ
5x5 µm Overlap: 0.35 V Interference Interconnect
How to Battle Capacitive Crosstalk • Avoid parallel wires • Shielding Shielding wire GND
VDD GND
Substrate (GND) Interconnect
Shielding layer
Driving Large Capacitances tpHL = CL Vswing/2 Iav
VDD
Vin
Vout CL
Interconnect
Transistor Sizing
Using Cascaded Buffers
In
Out
Ci
u2
u
1 C1
u N-1
C2 CL
uopt = e Interconnect
tp in function of u and x
u/ln(u)
60.0
40.0
x=10,000 x=1000
20.0
x=100 x=10
0.0 1.0
3.0
Interconnect
u
5.0
7.0
Impact of Cascading Buffers
Interconnect
Output Driver Design
Interconnect
How to Design Large Transistors D(rain) S
Multiple Contacts
D G
S(ource) S G(ate) (a) small transistors in parallel Interconnect
(b) circular transistors
Bonding Pad Design Bonding Pad
GND
100 µm
Out
VDD
In
GND Interconnect
Out
Reducing the swing tpHL = CL Vs wing /2 Iav • Reducing
the swing potentially yields linear reduction in delay • Also results in reduction in power dissipation • Requires use of “sense amplifier” to restore signal level
Interconnect
INTERCONNECT
Dealing with Resistance
Interconnect
Wire Resistance R=ρ L HW Sheet Resistance Ro
L H
W
R1
Interconnect
R2
Interconnect Resistance
Interconnect
Dealing with Resistance • Selective Technology Scaling
• Use Better Interconnect Materials e.g. silicides, bypasses • More Interconnect Layers reduce average wire-length
Interconnect
Polycide Gate Mosfet Silicide PolySilicon SiO 2
n+
n+ p
Silicides: WSi2, TiSi 2, PtSi2 and TaSi Conductivity: 8-10 times better than Poly Interconnect
Modern Interconnect
Interconnect
RI Introduced Noise I
VDD
R’
φpr e
VDD - ∆V’
X I ∆V R
Interconnect
∆V
Power and Ground Distribution GND
VDD
Logic
Logic VDD
VDD
GND
GND
(a) Finger-shaped network
(b) Network with multiple supply pins Interconnect
Electromigration (1)
Limits dc-current to 1 mA/µm Interconnect
Electromigration (2)
Interconnect
RC-Delay
Interconnect
RC-Models
Interconnect
Reducing RC-delay
Repeater
Interconnect
The Ellmore Delay
Interconnect
Penfield-Rubinstein-Horowitz
Interconnect
