CSCI 220: Computer Architecture-I Instructor: Pranava K ...
CSCI 220: Computer Architecture-I Instructor: Pranava K. Jha Adder-like Circuits Q. A four-bit incrementer circuit takes a four-bit number as the input, and adds 1 to it. The output is a five-bit number. Show how to implement this circuit using four half adders. Let a3a2a1a0 be a four-bit number, and let b4b3b2b1b0 be the five-bit number that is equal to (a3a2a1a0) + 1. The truth table follows. Input a3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
a2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
a1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Output a0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
b4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
b3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
b2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
b1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
b0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Here are simplified expressions for b0, b1, b2, b3 and b4 – obtainable by means of Karnaugh maps and algebraic manipulations: • • • • •
b0 = a0’ = a0 ⊕ 1. b1 = a1a0’ + a1’a0 = a1⊕ a0. b2 = a2a1’ + a2a0’ + a2’ a1a0 = a2 (a1 a0)’ + a2’ (a1a0) = a2 ⊕ (a1 a0). b3 = a3a2’ + a3a1’ + a3a0’ + a3’a2a1a0 = a3(a2a1a0)’ + a3’(a2a1a0) = a3 ⊕ (a2a1a0). b4 = a3a2a1a0.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Objective is to implement the incrementer circuit using half adders. To that end, here is the block diagram of a half adder (HA) where sum s = x ⊕ y and carry c = xy. x
y
1 4 c
2 HA
3 s
A realization of the required four-bit incrementer circuit follows. Correctness of the scheme follows from the earlier expressions for b0, b1, b2, b3 and b4, and working of the half adder.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Q. Using a 4-bit binary adder, design a simple network to convert the 8421 code into the corresponding excess-three code. Following is the block diagram of a four-bit binary adder, where 〈A3, A2, A1, A0〉 is the augend, 〈B3, B2, B1, B0〉 is the addend, Cin is the carry-in, 〈Σ3, Σ2, Σ1, Σ0〉 is the sum and Cout is the carry-out.
Here is the 8421 code and the corresponding excess-three code for each decimal digit.
A 0 0 0 0 0 0 0 0 1 1
8421 code B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0
D 0 1 0 1 0 1 0 1 0 1
Decimal digit 0 1 2 3 4 5 6 7 8 9
E 0 0 0 0 0 1 1 1 1 1
Excess-three code F G H 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
It is clear that 〈E, F, G, H〉 = 〈A, B, C, D〉 + 〈0, 0, 1, 1〉. The design follows.
Note: Cout bit (from pin 14) is not relevant. For valid inputs, it will be 0.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
4-bit adders are available as ICs. The most common is IC-74283. Q. Using a 4-bit binary adder, design a simple network to convert the excess-three code of into the corresponding 8421 code. Here is the excess-three code and the corresponding 8421 code for each decimal digit. Excess-three code A B C D 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0
Decimal digit 0 1 2 3 4 5 6 7 8 9
E 0 0 0 0 0 0 0 0 1 1
8421 code F G 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0
H 0 1 0 1 0 1 0 1 0 1
It is clear that 〈E, F, G, H〉 = 〈A, B, C, D〉 – 〈0, 0, 1, 1〉. However, since the objective is to use a 4-bit adder (instead of a subtractor), the following scheme is relevant: Add 〈1, 1, 0, 1〉 to 〈A, B, C, D〉, and discard the Cout bit. (This is equivalent to adding decimal 13 to a number between 3 and 12, and discarding the carry.) The four-bit string representing the sum is the desired 8421 code. The block diagram follows.
Note: Cout bit (from pin 14) is discarded.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Q. Recall that a half adder has two inputs, say X and Y, and two outputs, say S and C, where S = X ⊕ Y and C = X·Y. A block diagram appears below.
1 2
X Y
4 3
HA
S C
Show how to implement the following schematic by means of three half adders. (Use block diagrams, and include pin numbers.) E = A’B’D + A’BD’ + AB’D’ + ABD
A
F = A’BD + AB’D
B
G = ABD’ + A’D + B’D
D
H = ABD
Claim 1: E = A ⊕ B ⊕ D. Claim 2: F = (A ⊕ B)D. Claim 3: G = (AB) ⊕ D. Claim 4: H = (AB)D. Proofs of the claims are left to the readers. Implementation follows.
A
• B
1 2
HA
4 3
A⊕B
•
AB
HA
4 3
HA
4 3
A⊕B ⊕D (A ⊕ B)D
E F
• •
D
D
1 2
AB
• D
1 2
(AB) ⊕ D (AB)D
G H
Note: Properly showing the pin numbers within each half subtractor is important. In particular, it minimizes the possibility of a mix-up in an actual implementation.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Q. Recall that a half subtractor has two inputs, say x and y, and two outputs, say d and b, where d = x ⊕ y and b = x’⋅ y. A block diagram appears below. x y
1 2
4 3
HS
d b
Present an implementation of the following schematic by means of three half subtractors. Use block diagrams, and show the pin numbers of each unit. D=A⊕B⊕C
A
E = ABC + A’B’C
B
F = A’BC’ + AC + B’C
C
G = AC + B’C Note that • • • •
D = (A ⊕ B) ⊕ C E = (AB + A’B’)C = (A’B + AB’)’ C = (A ⊕ B)’ C F = A’BC’ + (A+B’)C = (A’B)C’ + (A’B)’ C = (A’B) ⊕ C, and G = (A + B’)C = (A’B)’ C.
Implementation of the given circuit is now immediate.
A
1 2
HS
4 3
A⊕B C
A’B
1 2
HS
4
3
A⊕B⊕C (A ⊕ B)’ C
D E
B A’B C
•
C
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1 2
HS
4 3
(A’B) ⊕ C (A’B)’ C
F G
CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Design of an 8421 BCD Adder Objective is to add two decimal digits, each expressed in 8421 BCD code. Inputs:
(i) Two four-bit numbers 〈A3, A2, A1, A0〉 and 〈B3, B2, B1, B0〉, each denoting a decimal digit in 8421 code, and (ii) a carry-in bit Cin, where 〈A3, A2, A1, A0〉 is the augend and 〈B3, B2, B1, B0〉 is the addend.
Outputs:
(i)A four-bit number 〈S3, S2, S1, S0〉 that is the sum, and (ii) a carry-out bit C.
Components available: 4-bit binary adders and simple logic gates. Here is the block diagram of the 8421 BCD adder at the highest level of abstraction. A3 A2 A1 A0 B3 B2 B1 B0 8421 BCD Adder
C
Cin
S3 S2 S1 S0 The outputs corresponding to the decimal sum (0 – 19) appear in the following table.
Decimal sum
C
S3
S2
S1
S0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
First employ a 4-bit binary adder to add 〈A3, A2, A1, A0〉, 〈B3, B2, B1, B0〉 and Cin as if they were usual binary numbers. Let outputs from the adder be K and 〈Z3, Z2, Z1, Z0〉. The block diagram at this level of abstraction appears below.
K
A3 A2 A1 A0
B3 B2 B1 B0
1
5
2
3
4
6
7
8
4-bit Binary Adder
14 13
C
12
Z3
S3
11
Z2
S2
10
Z1
S1
Cin
9
Z0
S0
The design is obviously incomplete at this point. The following table relates the intermediate outputs K and 〈Z3, Z2, Z1, Z0〉 with the desired outputs C and 〈S3, S2, S1, S0〉. Decimal sum
K
Z3
Z2
Z1
Z0
C
S3
S2
S1
S0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Remark: The intermediate outputs K and 〈Z3, Z2, Z1, Z0〉 correspond to usual binary representation of the decimal sum. It is not difficult to see from the preceding table that C = 1 if and only if the following holds: i. ii. iii.
K = 1, or Z3 = Z2 = 1, or Z3 = Z1 = 1.
Accordingly, C = K + Z3Z2 + Z3Z1. Finally, 〈S3, S2, S1, S0〉 is obtainable from C and 〈Z3, Z2, Z1, Z0〉 as follows: • •
If C = 0, then add 〈0, 0, 0, 0〉 to 〈Z3, Z2, Z1, Z0〉, and If C = 1, then add 〈0, 1, 1, 0〉 to 〈Z3, Z2, Z1, Z0〉.
In each case, discard the carry, if any. (In fact, carry will be generated in the second case only.) Here is the final implementation of the circuit. A3 A 2 A1 A0
K
1 14
2 3
B3 B2 B 1 B 0
4
5
6 7
4-bit Binary Adder 13
12
Z3
Z2
11
Z1
8 9
Cin
10
Z0
C
0 1 14
0 2 3
4
5
6 7
4-bit Binary Adder 13
12
11
10
S3
S2
S1
S0
8 9
0
Note: Input carry to the second binary adder is fixed at 0, while output carry is discarded.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Design of an Excess-three Adder Objective is to add two decimal digits, each expressed in excess-three code. Inputs:
(i) Two four-bit numbers 〈A3, A2, A1, A0〉 and 〈B3, B2, B1, B0〉, each denoting a decimal digit in excess-three code, and (ii) a carry-in bit Cin, where 〈A3, A2, A1, A0〉 is the augend and 〈B3, B2, B1, B0〉 is the addend.
Outputs: (i)A four-bit number 〈S3, S2, S1, S0〉 that is the sum, and (ii) a carry-out bit C. Components available: 4-bit binary adders and simple logic gates. Here is the block diagram of the excess-three adder at the highest level of abstraction.
The outputs corresponding to the decimal sum (0 – 19) appear in the following table. Decimal sum
C
S3
S2
S1
S0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1
0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1
1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
First employ a 4-bit binary adder to add 〈A3, A2, A1, A0〉, 〈B3, B2, B1, B0〉 and Cin as if they were usual binary numbers. Let outputs from the adder be K and 〈Z3, Z2, Z1, Z0〉. The block diagram at this level of abstraction appears below.
K
A3 A2 A1 A0
B3 B2 B1 B0
1
5
2
3
4
6
7
8
4-bit Binary Adder
14 13
C
12
Z3
S3
11
Z2
S2
10
Z1
S1
Cin
9
Z0
S0
The design is obviously incomplete at this point. The following table relates the intermediate outputs K and 〈Z3, Z2, Z1, Z0〉 with the desired outputs C and 〈S3, S2, S1, S0〉. Decimal sum
K
Z3
Z2
Z1
Z0
C
S3
S2
S1
S0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1
1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1
0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1
1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Remark: Since augend and addend to the binary adder are both in excess-three, the intermediate outputs K and 〈Z3, Z2, Z1, Z0〉 correspond to excess-six representation of the decimal sum. It is clear from the preceding table that C = K. Further, 〈S3, S2, S1, S0〉 is obtainable from K and 〈Z3, Z2, Z1, Z0〉 as follows: • •
If K = 0, then add 〈1, 1, 0, 1〉 to 〈Z3, Z2, Z1, Z0〉, and If K = 1, then add 〈0, 0, 1, 1〉 to 〈Z3, Z2, Z1, Z0〉.
In each case, discard the carry, if any. (In fact, carry will be generated in the first case only.) Remark: The following is equally correct: • •
If K = 0, then subtract 〈0, 0, 1, 1〉 from 〈Z3, Z2, Z1, Z0〉, and If K = 1, then add 〈0, 0, 1, 1〉 to 〈Z3, Z2, Z1, Z0〉.
However, from implementation point of view, the former solution is better: Uniformly employ two 4-bit binary adders, and discard the carry (if any) from the second adder. Here is the final implementation of the circuit.
Note: Input carry to the second binary adder is fixed at 0, while output carry is discarded.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Design of an 8421 BCD Subtractor Objective is to subtract a decimal digit from another, where each digit is expressed in 8421 BCD code. Inputs:
(i) Two four-bit numbers 〈X3, X2, X1, X0〉 and 〈Y3, Y2, Y1, Y0〉, each denoting a decimal digit in 8421 BCD code, and (ii) a borrow-in bit Bin, where 〈X3, X2, X1, X0〉 is the minuend and 〈Y3, Y2, Y1, Y0〉 is the subtrahend.
Outputs: (i)A four-bit number 〈D3, D2, D1, D0〉 that is the difference in 8421 code, and (ii) a borrow-out bit B. Components available: 4-bit binary subtractors and simple logic gates. Here is the block diagram of a 4-bit binary subtractor that is the most important component in the present design.
Following is the block diagram of the desired 8421 BCD subtractor at the highest level of abstraction.
Note that when a decimal digit is subtracted from another (taking into account the borrow-in), the result is a number between –10 and +9. The desired outputs corresponding to the decimal difference appear in the following table.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Decimal difference
B
D3
D2
D1
D0
9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
First employ a 4-bit binary subtractor where 〈X3, X2, X1, X0〉, 〈Y3, Y2, Y1, Y0〉, and Bin are input as if they were usual binary numbers. Let outputs from this subtractor be b and 〈P3, P2, P1, P0〉. The block diagram at this level of abstraction appears below.
b
X3
X2 X1 X0
Y3
Y2 Y1 Y0
1
2
5
6
14
3
4
4-bit Binary Subtractor 13
B
12
P3
D3
7
11
P2
D2
D1
8 9
10
P1
P0
D0
The design is obviously incomplete at this point. The following table relates the intermediate outputs b and 〈P3, P2, P1, P0〉 with the desired outputs B and 〈D3, D2, D1, D0〉.
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Bin
CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Decimal difference 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10
b 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
P3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
P2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
P1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
P0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
B 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
D3 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
D2 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0
D1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0
D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Observe that B = b. Further, if b = 0, then 〈D3, D2, D1, D0〉 = 〈P3, P2, P1, P0〉 – 〈0, 0, 0, 0〉, and if b = 1, then 〈D3, D2, D1, D0〉 = 〈P3, P2, P1, P0〉 – 〈0, 1, 1, 0〉. Here is the final implementation of the circuit.
Note: Borrow-in to the second subtractor is fixed at 0, while borrow-out is discarded.
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a2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
a1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Output a0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
b4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
b3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
b2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
b1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
b0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Here are simplified expressions for b0, b1, b2, b3 and b4 – obtainable by means of Karnaugh maps and algebraic manipulations: • • • • •
b0 = a0’ = a0 ⊕ 1. b1 = a1a0’ + a1’a0 = a1⊕ a0. b2 = a2a1’ + a2a0’ + a2’ a1a0 = a2 (a1 a0)’ + a2’ (a1a0) = a2 ⊕ (a1 a0). b3 = a3a2’ + a3a1’ + a3a0’ + a3’a2a1a0 = a3(a2a1a0)’ + a3’(a2a1a0) = a3 ⊕ (a2a1a0). b4 = a3a2a1a0.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Objective is to implement the incrementer circuit using half adders. To that end, here is the block diagram of a half adder (HA) where sum s = x ⊕ y and carry c = xy. x
y
1 4 c
2 HA
3 s
A realization of the required four-bit incrementer circuit follows. Correctness of the scheme follows from the earlier expressions for b0, b1, b2, b3 and b4, and working of the half adder.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Q. Using a 4-bit binary adder, design a simple network to convert the 8421 code into the corresponding excess-three code. Following is the block diagram of a four-bit binary adder, where 〈A3, A2, A1, A0〉 is the augend, 〈B3, B2, B1, B0〉 is the addend, Cin is the carry-in, 〈Σ3, Σ2, Σ1, Σ0〉 is the sum and Cout is the carry-out.
Here is the 8421 code and the corresponding excess-three code for each decimal digit.
A 0 0 0 0 0 0 0 0 1 1
8421 code B C 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0
D 0 1 0 1 0 1 0 1 0 1
Decimal digit 0 1 2 3 4 5 6 7 8 9
E 0 0 0 0 0 1 1 1 1 1
Excess-three code F G H 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
It is clear that 〈E, F, G, H〉 = 〈A, B, C, D〉 + 〈0, 0, 1, 1〉. The design follows.
Note: Cout bit (from pin 14) is not relevant. For valid inputs, it will be 0.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
4-bit adders are available as ICs. The most common is IC-74283. Q. Using a 4-bit binary adder, design a simple network to convert the excess-three code of into the corresponding 8421 code. Here is the excess-three code and the corresponding 8421 code for each decimal digit. Excess-three code A B C D 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0
Decimal digit 0 1 2 3 4 5 6 7 8 9
E 0 0 0 0 0 0 0 0 1 1
8421 code F G 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0
H 0 1 0 1 0 1 0 1 0 1
It is clear that 〈E, F, G, H〉 = 〈A, B, C, D〉 – 〈0, 0, 1, 1〉. However, since the objective is to use a 4-bit adder (instead of a subtractor), the following scheme is relevant: Add 〈1, 1, 0, 1〉 to 〈A, B, C, D〉, and discard the Cout bit. (This is equivalent to adding decimal 13 to a number between 3 and 12, and discarding the carry.) The four-bit string representing the sum is the desired 8421 code. The block diagram follows.
Note: Cout bit (from pin 14) is discarded.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Q. Recall that a half adder has two inputs, say X and Y, and two outputs, say S and C, where S = X ⊕ Y and C = X·Y. A block diagram appears below.
1 2
X Y
4 3
HA
S C
Show how to implement the following schematic by means of three half adders. (Use block diagrams, and include pin numbers.) E = A’B’D + A’BD’ + AB’D’ + ABD
A
F = A’BD + AB’D
B
G = ABD’ + A’D + B’D
D
H = ABD
Claim 1: E = A ⊕ B ⊕ D. Claim 2: F = (A ⊕ B)D. Claim 3: G = (AB) ⊕ D. Claim 4: H = (AB)D. Proofs of the claims are left to the readers. Implementation follows.
A
• B
1 2
HA
4 3
A⊕B
•
AB
HA
4 3
HA
4 3
A⊕B ⊕D (A ⊕ B)D
E F
• •
D
D
1 2
AB
• D
1 2
(AB) ⊕ D (AB)D
G H
Note: Properly showing the pin numbers within each half subtractor is important. In particular, it minimizes the possibility of a mix-up in an actual implementation.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Q. Recall that a half subtractor has two inputs, say x and y, and two outputs, say d and b, where d = x ⊕ y and b = x’⋅ y. A block diagram appears below. x y
1 2
4 3
HS
d b
Present an implementation of the following schematic by means of three half subtractors. Use block diagrams, and show the pin numbers of each unit. D=A⊕B⊕C
A
E = ABC + A’B’C
B
F = A’BC’ + AC + B’C
C
G = AC + B’C Note that • • • •
D = (A ⊕ B) ⊕ C E = (AB + A’B’)C = (A’B + AB’)’ C = (A ⊕ B)’ C F = A’BC’ + (A+B’)C = (A’B)C’ + (A’B)’ C = (A’B) ⊕ C, and G = (A + B’)C = (A’B)’ C.
Implementation of the given circuit is now immediate.
A
1 2
HS
4 3
A⊕B C
A’B
1 2
HS
4
3
A⊕B⊕C (A ⊕ B)’ C
D E
B A’B C
•
C
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1 2
HS
4 3
(A’B) ⊕ C (A’B)’ C
F G
CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Design of an 8421 BCD Adder Objective is to add two decimal digits, each expressed in 8421 BCD code. Inputs:
(i) Two four-bit numbers 〈A3, A2, A1, A0〉 and 〈B3, B2, B1, B0〉, each denoting a decimal digit in 8421 code, and (ii) a carry-in bit Cin, where 〈A3, A2, A1, A0〉 is the augend and 〈B3, B2, B1, B0〉 is the addend.
Outputs:
(i)A four-bit number 〈S3, S2, S1, S0〉 that is the sum, and (ii) a carry-out bit C.
Components available: 4-bit binary adders and simple logic gates. Here is the block diagram of the 8421 BCD adder at the highest level of abstraction. A3 A2 A1 A0 B3 B2 B1 B0 8421 BCD Adder
C
Cin
S3 S2 S1 S0 The outputs corresponding to the decimal sum (0 – 19) appear in the following table.
Decimal sum
C
S3
S2
S1
S0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
First employ a 4-bit binary adder to add 〈A3, A2, A1, A0〉, 〈B3, B2, B1, B0〉 and Cin as if they were usual binary numbers. Let outputs from the adder be K and 〈Z3, Z2, Z1, Z0〉. The block diagram at this level of abstraction appears below.
K
A3 A2 A1 A0
B3 B2 B1 B0
1
5
2
3
4
6
7
8
4-bit Binary Adder
14 13
C
12
Z3
S3
11
Z2
S2
10
Z1
S1
Cin
9
Z0
S0
The design is obviously incomplete at this point. The following table relates the intermediate outputs K and 〈Z3, Z2, Z1, Z0〉 with the desired outputs C and 〈S3, S2, S1, S0〉. Decimal sum
K
Z3
Z2
Z1
Z0
C
S3
S2
S1
S0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Remark: The intermediate outputs K and 〈Z3, Z2, Z1, Z0〉 correspond to usual binary representation of the decimal sum. It is not difficult to see from the preceding table that C = 1 if and only if the following holds: i. ii. iii.
K = 1, or Z3 = Z2 = 1, or Z3 = Z1 = 1.
Accordingly, C = K + Z3Z2 + Z3Z1. Finally, 〈S3, S2, S1, S0〉 is obtainable from C and 〈Z3, Z2, Z1, Z0〉 as follows: • •
If C = 0, then add 〈0, 0, 0, 0〉 to 〈Z3, Z2, Z1, Z0〉, and If C = 1, then add 〈0, 1, 1, 0〉 to 〈Z3, Z2, Z1, Z0〉.
In each case, discard the carry, if any. (In fact, carry will be generated in the second case only.) Here is the final implementation of the circuit. A3 A 2 A1 A0
K
1 14
2 3
B3 B2 B 1 B 0
4
5
6 7
4-bit Binary Adder 13
12
Z3
Z2
11
Z1
8 9
Cin
10
Z0
C
0 1 14
0 2 3
4
5
6 7
4-bit Binary Adder 13
12
11
10
S3
S2
S1
S0
8 9
0
Note: Input carry to the second binary adder is fixed at 0, while output carry is discarded.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Design of an Excess-three Adder Objective is to add two decimal digits, each expressed in excess-three code. Inputs:
(i) Two four-bit numbers 〈A3, A2, A1, A0〉 and 〈B3, B2, B1, B0〉, each denoting a decimal digit in excess-three code, and (ii) a carry-in bit Cin, where 〈A3, A2, A1, A0〉 is the augend and 〈B3, B2, B1, B0〉 is the addend.
Outputs: (i)A four-bit number 〈S3, S2, S1, S0〉 that is the sum, and (ii) a carry-out bit C. Components available: 4-bit binary adders and simple logic gates. Here is the block diagram of the excess-three adder at the highest level of abstraction.
The outputs corresponding to the decimal sum (0 – 19) appear in the following table. Decimal sum
C
S3
S2
S1
S0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1
0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1
1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
First employ a 4-bit binary adder to add 〈A3, A2, A1, A0〉, 〈B3, B2, B1, B0〉 and Cin as if they were usual binary numbers. Let outputs from the adder be K and 〈Z3, Z2, Z1, Z0〉. The block diagram at this level of abstraction appears below.
K
A3 A2 A1 A0
B3 B2 B1 B0
1
5
2
3
4
6
7
8
4-bit Binary Adder
14 13
C
12
Z3
S3
11
Z2
S2
10
Z1
S1
Cin
9
Z0
S0
The design is obviously incomplete at this point. The following table relates the intermediate outputs K and 〈Z3, Z2, Z1, Z0〉 with the desired outputs C and 〈S3, S2, S1, S0〉. Decimal sum
K
Z3
Z2
Z1
Z0
C
S3
S2
S1
S0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1
1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1
0 1 1 1 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 1
1 0 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Remark: Since augend and addend to the binary adder are both in excess-three, the intermediate outputs K and 〈Z3, Z2, Z1, Z0〉 correspond to excess-six representation of the decimal sum. It is clear from the preceding table that C = K. Further, 〈S3, S2, S1, S0〉 is obtainable from K and 〈Z3, Z2, Z1, Z0〉 as follows: • •
If K = 0, then add 〈1, 1, 0, 1〉 to 〈Z3, Z2, Z1, Z0〉, and If K = 1, then add 〈0, 0, 1, 1〉 to 〈Z3, Z2, Z1, Z0〉.
In each case, discard the carry, if any. (In fact, carry will be generated in the first case only.) Remark: The following is equally correct: • •
If K = 0, then subtract 〈0, 0, 1, 1〉 from 〈Z3, Z2, Z1, Z0〉, and If K = 1, then add 〈0, 0, 1, 1〉 to 〈Z3, Z2, Z1, Z0〉.
However, from implementation point of view, the former solution is better: Uniformly employ two 4-bit binary adders, and discard the carry (if any) from the second adder. Here is the final implementation of the circuit.
Note: Input carry to the second binary adder is fixed at 0, while output carry is discarded.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Design of an 8421 BCD Subtractor Objective is to subtract a decimal digit from another, where each digit is expressed in 8421 BCD code. Inputs:
(i) Two four-bit numbers 〈X3, X2, X1, X0〉 and 〈Y3, Y2, Y1, Y0〉, each denoting a decimal digit in 8421 BCD code, and (ii) a borrow-in bit Bin, where 〈X3, X2, X1, X0〉 is the minuend and 〈Y3, Y2, Y1, Y0〉 is the subtrahend.
Outputs: (i)A four-bit number 〈D3, D2, D1, D0〉 that is the difference in 8421 code, and (ii) a borrow-out bit B. Components available: 4-bit binary subtractors and simple logic gates. Here is the block diagram of a 4-bit binary subtractor that is the most important component in the present design.
Following is the block diagram of the desired 8421 BCD subtractor at the highest level of abstraction.
Note that when a decimal digit is subtracted from another (taking into account the borrow-in), the result is a number between –10 and +9. The desired outputs corresponding to the decimal difference appear in the following table.
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CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Decimal difference
B
D3
D2
D1
D0
9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
First employ a 4-bit binary subtractor where 〈X3, X2, X1, X0〉, 〈Y3, Y2, Y1, Y0〉, and Bin are input as if they were usual binary numbers. Let outputs from this subtractor be b and 〈P3, P2, P1, P0〉. The block diagram at this level of abstraction appears below.
b
X3
X2 X1 X0
Y3
Y2 Y1 Y0
1
2
5
6
14
3
4
4-bit Binary Subtractor 13
B
12
P3
D3
7
11
P2
D2
D1
8 9
10
P1
P0
D0
The design is obviously incomplete at this point. The following table relates the intermediate outputs b and 〈P3, P2, P1, P0〉 with the desired outputs B and 〈D3, D2, D1, D0〉.
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Bin
CSCI 220: Computer Architecture-I: Adder-like Circuits (Instructor: Pranava K. Jha)
Decimal difference 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10
b 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
P3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
P2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
P1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
P0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
B 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
D3 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
D2 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0
D1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0
D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Observe that B = b. Further, if b = 0, then 〈D3, D2, D1, D0〉 = 〈P3, P2, P1, P0〉 – 〈0, 0, 0, 0〉, and if b = 1, then 〈D3, D2, D1, D0〉 = 〈P3, P2, P1, P0〉 – 〈0, 1, 1, 0〉. Here is the final implementation of the circuit.
Note: Borrow-in to the second subtractor is fixed at 0, while borrow-out is discarded.
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