Defect-oriented fault simulation and test ... - Semantic Scholar
Defect-Oriented Fault Simulation and Test Generation in Digital Circuits W .Kuzmicz, W .Pleskacz Warsaw University of Technology
shown that high SAF coverage cannot quarantee high quality of testing, for example, for CMOS integrated circuits [3-51.The reason is that the SAF model ignores the actual behaviour of digital circuits implemented as CMOS integrated circuits, and does not adequately represent the majority of real IC defects and failure mechanisms which often do not manifest themselves as stuck-at faults. The types of faults that can be observed in a real gate depend not only on the logic function of the gate, but also on its physical design. These facts are well known [4-71 but usually ignored in engineering practice. In earlier works on layout-based test generation techniques [6,7] the whole circuits having hundreds of gates were analysed as single blocks. Such an approach is computationally expensive and thus highly impractical as a method of generation of tests for real VLSI designs. In this work we characterise faults in library cells, determine kinds of faults and their probabilities and then use this information for defect oriented fault simulation and test generation at higher levels of abstraction. This approach is based on the assumption that the majority of defects occur inside the cells and not in the routing between them. Such assumption would not be realistic in the case of older CMOS technologies with two levels of metal and very dense routing. However, in state-of-the-art deep submicron technologies still only one or two levels are used inside cells but 6 or more levels of metal are available for routing. More routing levels means lower sensitivity to defects. Routing between the cells is less dense and various nodes are routed at various metal levels. As a result, probability of shorts outside cells is significantly reduced. In this work we verify functionality of analysed gates for all possible defects and find the actual functions performed, using transistor-level simulation. This characterisation process may be computationally expensive, but it is performed only once for every library cell. In other words, we replace abstract fault models like SAF with realistic defect models. In [8] a new approach was introduced for hierarchical defect simulation based on defect preanalysis for components, and using the results of preanalysis in higher level fault simulation. Here, we generalize this approach by introducing a functional fault model as a method for mapping faults from one hierarchical level to another.
Abstract A generalized approach is presented to fault simulation and test generation based on a uniform functional fault model for different system representation levels. The fault model allows to represent the defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generalized differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for the higher level fault simulation purposes. In such a way, the functional fault model can be regarded as interface for mapping faults from one system level to another, helping to carry out hierarchical fault simulation and test generation in digital systems. A methodology is proposed which allows to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. Experimental data of the hierarchical defect-oriented simulation for ISCAS’85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation based on counting defects without considering defect probabilities may lead to considerable overestimation of results.
1. Introduction Testing and diagnosis of VLSI circuits and digital systems have faced a lot of problems produced by continuous emerging of new technologies and.by growing complexity of circuits and systems. The efficiency of test generation (test quality, generation speed) is highly depending on the system description and fault models. Since traditional low-level test generation methods and tools for complex VLSI systems have lost their importance, other approaches based mainly on functional, behavioral, or hierarchical methods are gaining more and more popularity [l-21. The advantage of hierarchical test generation approaches compared to the functional ones lies in the possibility of constructing test plans at higher functional levels, and modeling faults at lower levels. Traditionally used very popular stuck-at fault (SAF) model has not withstood the test of time. It has been
365 0-7695-1025-6/01$10.00 0 2001 IEEE
J.Raik, R.Ubar Tallinn Technical University
Based on this approach, hierarchical algorithms for dafect-oriented fault simulation and test generation are developed and implemented. The functional fault model in a form of a set of logical conditions allows to represent the defects in components and in the communication networks by the same technique. Then we propose a methodology which allows to find the types of logic faults that may occur in a real circuit, to determine their probabilities of occurrence, and to find the input test pattems that detect these faults. We compare the results obtained in this way with the results of testing of the same circuits by the sequences of test patterns based on the conventional fault model. Experiments were carried out for the ISCAS'85 benchmark circuits. The paper is organized as follows. In Section 2 we present a new method of parametric fault modeling for carrying out defect analysis in digital circuits. In Section 3 we define the functional fault model which will be used as a interface for mapping faults from one hierarchical level to another. In Section 4 we propose a uniform hierarchical approach to test based on the functional fault model. Section 5 presents the results of a probabilistic analysis of defects and relates the defects to the functional fault model. In Section 6 we propose a new hierarchical defect oriented fault simulator and a random test generator. Section 7 presents experimental results, and finally, in Section 8 we draw the conclusions of this research.
l(xI
A
x 2 ) in the case of the defect d can be represented
as Y
=ffXi,X2J3Jd=
4x1
X 5 ) m z = 1 ( X 1 ~ fX3A -C4)) m2).
Introduce now a generalized parametric function y* =f*( X I , ~ 2 ..., , x,, x,,], ... xP, d ) = -7d & f v d & f as a function of a defect variable d , which describes the behavior of the component simultaneously for both possible cases. For the erroneous case the value of the defect variable d as a parameter is equal to 1, and for the nonerroneous case d = 0. In other words, y* = f if d = 1, and y* = f if d = 0. The solution of the Boolean differential equation ap/ad= 1 (1) describes now the conditions (constraints) which activate the fault d o n a line y (Fig.2). For example for the short in Fig.1 we have y* = y d f i d f = ~ d ? ( x l A x2) v d( - K I - + X ~A xq) v-x2). W'=ay*/ad =x~x2x3x4. The parametric modeling of a given physical defect d by equation (1) allows us to use the solutions W', either in defect-oriented fault simulation, for checking if the condition (1) for a given defect d is fulfilled (if the defect d is activated), or - in defect-oriented test generation, to solve the differential equation (1) with tlhe goal to activate the given defect d. To find the parametric fault model fix a given defect d we have to create the corresponding logical expression for the faulty functionsf either by logicall reasoning or by carrying out directly defect simulation. Some examples of the conditions W' for different type of defects (where stuck-at-fault (SAF) is a particular case) are given in Table 1 (here xk is the otiservable variable, and x'k is the variable at the previous time moment).
w'=
2. Parametric defect modeling In this Section we present a new general fault model for describing and modeling arbitrary physical dejects in components of digital circuits that result in a viola.tion of the logical function of a component. Consider a Boolean function y = f (xl, x2, ..., x,) implemented by an embedded component in a digital circuit. Introduce a Boolean variable d for representing a given defect in the component or in the neighbourhood layout of the component, which may affect the value y by converting the Boolean function f into another function d ~ 2 ...> , xn, x n + / , ... xp). y =f ... xp belong to the Here, the variables x,,,, neighbourhood layout of the component which will influence the function y in the presence of defect d.
Table 1. Activating conditions for different defects Defect I Conditions W
I No I
Short between xk and X I Exchange of lines xk and xI
xk = 1 , q = 0
Delay fault on the line xk
xk =
I
xk = 1, xI = 0, or
1, x ' k = 0, or
The conditions wd for activating defects d can be used at the higher (logical or register transfer) level either for fault simulation or for test pattern generation without paying attention to the physical reasons of defects.
3. Concept of the functional fault model The method of defect modeling by logical conditions (see Fig. 2) can be generalized for the purpose of hierarchical fault simulation.
Figure 1. A short between two signal leads
For example, assume there is a short between leeds xl and x5 in the circuit in Fig. 1. The faulty function y =f(xl,xz) =
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I Component
components of a circuit without going into structural details of components and for structural defects in the communication network of components. In both cases, a condition W describes how a lower level fault r (either in a component or in a network) should be activated at a higher level to a given node in a circuit. The conditions U" can be used both in fault simulation and in test generation. Consider a node k in a circuit as the output of a module Mk. and represented by a variable xk.. Associate with the node k a set of faults Rk = RFkV Rsk where RFkis the subset of faults in the module Mkrand RSk is a subset of structural faults (defects) in the the condition when "neighborhood" of Mk. Denote by the fault r E Rk will change the value of xk. An arbitrary erroneous change of the value of xk (denoted by dxk = 1) can be represented formally by implication
I
Fig. 2. Functionalfault model for a physical defect A module (e.g. a library component) in a circuit can be preprocessed by lower level fault simulation with the goal to generate a set of logical conditions W = { W ) for all possible lower level faults r of the component. Each condition W can be regarded as a higher level functional fault model for a given lower level fault r, since in the presence of the fault r the functional behavior of the component at the input stimuli W = 1 will be faulty. Definition I : We call a failed input pattem t, of a given module M (complex gate or component) a functional fault if it detects at the output of M at least one lower level fault 5 in the module M. The functional fault model can be regarded as a uniform way of mapping faults between two hierarchical levels. For example, we can map by the same way both, the gate level stuck-at faults or the physical defects of a component in a circuit to the higher behaviour level of the same component. The input pattems t, for a given fault r, can be found either by traditional gate level test generation (e.g. for stuck-at faults) or by parametric fault modeling and solving corresponding differential equations (1) for physical level defects. Definition 2: We call a set of functional faults which cover all the lower level faults of the component a functional fault model of the component. Using the conception of the functional fault model allows to reduce the complexity of fault modeling if the number of higher level faults is less than the number of lower level faults. For example, for the ISCAS'85 benchmark circuit c17, it was possible to replace 78 lower level physical defects by only 4 functional faults (see Section 6). The complexity reduction in this particular case is 20 times. On the other hand, the functional fault model allows to process all the lower level faults by means of higher level language. No disclosure of the intemal stucture of the component for modeling lower level faults is needed. In general, the functional fault model is not unique. The given set of low level faults can be covered by different high level functional faults (sets of input patterns of the module). This fact should be considered both, in hierarchical fault simulation and test generation.
w
+v
w),
dXk (rA rE Rk. (2) All the suspected faults can now be determined by solving the equation (3) In such a way we should construct for each module Mk of the circuit a list of faults Rk with logical conditions for each fault r E Rk. The conditions for functional faults r E RFkof the module can be found, for example, by low level (gate level) test generation for the stuck-at faults in the module. When defect-oriented test method is chosen, then the activisation conditions for defects can be found by parametric defect modeling and solving the equation (1). The conditions for structural faults (or defects) in the network (in the neighbourhood of the module) can be calculated also by parametric fault modeling and solving the corresponding equations (1). In Fig. 3, a hierarchical test conception based on parametric fault modeling and functional fault model for a 3-level system is illustrated. In the functional approach, only the information about the functional behaviour is used. In the structural approach, tests are targeted to detect the faults in the networked components and in the network communication. For gates usually stuck-at faults are the basis of test generation. In some sense, this method can be regarded as a functional approach. Using the layout information of the circuit of the gate, physical defects can be selected, and after parametric modeling and solving the equation (1), a set of activation conditions wflki for a given gate Gki can be created. The test pattems generated in such a way form a set of conditions v k ; which can be regarded as a functional fault model for this gate in a network level. The network structural faults (defects in the layout) can be modeled parametrically for creating a set of conditions
w
4. Uniform hierarchical approach to test The method of modeling faults by logic conditions W allows to unify the functional level fault simulation for
367
Pkiwhich together with the sets of flkifor all gates in the network form a test for the given module Gk. This test in its tum can be regarded as a functional fault model flk for the module in a system level etc. Functional approach
i 1
Structural approach
System Network of modules
Fig.3. Hierarchical test approach In such a way, at each level the faults in a system under test are represented by the functional model as a set of where fl represents functional conditions W = WFv faults in the components of the network and represents structural faults in the network.
5. Probabilistic defect modeling In the following we consider one kind of physical defects in CMOS gates - shorts belween conducting regions. This is one of the most important sources of faults in CMOS digital circuits. However, the methodology can be extended to other types of physical defects as well (e.g. breaks). A short is a piece of extra conducting material that connects a pair of separate conducting regions in the circuit. This affects the connectivity of the circuit - two separate nodes become connected. It is intuitively obvious that probabilities of shorts depend on the layout of the circuit. Conducting regions that are adjacent to one another are more susceptible to shorts than regions that are separated by a large distance. We assume that every defect that results in a short can be approximated by a circle. To estimate the probabilities of shorts between pairs of nodes we use the concept of critical area for shorts [ 5 ] . The critical area is such a region in the circuit that if the center of a defect of a given radius R is located anywhere inside the critical region, a :short between two adjacent conducting regions occurs. The critical area is the area of the critical region. It depends on the shapes and locations of the conducting regions that can be shorted and is a function of the defect radius R . The radii of defects are random and can be characterised by a probability density function Pd$R) which is specific for a given manufacturing process and given conducting layer.
Table 2. Conditional probabilities of and-type shorts in the complex gate AND2,2/NOR2 and tlhe fault table
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a module and yc is the output of a gate with a physical defect d, then the condition to detect the defect d on the observable test point Y of the system is w A dyM/&, A I@= 1, where is the Boolean derivative calculated by the high-level simulation, &, /&, is the Boolean derivative calculated by the gate-level simulation, and is the functional fault condition found by the gate preanalysis.
We assume that the probability of a short between a pair of conducting regions that correspond to a pair of electrical nodes is proportional to the critical area for these two regions. The critical area for shorts is a function P d R ) of the defect radius R. Since the defect radii exhibit a random distribution, the product PdflR) * P,(R) integrated over the range of R where P,(R) > 0 can be taken as the measure of the total probability of shorts between a given pair of nodes. Pt = /P,(R) PdjfR) dR The first step in identification of logic faults and their probabilities is to calculate Pt for all pairs of conducting regions representing electrical nodes. If for a given pair Pt = 0, this pair of nodes cannot be shorted and is not taken into account. For the pairs that can be shorted the logic faults are determined. In simple cases this can be done by inspection of the circuit, for example it is obvious that a short between an output node and VDD results in “stuck-at-1” fault at this node. In more complex cases it may be necessary to simulate operation of the faulty circuit at the transistor level by SPICE. In our simulations shorts were represented by resistors. We tried several resistance values in the range from 0.01 ohm to 200 ohm. The gate behaviour at the logic level did not depend on this resistance. The waveforms obtained from the simulation allow to determine the actual logic function performed by the faulty circuit. In this way the functional faults that result from shorts are identified and their probabilities are determined. This procedure and the software developed for this purpose are described in more detail elsewhere [lo]. Table 2 shows the distribution of the probabilities of various types of functional faults for a complex 4 input gate performing the AND2,2/NOR2 function. This gate is from an industrial standard cell library in 0.8 micron CMOS technology. Usually the most time consuming part of the characterisation process is the identification of the logical faults that correspond to shorts. If the number of possible shorts is large and operation of faulty cell is not obvious for most of them, it is necessary to perform many circuit simulations. This is time consuming and difficult to automate. Hence, the complexity of the characterisation process depends mainly on the number of physically possible shorts in the characterised cell and the complexity of the cell function.
a/&,,,
Functional fault activated
1
Functional
High-level
___, simulation
Sate-level simulation
Gate-level fault analysis
System Fig. 4. Hierarchical defect oriented fault simulation The relationships between the functional faults (patterns) ti and the defects d, for all the gates g in the library L are given by defect tables DT, = I I d , 1 1 , g E L, where an entry d, = 1 means that the input pattern t, of the gate detects the defect d, , otherwise d,f = 0. Let D, be a set of defects in the gate g E L. Then for each gate g E L we create a set of probabilities P8 where each entry pf E P, means the conditional probability of a defect d, E D, in the condition that a defect is present in the system. The multi-level functional fault simulation is carried out as follows (see Fig. 4): on the defect level we relate the physical defects of complex gates to the functional fault model by fixing which defects are detected by which input pattern of the gate; this information is stored in the library fault tables; on the logical level we check if the functional faults of the given gate are activated and propagated to the output of the given module, and on the RTL level we check if the erroneous signals caused by defects are propagated from the outputs of modules to an observable point of the system. where ti c T, means that the test pattern T, includes the input pattern t, of the gate g,. For carrying out the experimental part of this work, a hierarchical two-level defect oriented fault simulation technique was implemented. The method consists of the following two steps: traditional gate-level stuck-at fault simulation with the goal of creating a fault table for stuck-at faults of
6. Hierarchical fault simulation Consider a task of defect oriented fault simulation in a system which is simulated at three levels: register transfer, gate and defect levels (Fig. 4). Formally, if Y is the system variable representing an observable point of the system, yu is an output variable of
369
a gate-level circuit, i.e. of finding all the cases when dxk = 1 in (2), and defect oriented functional fault simulation based on solving the equation (3) for all xk where dxk = 1 with the goal of fixing the subsets of defects detected in all the gates of the given circuit. On the first step, for a given module a fault table FT = I I tf) I is created for the stuck-at faults x, = e, e E {O,l}at the outputs of complex gates g,, where an entry rf, = e means that a test pattern T, of the circuit detects the fault x, = e , otherwise tq = X where X means don’t care. On the other hand, each entry tlJ ~ ( 0 , 1 }in FT means that a functional fault tf of the gate g, is detected on its output x,. On the second step, for each t, in the fault table FT, a subset of defects D,,(rJ c D,, will be fixed for the gate g, detected by the test pattern T, by the following operation: D,,,frJ = (d, I j : 4, = 1 & , r, c T, I , where r, c TI means that the test pattem T, includes the input pattern r, of the gate g,. Based on this simulator we implemented also a random test pattern generator (D-TPG) targeted for detecting physical defects in the circuit.
Circuit c17 c432 c499
7. Experimental results The purpose of experiments carried out with the prototypes of defect oriented fault simulator and test generator was twofold: 1) to compare the quality of 100% stuck-at test pattems in relation to physical CMOS defects for the family of ISCAS’85 benchmark circuits, and 2) to compare the efficiencies of stuck-at fault based test generator (S-TPG) with defect oriented test generator (D-TPG) for the same circuits. For carrying out the experiments we used the data produced by probabilistic analysis of the physical defects of the AND2,2/NOR2 gate (Table 2), ‘and we resynthesized the ISCAS’85 circuits trying to use as much as possible this complex gate. Let D be a set of physical defects under consideration. The 25 defects d c D of the complex gate AND2,2/NOR2 are listed in Table 2 together with the erroneous functions fd. A,B,C,D are the inputs of the gate, Q is the output and N1 is an internal node of the gate. All the defects covered by each input pattern of the gate are marked by 1 . For each defect d, the probabilities P, are also given.
Total #of
#of complex
gates
gates
6 152
1
Fault cover, 76 100.0
12
100.0
67
108
100.0 100.0 100.0 100.0
96
c880
356 293
c1355 cl908 c3540 c5315
1035
53
s
t
u
c
k
F
i
attems 6
60
100.0 100.0
100.0 Defect-oriented fault simulation For the ISCAS’85 circuits was carried out hierarchically in two steps. At first, for each complex gate in the circuits the functional fault coverage was calculated. Then, at the lower level, the real defect coverage for these gates basedl on the functional fault coverages of gates and on the data in Table 2 was calculated. The computed fault coverages for the parts of circuits consisted only of the complex gates AND2,2/ NOR2 are depicted in Table 5. From Table 4 we see that even for the chosen subset of physical defects - the shorts in the layout (breaks and opens were not considered) the quality of stuck-at test would not be sufficent. On the other hand, we see that the defect coverages in Table 5 are higher than in the worst case test for the complex gate in Table 3. The only case where the lowest defect coverage (85,35%) was reached is the circuit c6288. This observation leads to a conclusion that a 100% stuckat fault test for a whole circuit covers defects in components in average better than the worst case 100% stuck-at fault tests of components. In fact, it is not surprising that the 100% stuck-at fault tests can not achieve the 100% defect coverage. The main result of the paper is to present a new method and a tool for efficient calculation of the exact defect coverage for given test sets. By this tool it is possible to show
Table 3. Testing of the gate AND2,2/NOR2
We generated for the complex gate AND2,2/NOR2 a test set T = {0101,1010,1011,1110) with 100% stuck-at
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quantitatively the real quality of the given test sets e.g. of tests expected to have 100% quality.
this method, the conditional probabilities of defects can be also used in probabilistic defect coverage calculation. This method was generalized to a uniform approach to map faults from one level to another in system hierarchical representation. For carrying out experimental work, a hierarchical two-level defect oriented fault simulator was implemented. The simulator was used also in implementing a defectoriented random test pattern generator. A probabilistic analysis of CMOS physical defects has been carried out for generating input data for stuck-at-fault test quality estimation. Based on these data, and by using the implemented tools it was possible to show quantitatively the real quality of test expected to have 100%quality. It was shown also that the classical test coverage calculation based on counting defects without taking into consideration defect probabilities may lead to considerable overestimation of the quality of tests for CMOS circuits.
Table 5. Data of defect-oriented fault simulation Defect coverage, % Circuit OR-type shorts 1 AND-type shorts Counted I Probabil. 1 Counted I Probabil.
Acknowledgements
Circuit
This work has been supported by the EC project INCOCOPERNICUS 977 133 VILAB “Microelectronics Virtual Laboratory for Cooperation in Research and Knowledge Transfer”, by the Estonian Science Foundation grant G3658, and by the Polish State Committee for Scientific Research grant for international cooperation with Ukraine. The authors are grateful for Dr. M.Blyzniuk and Dr. M.Lobur from Lviv Polytechnic, Lviv, Ukraine for their important contribution in earlier stages of this work described in [8] and [lo].
Defect coverage, % OR-type shorts I AND-type shorts Counted 1 Probabil. 1 Counted 1 Probabil.
References [I] S.R.Rao, B.Y.Pan, J.R.Armstrong. Hierarch. Test Generation for VHDL Behavioral Models. EDAC, Feb. 1993,pp. 175-183. [2] E.M.Rudnick, R.Vietti, A.Ellis, F.Como, P.Prinetto, M.Sonza Reorda. Fast sequential circuit test generation using high-level and gate-level techniques. Proc. of DATE, 1998. [3] J.M. Soden, C.F. Hawkins. Quality Testing Requires Quality Thinking. Proc. Int. Test Conference, 1993,pp.596. [4] W.Maly, J.P.Shen, J.Ferguson. System. Characterization of Physical Defects for Fault Analysis of MOS IC Cells. Proc. 1984 ITC, pp. 390-399,Philadelphia, 1984. [5] J.P.Shen, W.Maly, J.Ferguson. Inductive Fault Analysis of MOS ICS. IEEE DesignLkTest,pp.13-26, 1985. [6] P.Nigh,W.Maly. Layout - Driven Test Generation. Proc.1989 ICCAD, pp. 154-157,1989. [7] M.Jacomet, WGuggenbuhl. Layout-Dependent Fault Analysis and Test Synthesis for CMOS Circuits. IEEE Trans. on CAD, vol. 12, pp. 888-899, 1993. [8] M.Blyzniuk, FT.Cibakova, EGramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical DefectOriented Fault Simulation for Digital Circuits. European Test Workshop, Cascais, Portugal, Mai 23-26,2000, pp.151-156. [9] W.Maly. Modeling of Litography-Related Yield Losses for CAD in VLSI. IEEE Trans. on CAD, vo1.4, pp.166-177, 1985. [lo] M.Blyzniuk, W.Pleskacz, M.Lobur, W.Kuzmicz. Estim. of Probability of Functional Faults Caused by Spot Defects in VLSI. Proc. TCSET 2000 Conf., Slavsko, Ukraine, 2000.
The new result in this paper is also to show that the quality of tests in terms of defect coverage is higher when the defect probabilities are not taken into account (see Tables 3, 5 and 6). From this result, we can conclude that the traditional methods of test coverage measuring based on simply counting of not detected defects, where all the faults are assumed to have the same probability, are tending to be overestimated.
8. Conclusions A new hierarchical defect modeling method has been developed and implemented as a tool. In this method, we use a new functional fault model developed for representing defects on the higher level, and the fault-todefect mapping in the form of defect coverage table. In
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shown that high SAF coverage cannot quarantee high quality of testing, for example, for CMOS integrated circuits [3-51.The reason is that the SAF model ignores the actual behaviour of digital circuits implemented as CMOS integrated circuits, and does not adequately represent the majority of real IC defects and failure mechanisms which often do not manifest themselves as stuck-at faults. The types of faults that can be observed in a real gate depend not only on the logic function of the gate, but also on its physical design. These facts are well known [4-71 but usually ignored in engineering practice. In earlier works on layout-based test generation techniques [6,7] the whole circuits having hundreds of gates were analysed as single blocks. Such an approach is computationally expensive and thus highly impractical as a method of generation of tests for real VLSI designs. In this work we characterise faults in library cells, determine kinds of faults and their probabilities and then use this information for defect oriented fault simulation and test generation at higher levels of abstraction. This approach is based on the assumption that the majority of defects occur inside the cells and not in the routing between them. Such assumption would not be realistic in the case of older CMOS technologies with two levels of metal and very dense routing. However, in state-of-the-art deep submicron technologies still only one or two levels are used inside cells but 6 or more levels of metal are available for routing. More routing levels means lower sensitivity to defects. Routing between the cells is less dense and various nodes are routed at various metal levels. As a result, probability of shorts outside cells is significantly reduced. In this work we verify functionality of analysed gates for all possible defects and find the actual functions performed, using transistor-level simulation. This characterisation process may be computationally expensive, but it is performed only once for every library cell. In other words, we replace abstract fault models like SAF with realistic defect models. In [8] a new approach was introduced for hierarchical defect simulation based on defect preanalysis for components, and using the results of preanalysis in higher level fault simulation. Here, we generalize this approach by introducing a functional fault model as a method for mapping faults from one hierarchical level to another.
Abstract A generalized approach is presented to fault simulation and test generation based on a uniform functional fault model for different system representation levels. The fault model allows to represent the defects in components and defects in the communication network of components by the same technique. Physical defects are modeled as parameters in generalized differential equations. Solutions of these equations give the conditions at which defects are locally activated. The defect activation conditions are used as functional fault models for the higher level fault simulation purposes. In such a way, the functional fault model can be regarded as interface for mapping faults from one system level to another, helping to carry out hierarchical fault simulation and test generation in digital systems. A methodology is proposed which allows to find the types of faults that may occur in a real circuit, to determine their probabilities, and to find the input test patterns that detect these faults. Experimental data of the hierarchical defect-oriented simulation for ISCAS’85 benchmarks are presented, which show that classical stuck-at fault based simulation and the test coverage calculation based on counting defects without considering defect probabilities may lead to considerable overestimation of results.
1. Introduction Testing and diagnosis of VLSI circuits and digital systems have faced a lot of problems produced by continuous emerging of new technologies and.by growing complexity of circuits and systems. The efficiency of test generation (test quality, generation speed) is highly depending on the system description and fault models. Since traditional low-level test generation methods and tools for complex VLSI systems have lost their importance, other approaches based mainly on functional, behavioral, or hierarchical methods are gaining more and more popularity [l-21. The advantage of hierarchical test generation approaches compared to the functional ones lies in the possibility of constructing test plans at higher functional levels, and modeling faults at lower levels. Traditionally used very popular stuck-at fault (SAF) model has not withstood the test of time. It has been
365 0-7695-1025-6/01$10.00 0 2001 IEEE
J.Raik, R.Ubar Tallinn Technical University
Based on this approach, hierarchical algorithms for dafect-oriented fault simulation and test generation are developed and implemented. The functional fault model in a form of a set of logical conditions allows to represent the defects in components and in the communication networks by the same technique. Then we propose a methodology which allows to find the types of logic faults that may occur in a real circuit, to determine their probabilities of occurrence, and to find the input test pattems that detect these faults. We compare the results obtained in this way with the results of testing of the same circuits by the sequences of test patterns based on the conventional fault model. Experiments were carried out for the ISCAS'85 benchmark circuits. The paper is organized as follows. In Section 2 we present a new method of parametric fault modeling for carrying out defect analysis in digital circuits. In Section 3 we define the functional fault model which will be used as a interface for mapping faults from one hierarchical level to another. In Section 4 we propose a uniform hierarchical approach to test based on the functional fault model. Section 5 presents the results of a probabilistic analysis of defects and relates the defects to the functional fault model. In Section 6 we propose a new hierarchical defect oriented fault simulator and a random test generator. Section 7 presents experimental results, and finally, in Section 8 we draw the conclusions of this research.
l(xI
A
x 2 ) in the case of the defect d can be represented
as Y
=ffXi,X2J3Jd=
4x1
X 5 ) m z = 1 ( X 1 ~ fX3A -C4)) m2).
Introduce now a generalized parametric function y* =f*( X I , ~ 2 ..., , x,, x,,], ... xP, d ) = -7d & f v d & f as a function of a defect variable d , which describes the behavior of the component simultaneously for both possible cases. For the erroneous case the value of the defect variable d as a parameter is equal to 1, and for the nonerroneous case d = 0. In other words, y* = f if d = 1, and y* = f if d = 0. The solution of the Boolean differential equation ap/ad= 1 (1) describes now the conditions (constraints) which activate the fault d o n a line y (Fig.2). For example for the short in Fig.1 we have y* = y d f i d f = ~ d ? ( x l A x2) v d( - K I - + X ~A xq) v-x2). W'=ay*/ad =x~x2x3x4. The parametric modeling of a given physical defect d by equation (1) allows us to use the solutions W', either in defect-oriented fault simulation, for checking if the condition (1) for a given defect d is fulfilled (if the defect d is activated), or - in defect-oriented test generation, to solve the differential equation (1) with tlhe goal to activate the given defect d. To find the parametric fault model fix a given defect d we have to create the corresponding logical expression for the faulty functionsf either by logicall reasoning or by carrying out directly defect simulation. Some examples of the conditions W' for different type of defects (where stuck-at-fault (SAF) is a particular case) are given in Table 1 (here xk is the otiservable variable, and x'k is the variable at the previous time moment).
w'=
2. Parametric defect modeling In this Section we present a new general fault model for describing and modeling arbitrary physical dejects in components of digital circuits that result in a viola.tion of the logical function of a component. Consider a Boolean function y = f (xl, x2, ..., x,) implemented by an embedded component in a digital circuit. Introduce a Boolean variable d for representing a given defect in the component or in the neighbourhood layout of the component, which may affect the value y by converting the Boolean function f into another function d ~ 2 ...> , xn, x n + / , ... xp). y =f ... xp belong to the Here, the variables x,,,, neighbourhood layout of the component which will influence the function y in the presence of defect d.
Table 1. Activating conditions for different defects Defect I Conditions W
I No I
Short between xk and X I Exchange of lines xk and xI
xk = 1 , q = 0
Delay fault on the line xk
xk =
I
xk = 1, xI = 0, or
1, x ' k = 0, or
The conditions wd for activating defects d can be used at the higher (logical or register transfer) level either for fault simulation or for test pattern generation without paying attention to the physical reasons of defects.
3. Concept of the functional fault model The method of defect modeling by logical conditions (see Fig. 2) can be generalized for the purpose of hierarchical fault simulation.
Figure 1. A short between two signal leads
For example, assume there is a short between leeds xl and x5 in the circuit in Fig. 1. The faulty function y =f(xl,xz) =
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I Component
components of a circuit without going into structural details of components and for structural defects in the communication network of components. In both cases, a condition W describes how a lower level fault r (either in a component or in a network) should be activated at a higher level to a given node in a circuit. The conditions U" can be used both in fault simulation and in test generation. Consider a node k in a circuit as the output of a module Mk. and represented by a variable xk.. Associate with the node k a set of faults Rk = RFkV Rsk where RFkis the subset of faults in the module Mkrand RSk is a subset of structural faults (defects) in the the condition when "neighborhood" of Mk. Denote by the fault r E Rk will change the value of xk. An arbitrary erroneous change of the value of xk (denoted by dxk = 1) can be represented formally by implication
I
Fig. 2. Functionalfault model for a physical defect A module (e.g. a library component) in a circuit can be preprocessed by lower level fault simulation with the goal to generate a set of logical conditions W = { W ) for all possible lower level faults r of the component. Each condition W can be regarded as a higher level functional fault model for a given lower level fault r, since in the presence of the fault r the functional behavior of the component at the input stimuli W = 1 will be faulty. Definition I : We call a failed input pattem t, of a given module M (complex gate or component) a functional fault if it detects at the output of M at least one lower level fault 5 in the module M. The functional fault model can be regarded as a uniform way of mapping faults between two hierarchical levels. For example, we can map by the same way both, the gate level stuck-at faults or the physical defects of a component in a circuit to the higher behaviour level of the same component. The input pattems t, for a given fault r, can be found either by traditional gate level test generation (e.g. for stuck-at faults) or by parametric fault modeling and solving corresponding differential equations (1) for physical level defects. Definition 2: We call a set of functional faults which cover all the lower level faults of the component a functional fault model of the component. Using the conception of the functional fault model allows to reduce the complexity of fault modeling if the number of higher level faults is less than the number of lower level faults. For example, for the ISCAS'85 benchmark circuit c17, it was possible to replace 78 lower level physical defects by only 4 functional faults (see Section 6). The complexity reduction in this particular case is 20 times. On the other hand, the functional fault model allows to process all the lower level faults by means of higher level language. No disclosure of the intemal stucture of the component for modeling lower level faults is needed. In general, the functional fault model is not unique. The given set of low level faults can be covered by different high level functional faults (sets of input patterns of the module). This fact should be considered both, in hierarchical fault simulation and test generation.
w
+v
w),
dXk (rA rE Rk. (2) All the suspected faults can now be determined by solving the equation (3) In such a way we should construct for each module Mk of the circuit a list of faults Rk with logical conditions for each fault r E Rk. The conditions for functional faults r E RFkof the module can be found, for example, by low level (gate level) test generation for the stuck-at faults in the module. When defect-oriented test method is chosen, then the activisation conditions for defects can be found by parametric defect modeling and solving the equation (1). The conditions for structural faults (or defects) in the network (in the neighbourhood of the module) can be calculated also by parametric fault modeling and solving the corresponding equations (1). In Fig. 3, a hierarchical test conception based on parametric fault modeling and functional fault model for a 3-level system is illustrated. In the functional approach, only the information about the functional behaviour is used. In the structural approach, tests are targeted to detect the faults in the networked components and in the network communication. For gates usually stuck-at faults are the basis of test generation. In some sense, this method can be regarded as a functional approach. Using the layout information of the circuit of the gate, physical defects can be selected, and after parametric modeling and solving the equation (1), a set of activation conditions wflki for a given gate Gki can be created. The test pattems generated in such a way form a set of conditions v k ; which can be regarded as a functional fault model for this gate in a network level. The network structural faults (defects in the layout) can be modeled parametrically for creating a set of conditions
w
4. Uniform hierarchical approach to test The method of modeling faults by logic conditions W allows to unify the functional level fault simulation for
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Pkiwhich together with the sets of flkifor all gates in the network form a test for the given module Gk. This test in its tum can be regarded as a functional fault model flk for the module in a system level etc. Functional approach
i 1
Structural approach
System Network of modules
Fig.3. Hierarchical test approach In such a way, at each level the faults in a system under test are represented by the functional model as a set of where fl represents functional conditions W = WFv faults in the components of the network and represents structural faults in the network.
5. Probabilistic defect modeling In the following we consider one kind of physical defects in CMOS gates - shorts belween conducting regions. This is one of the most important sources of faults in CMOS digital circuits. However, the methodology can be extended to other types of physical defects as well (e.g. breaks). A short is a piece of extra conducting material that connects a pair of separate conducting regions in the circuit. This affects the connectivity of the circuit - two separate nodes become connected. It is intuitively obvious that probabilities of shorts depend on the layout of the circuit. Conducting regions that are adjacent to one another are more susceptible to shorts than regions that are separated by a large distance. We assume that every defect that results in a short can be approximated by a circle. To estimate the probabilities of shorts between pairs of nodes we use the concept of critical area for shorts [ 5 ] . The critical area is such a region in the circuit that if the center of a defect of a given radius R is located anywhere inside the critical region, a :short between two adjacent conducting regions occurs. The critical area is the area of the critical region. It depends on the shapes and locations of the conducting regions that can be shorted and is a function of the defect radius R . The radii of defects are random and can be characterised by a probability density function Pd$R) which is specific for a given manufacturing process and given conducting layer.
Table 2. Conditional probabilities of and-type shorts in the complex gate AND2,2/NOR2 and tlhe fault table
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a module and yc is the output of a gate with a physical defect d, then the condition to detect the defect d on the observable test point Y of the system is w A dyM/&, A I@= 1, where is the Boolean derivative calculated by the high-level simulation, &, /&, is the Boolean derivative calculated by the gate-level simulation, and is the functional fault condition found by the gate preanalysis.
We assume that the probability of a short between a pair of conducting regions that correspond to a pair of electrical nodes is proportional to the critical area for these two regions. The critical area for shorts is a function P d R ) of the defect radius R. Since the defect radii exhibit a random distribution, the product PdflR) * P,(R) integrated over the range of R where P,(R) > 0 can be taken as the measure of the total probability of shorts between a given pair of nodes. Pt = /P,(R) PdjfR) dR The first step in identification of logic faults and their probabilities is to calculate Pt for all pairs of conducting regions representing electrical nodes. If for a given pair Pt = 0, this pair of nodes cannot be shorted and is not taken into account. For the pairs that can be shorted the logic faults are determined. In simple cases this can be done by inspection of the circuit, for example it is obvious that a short between an output node and VDD results in “stuck-at-1” fault at this node. In more complex cases it may be necessary to simulate operation of the faulty circuit at the transistor level by SPICE. In our simulations shorts were represented by resistors. We tried several resistance values in the range from 0.01 ohm to 200 ohm. The gate behaviour at the logic level did not depend on this resistance. The waveforms obtained from the simulation allow to determine the actual logic function performed by the faulty circuit. In this way the functional faults that result from shorts are identified and their probabilities are determined. This procedure and the software developed for this purpose are described in more detail elsewhere [lo]. Table 2 shows the distribution of the probabilities of various types of functional faults for a complex 4 input gate performing the AND2,2/NOR2 function. This gate is from an industrial standard cell library in 0.8 micron CMOS technology. Usually the most time consuming part of the characterisation process is the identification of the logical faults that correspond to shorts. If the number of possible shorts is large and operation of faulty cell is not obvious for most of them, it is necessary to perform many circuit simulations. This is time consuming and difficult to automate. Hence, the complexity of the characterisation process depends mainly on the number of physically possible shorts in the characterised cell and the complexity of the cell function.
a/&,,,
Functional fault activated
1
Functional
High-level
___, simulation
Sate-level simulation
Gate-level fault analysis
System Fig. 4. Hierarchical defect oriented fault simulation The relationships between the functional faults (patterns) ti and the defects d, for all the gates g in the library L are given by defect tables DT, = I I d , 1 1 , g E L, where an entry d, = 1 means that the input pattern t, of the gate detects the defect d, , otherwise d,f = 0. Let D, be a set of defects in the gate g E L. Then for each gate g E L we create a set of probabilities P8 where each entry pf E P, means the conditional probability of a defect d, E D, in the condition that a defect is present in the system. The multi-level functional fault simulation is carried out as follows (see Fig. 4): on the defect level we relate the physical defects of complex gates to the functional fault model by fixing which defects are detected by which input pattern of the gate; this information is stored in the library fault tables; on the logical level we check if the functional faults of the given gate are activated and propagated to the output of the given module, and on the RTL level we check if the erroneous signals caused by defects are propagated from the outputs of modules to an observable point of the system. where ti c T, means that the test pattern T, includes the input pattern t, of the gate g,. For carrying out the experimental part of this work, a hierarchical two-level defect oriented fault simulation technique was implemented. The method consists of the following two steps: traditional gate-level stuck-at fault simulation with the goal of creating a fault table for stuck-at faults of
6. Hierarchical fault simulation Consider a task of defect oriented fault simulation in a system which is simulated at three levels: register transfer, gate and defect levels (Fig. 4). Formally, if Y is the system variable representing an observable point of the system, yu is an output variable of
369
a gate-level circuit, i.e. of finding all the cases when dxk = 1 in (2), and defect oriented functional fault simulation based on solving the equation (3) for all xk where dxk = 1 with the goal of fixing the subsets of defects detected in all the gates of the given circuit. On the first step, for a given module a fault table FT = I I tf) I is created for the stuck-at faults x, = e, e E {O,l}at the outputs of complex gates g,, where an entry rf, = e means that a test pattern T, of the circuit detects the fault x, = e , otherwise tq = X where X means don’t care. On the other hand, each entry tlJ ~ ( 0 , 1 }in FT means that a functional fault tf of the gate g, is detected on its output x,. On the second step, for each t, in the fault table FT, a subset of defects D,,(rJ c D,, will be fixed for the gate g, detected by the test pattern T, by the following operation: D,,,frJ = (d, I j : 4, = 1 & , r, c T, I , where r, c TI means that the test pattem T, includes the input pattern r, of the gate g,. Based on this simulator we implemented also a random test pattern generator (D-TPG) targeted for detecting physical defects in the circuit.
Circuit c17 c432 c499
7. Experimental results The purpose of experiments carried out with the prototypes of defect oriented fault simulator and test generator was twofold: 1) to compare the quality of 100% stuck-at test pattems in relation to physical CMOS defects for the family of ISCAS’85 benchmark circuits, and 2) to compare the efficiencies of stuck-at fault based test generator (S-TPG) with defect oriented test generator (D-TPG) for the same circuits. For carrying out the experiments we used the data produced by probabilistic analysis of the physical defects of the AND2,2/NOR2 gate (Table 2), ‘and we resynthesized the ISCAS’85 circuits trying to use as much as possible this complex gate. Let D be a set of physical defects under consideration. The 25 defects d c D of the complex gate AND2,2/NOR2 are listed in Table 2 together with the erroneous functions fd. A,B,C,D are the inputs of the gate, Q is the output and N1 is an internal node of the gate. All the defects covered by each input pattern of the gate are marked by 1 . For each defect d, the probabilities P, are also given.
Total #of
#of complex
gates
gates
6 152
1
Fault cover, 76 100.0
12
100.0
67
108
100.0 100.0 100.0 100.0
96
c880
356 293
c1355 cl908 c3540 c5315
1035
53
s
t
u
c
k
F
i
attems 6
60
100.0 100.0
100.0 Defect-oriented fault simulation For the ISCAS’85 circuits was carried out hierarchically in two steps. At first, for each complex gate in the circuits the functional fault coverage was calculated. Then, at the lower level, the real defect coverage for these gates basedl on the functional fault coverages of gates and on the data in Table 2 was calculated. The computed fault coverages for the parts of circuits consisted only of the complex gates AND2,2/ NOR2 are depicted in Table 5. From Table 4 we see that even for the chosen subset of physical defects - the shorts in the layout (breaks and opens were not considered) the quality of stuck-at test would not be sufficent. On the other hand, we see that the defect coverages in Table 5 are higher than in the worst case test for the complex gate in Table 3. The only case where the lowest defect coverage (85,35%) was reached is the circuit c6288. This observation leads to a conclusion that a 100% stuckat fault test for a whole circuit covers defects in components in average better than the worst case 100% stuck-at fault tests of components. In fact, it is not surprising that the 100% stuck-at fault tests can not achieve the 100% defect coverage. The main result of the paper is to present a new method and a tool for efficient calculation of the exact defect coverage for given test sets. By this tool it is possible to show
Table 3. Testing of the gate AND2,2/NOR2
We generated for the complex gate AND2,2/NOR2 a test set T = {0101,1010,1011,1110) with 100% stuck-at
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quantitatively the real quality of the given test sets e.g. of tests expected to have 100% quality.
this method, the conditional probabilities of defects can be also used in probabilistic defect coverage calculation. This method was generalized to a uniform approach to map faults from one level to another in system hierarchical representation. For carrying out experimental work, a hierarchical two-level defect oriented fault simulator was implemented. The simulator was used also in implementing a defectoriented random test pattern generator. A probabilistic analysis of CMOS physical defects has been carried out for generating input data for stuck-at-fault test quality estimation. Based on these data, and by using the implemented tools it was possible to show quantitatively the real quality of test expected to have 100%quality. It was shown also that the classical test coverage calculation based on counting defects without taking into consideration defect probabilities may lead to considerable overestimation of the quality of tests for CMOS circuits.
Table 5. Data of defect-oriented fault simulation Defect coverage, % Circuit OR-type shorts 1 AND-type shorts Counted I Probabil. 1 Counted I Probabil.
Acknowledgements
Circuit
This work has been supported by the EC project INCOCOPERNICUS 977 133 VILAB “Microelectronics Virtual Laboratory for Cooperation in Research and Knowledge Transfer”, by the Estonian Science Foundation grant G3658, and by the Polish State Committee for Scientific Research grant for international cooperation with Ukraine. The authors are grateful for Dr. M.Blyzniuk and Dr. M.Lobur from Lviv Polytechnic, Lviv, Ukraine for their important contribution in earlier stages of this work described in [8] and [lo].
Defect coverage, % OR-type shorts I AND-type shorts Counted 1 Probabil. 1 Counted 1 Probabil.
References [I] S.R.Rao, B.Y.Pan, J.R.Armstrong. Hierarch. Test Generation for VHDL Behavioral Models. EDAC, Feb. 1993,pp. 175-183. [2] E.M.Rudnick, R.Vietti, A.Ellis, F.Como, P.Prinetto, M.Sonza Reorda. Fast sequential circuit test generation using high-level and gate-level techniques. Proc. of DATE, 1998. [3] J.M. Soden, C.F. Hawkins. Quality Testing Requires Quality Thinking. Proc. Int. Test Conference, 1993,pp.596. [4] W.Maly, J.P.Shen, J.Ferguson. System. Characterization of Physical Defects for Fault Analysis of MOS IC Cells. Proc. 1984 ITC, pp. 390-399,Philadelphia, 1984. [5] J.P.Shen, W.Maly, J.Ferguson. Inductive Fault Analysis of MOS ICS. IEEE DesignLkTest,pp.13-26, 1985. [6] P.Nigh,W.Maly. Layout - Driven Test Generation. Proc.1989 ICCAD, pp. 154-157,1989. [7] M.Jacomet, WGuggenbuhl. Layout-Dependent Fault Analysis and Test Synthesis for CMOS Circuits. IEEE Trans. on CAD, vol. 12, pp. 888-899, 1993. [8] M.Blyzniuk, FT.Cibakova, EGramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar. Hierarchical DefectOriented Fault Simulation for Digital Circuits. European Test Workshop, Cascais, Portugal, Mai 23-26,2000, pp.151-156. [9] W.Maly. Modeling of Litography-Related Yield Losses for CAD in VLSI. IEEE Trans. on CAD, vo1.4, pp.166-177, 1985. [lo] M.Blyzniuk, W.Pleskacz, M.Lobur, W.Kuzmicz. Estim. of Probability of Functional Faults Caused by Spot Defects in VLSI. Proc. TCSET 2000 Conf., Slavsko, Ukraine, 2000.
The new result in this paper is also to show that the quality of tests in terms of defect coverage is higher when the defect probabilities are not taken into account (see Tables 3, 5 and 6). From this result, we can conclude that the traditional methods of test coverage measuring based on simply counting of not detected defects, where all the faults are assumed to have the same probability, are tending to be overestimated.
8. Conclusions A new hierarchical defect modeling method has been developed and implemented as a tool. In this method, we use a new functional fault model developed for representing defects on the higher level, and the fault-todefect mapping in the form of defect coverage table. In
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