Design and Implementation of SAR ADC - Semantic Scholar
JOURNAL OF COMPUTERS, VOL. 6, NO. 12, DECEMBER 2011
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Design and Implementation of SAR ADC Weibin Wu College of Engineering, South China Agricultural University Guangzhou, China [email protected] Tiansheng Hong†, Joseph Mwape Chileshe, Jieyu LU, Benquan MO, Chaohong LAI College of Engineering, South China Agricultural University Guangzhou, China [email protected]
Abstract—The successive approximation register analog to digital converter (SAR ADC) technique is not yet mature in China mainly because of the imperfect analog module of the SAR ADC. The purpose of this design was to optimize the analog module by designing and making a 8-bit 1MHz SAR ADC and testing a 12-bit SAR ADC theoretically and by simulation. The design of the 1MHz SAR DAC, which consists of analog circuit and digital circuit, was designed according to the positive design method and the specific standard. And the ADC circuit was designed according to the sub-module layout. By the time the project design was finished, its hardware which was made of discrete components by welding printed circuit board (PCB) was debugged. The hardware’s physical properties were analyzed by using a SAR DAC test platform created in LabVIEW8.6 interfaced with data acquisition cards. This designed SAR ADC can be applied to sensor interface, data acquisition system, portable test instrument, low power control system and some aspects of communication. Its absolute average error is about 1% in the laboratory tests which meet the expectations of high accuracy requirement. When it was used in the ropeway project of agriculture engineering project, it reached a good accuracy of 91.5%. It is recommended that PCB automatic routing function be used to reduce the error and interference in the further study from the tests result. Index Terms—ADC, successive approximation register, Multisim, LabVIEW
I. INTRODUCTION This paper is aimed at describing the design of a discrete-component, successive approximation register analog to digital converter (SAR ADC). Its resolution is 12-bit, 5V single-phase power supply. Its maximum power consumption is 93.456mW with 0~5V analog input ranges, which can be broadened from 0V to 10V. Its conversion time is 13.01us, and the output level conformed to the level of transistor transistor logic (TTL). This ADC can be used in the interface of sensors, data acquisition system, portable test instruments, low power control system and communication [1]. †
Corresponding author: Tiansheng Hong, South China Agricultural University, Guangzhou (E-mail: [email protected])
© 2011 ACADEMY PUBLISHER doi:10.4304/jcp.6.12.2631-2638
SAR ADC has many advantages, such as low power consumption, high resolution, high accuracy, no delays associated with the output data and it is compact. The main limitation of the successive approximation structure is the low sampling rate and its demand for the same accuracy between the whole system and each constituent unit, such as DAC and the comparator. Because of these characteristics, they are applied to the moderate or high resolution ADC whose resolution requirement is between 8-bit to 16-bit and its sampling rate is below 5Msps [2]. Consequently, SAR ADCs are widely used in portable battery-powered meters, pen quantizers, industrial control and data and signal acquisition devices. ADC converter has been developed to a very high level in the world. For instance, its highest resolution factor may reach 16 bit, and the power consumption is very low. However, due to the analog modules, such as the comparator and the voltage reference module, it has not been optimized. In addition the development of ADC in China is still in its infancy. The purpose of this design is to find out an optimization design of the ADC analog module and perfect it in the future [3]. II. DESIGN OF THE SAR ADC A. Structure Schematic The 12-bit SAR ADC consisted of control logic circuit, timing generator, shift register, DAC and voltage comparator. The filtered analog input goes through the sample and hold circuit in the sample hold device module. The numerical approximation was obtained after being quantized and coded. The SAR process includes several comparisons made between analog input signal and the reference voltage, and until the converted value numerically approaches the corresponding analog inputs. B. The whole ADC Circuit The ADC layout design is shown in Fig 1. The whole layout design consists of 8 modules, the clock circuit, ADC module, DAC module, sample holder module, reference voltage selector, input filtering device, comparison circuitry and the latch module. The clock circuit provides 1 MHz clock signal and 76.923 kHz
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initiating signal for the whole circuit, and controls signal for the shift register, SAR and the sample holder module. The ADC module generates shift signal to control the D-flip-flop’s working sequence, and temporarily stores and updates the 12-bit converted digital output. Two
DAC modules generate the approximated wave and the latch output wave, which was made a comparison with the analog input wave. Signals of the analog input module could be sine wave input, DC input, or a hybrid waveform of sine wave input DC input.
Display1
Ⅰ
Ⅱ
Display2 Ⅲ
Ⅴ hi
Ⅷ Ⅸ Ⅹ
Ⅵ
Ⅶ
Ⅰ.Latch and display circuit Ⅱ.Shift register display circuit Ⅲ.Waveform display circuits Ⅳ.DAC1 Ⅵ.Reference voltage selection module Ⅶ.Sample hold device Ⅷ.Comparator Ⅸ.Fliter Ⅹ.ADC
Ⅴ.DAC2
Figure 1. Diagram of 12-bit ADC integrated circuit
The sin-wave frequency could range from tens to tens of thousands hertz. Filtering device filters ambient noise. However it must be noted that the filtering circuit may introduce two-period delay, which could affect the output waveform; but it is negligible. The 8 channels sample hold device Module provides 8 channels analog input. Besides the sample and hold function, it has voltage drift function but only the voltage is positive. The reference voltage selector provides 5V and 10V optional reference voltage that can increases the accuracy. The latch module records the 12-bit converted numerical output in real time, and provides data for the DAC2 to convert, so as to acquire a wave approximation. The comparison circuitry makes a comparison between the analog input signal after being sampled and held and the converted signal after being converted by ADC and DAC. The result returns to the ADC module and renews the converted output. To ensure accuracy, the LF400 is chosen as the comparator device. C. The DAC Module The DAC module is an important part. Speed of the whole ADC depends on the converting speed and © 2011 ACADEMY PUBLISHER
accuracy of DAC module. There are several types of DAC such as weighted resistance DAC, R-2R ladder resistor DAC which is only using R and 2R resistances, and R-2R inverse-ladder resistance DAC. The last type was chosen in this paper, as shown in Fig 2. Summing (MSB) Junction
(LCB)
d0
RF
d3
d2
d1
A S0 2R
I 16
S1
I 2R 8 R
2R R
I 4
S2
S3
I 2R 2
2R
R
0
I VREF
2R
I 2R 8
I 4
2R
I 2R 2
R
Figure 2. Function diagram of R-2R Inverse-Ladder Resistance DAC
Using R-2R inverse-ladder resistance DAC can simplify the design which can handle different conditions such as reference power supply with high voltage and different switching speed of analog switch. The two through connection points of the analog switch were grounding point and input current summing junction and the electric potential of the summing junction was
JOURNAL OF COMPUTERS, VOL. 6, NO. 12, DECEMBER 2011
approximate with grounding point, so only between two approximate electric potentials could the switch shift. Though the arithmetic amplifier’s input current changes along with the input data, for the whole resistance group, current is provided by the reference power resource which is stable, so is that of each branch. That means currents of branches ere synchronize and increased the converting speed [4]. III. ANALYTICAL SIMULATION AND ELEMENTAL IMPLEMENTATION OF SAR ADC A. DC Simulation Waveform Multisim 10.0 from National Instruments Company (NI) was chosen as the simulation software. Setting the DAC reference voltage 5V and input DC voltage 1V, the simulation waveform showed that, at the 13.02μs, the digital converted value D11~D0 was 001101000000. This value corresponds to analog voltage 1.015625V. Compared to the actual input DC voltage 1V, the comparative error was just 1.56%. The converted output of the latch made the approximate waveform. The value displays as 1.040V and the approximate one was 1.040V. Error value was zero. 12-bit numerical value displays as 110010111111, and its negation was 001101000000. Successive approximate ADC’s converting time related to its clock-pulse frequency and its bit. The smaller the bit and the higher the frequency, the shorter the converting time [5].
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waveform envelope was similar to the sine, and resembles the sine-wave of the input analog signal. There was only 13.01μs delay between them. The output data of the Latch, converted by DAC, approximated the shape of ladder, which reflects the approximation process and time consumption. C. Power Analysis The formula P=U×I was used to calculate the simulation power. Joining all the grounding points of this simulation circuit together and testing them using the multimeter, the maximum stable current value was 18.9 mA. According to the formula, the result of the power is 93.465 W. This ADC circuit used two DAC modules and a few external circuits. The power consumption of the ADC module itself was even lower [6-7]. D. Physical Circuit on PCB When the design was completed, this ADC was implemented physically with elements on PCB, as shown in Fig 3. IV. ADC FUNCTION TESTING PLATFORM AND DATA ANALYSIS A. ADC Testing Platform Based on the NI data acquisition cards such as PCI6259, USB6221, PCI6022, and so on, a platform for ADC function testing was built. The platform is as shown in Fig.4.
B. Sine Simulation Waveform The simulation result showed that, the latch’s output waveform was a step-shape, each step being 13.01μs. Its
Voltage refference of +5V or +10V
Power source
Interfaces of LF400 OUT, DC IN, AI, GND
Output part
Input part Switch selections of 5V, 2.5V, Diret current
Figure3. Physical circuit diagram of the 8-bit SAR DAC circuit
© 2011 ACADEMY PUBLISHER
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JOURNAL OF COMPUTERS, VOL. 6, NO. 12, DECEMBER 2011
Power source
Screen
Physical Circuit on PCB
converted signal, analog input voltage, approximated voltage and comparative error were displayed. All of these data could be chosen in real time to record, for further analysis. V. TEST RESULT ANALYSIS
Waveform generator
Part of NI data acquisition
Figure 4. Hardware test platform of ADC
The clock signal was generated and collected by PCI6022 and displayed on template. The data acquisition card separately collected analog input, including direct and indirect current signal, clock signal, initiating signal, sampled and held waveform and the latch output waveform after DAC converted. Then the 8bit digital latch output, power spectrum, power spectrum density,
The test result analysis of the circuit with DC voltage input signal was shown as in Table Ⅰ. The test result analysis of the circuit with different frequency, such as 500Hz, 1000Hz and 2000Hz, sinusoidal input was shown as in Table Ⅱ. From Table.1, the maximum comparative error is 0.697464% and the absolute average error is about 0.198339%. From Table Ⅱ, the maximum comparative error is 4.4412% and the absolute average error is about 1.0684%. Different input signals have different maximum comparative error, but the absolute average error is about 1%. The expectation was that the maximum comparative should not be more than 5% and the absolute average error should be around 1%. So the test results were within the expected range.
TABLE Ⅰ TEST RESULT ANALYSIS WITH DC ANALOG INPUT Latch voltage(V)
DC analog input voltage(V)
Comparative error
5.001313
5.000001
0.026263%
5.003746
5.000000
0.074922%
4.99003
4.980392
0.193515%
4.992394
5.000000
0.152120%
4.690146
4.686275
0.082617%
4.696889
4.705882
0.191106%
4.695424
4.686275
0.195246%
3.497503
3.490196
0.209350%
3.504077
3.509804
0.163165%
2.000679
2.000000
0.033959%
1.997902
2.000001
0.104914%
0.990021
1.980392
0.486218%
0.493615
0.490196
0.697464%
0.508958
0.509804
0.165888%
TABLE Ⅱ TEST RESULT ANALYSIS OF SINUSOIDAL INPUT Actual sine wave voltage(V)
Tested voltage(V)
Comparative error
0.488317
0.510004
4.4412%
0.744709
0.745800
0.1465%
1.001091
1.010004
0.8903%
1.441187
1.400850
-2.7989%
1.637066
1.633304
-0.2298%
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1.925201
2.000125
3.8918%
2.021271
2.051021
1.4718%
2.499701
2.586293
3.4641%
2.667217
2.666667
-0.0206%
2.733009
2.725491
-0.2751%
2.926899
2.921569
-0.1821%
3.028088
3.019608
-0.2800%
3.356137
3.352941
-0.0952%
3.383683
3.392157
0.2504%
4.098719
4.098039
-0.0166%
4.141406
4.137255
-0.1002%
4.380690
4.372549
-0.1858%
5.023431
4.998774
-0.4908%
VI. ADC APPLICATION IN INDUSTRY AND AGRICULTURE PROJECT A. ADC and Axle Fatigue Test The digital signal was converted into analog value and provided the input signal for the hydraulic cylinder in axle fatigue test. This input signal drove the hydrovalve’ movement, and imitated a test that was about the fatigue damage of axle movement. On the other hand, the collected analog value was converted into digital quantity to so as to process the signal and analyze the data based on LabVIEW interface [8]. The interface is shown in Fig5.
approximation lasted long. The collected data is as shown in Table Ⅲ. After this, the data was analyzed t to determine its operating force and deviation. Data in Table Ⅲ showed that, the maximum comparative error is 3.3461%, and the absolute average error is about 1.0294%. In this test, the SAR ADC also met the expectation either the maximum comparative error or the absolute average error. In addition, the sampled and held voltage values and the approximated ones were able to meet the 8bit converting requirement. Accurate positioning of the hydraulic valve is another essential step in axle test. However, this DPZO-L-270-L5 40 type ATOS hydraulic valve does not have such functions. So a slow ADC approximate procedure helps achieving the accurate positioning function. During the test, corresponding to the assumed location offset 186mm, the converted voltage is 4.23V, the actual approximated voltage value is 4.120V and the comparative error is 0.945%. The accurate positioning requirement is met. Around all these axle tests, the designed SAR ADC met the expectations at all. The low absolute average error is the one of the major characters for designing this SAR ADC, and the absolute average error from the tests was about 1% which met the expectation. In other words, it has reached the required accuracy. B. Application in Agriculture Engineering Projects.
Figure 5. Experimental Platform for Axle Detection
When carrying out the hydrostatic test, experiment completing, one important step was preloading, aiming at eliminating external interference. Only after three repetitions of the preloading could the sine wave be loaded. In the course of the experiment, the preload signals were channeled through PCI-6259 data acquisition card and generated a simulation by Multisim10.0. Since the preload procedure frequency was low that was usually from 2Hz to 3Hz, the process of the © 2011 ACADEMY PUBLISHER
The transportation of citrus orchards and agricultural fertilizers in South China rely on human labor. But this kind of transport is inefficient especially in the period of citrus harvest. Due to its strong transportation capacity and good terrain adaptability, the ropeway has a very good application prospect in the southern citrus orchards [9], which is a project, the technological study and demonstration of circular chain ropeway in mountainous citrus orchards, belonging the Special Fund for Agroscientific Research in the Public Interest of the Chinese
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Ministry of Agriculture. In this project the strength of steel wire is important in the safe use steel rope in the ropeways being developed for the citrus orchards in south China. The SAR ADC was applied to this ropeway project, especially in the sensor of a non-destructive testing device of steel wire which can help in predicting failure in steel wire [10]. Using the designed SAR ADC, 91.5% of the likely points of failure could be determined. It reach a good accuracy and even higher than expected about the project.
It has been also applied to another project in detection of leaf area index (LAI) based on spectrum, which is a project belonging to National Natural Science Foundation of China. It was used in a data acquisition platform and some parts of the Analysis System for Citrus LAI Spectrum Data. The fitting equation of LAI and spectral information obtained is Y=1.5106X+0.7869 and the calculation error is 0.0378%. Its accuracy is high enough to reach the requirement of the project.
TABLE Ⅲ DATA ANALYSIS IN PRELOADING PROCEDURE Reference voltage(V）
Tested Approximated voltage(V)
Comparative error
4.989
4.912
1.5434%
4.832
4.775
1.1796%
4.624
4.601
0.4974%
4.591
4.581
0.2178%
4.465
4.444
0.4703%
4.371
4.289
1.8760%
4.179
4.133
1.1007%
4.093
4.090
0.0732%
4.120
4.112
0.1941%
4.121
4.112
0.2184%
4.009
3.956
1.3220%
3.896
3.820
1.9507%
3.862
3.820
1.0875%
3.828
3.806
0.5747%
3.678
3.644
0.9244%
3.500
3.499
0.0285%
3.435
3.352
2.4163%
3.414
3.352
1.8161%
3.314
3.313
0.0302%
3.203
3.196
0.2185%
3.043
3.020
0.7558%
2.825
2.902
-2.7257%
2.765
2.746
0.6871%
2.571
2.570
0.0390%
2.137
2.103
1.5910%
2.064
2.051
0.6298%
1.964
1.941
1.1711%
1.752
1.749
0.1712%
1.490
1.479
0.7382%
1.302
1.287
1.1521%
1.281
1.277
0.3122%
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1.046
1.011
3.3461%
1.011
0.997
1.3848%
0.504
0.503
0.1988%
0.359
0.347
3.3426%
[4]
VII. CONCLUSIONS This paper described the 8-bit SAR ADC’s designing process and the tests of the 12-bit SAR ADC in detail. As the simulation waveform and the physical circuit testing result showed, conclusion could be carried out. Firstly, this SAR ADC achieved analog-digital converting. Secondly, its resolution could reach 8-bit and 12-bit ADC requirement. Thirdly, when powered by 5V single-phase resource, its maximum power consumption was 93.451mW and the average current was 1.37mA. Its absolute average error is near 1% in the tests in laboratory which could meet the expectation at all and reach the accuracy requirement. When it was used in the ropeway project of agriculture engineering project, it reached a good accuracy of 91.5%. And its accuracy is high enough to reach the requirement of the project in detection of LAI based on spectrum. However, some improvement could be made. It is better to use bandgap-reference as the reference voltage VREF in the circuit structure.In order to have a better connection with ELVIS, manual welding on breadboard was adopted. It is also recommended in the further study, that the PCB auto routing function be improved for reducing the unnecessary error and interference. ACKNOWLEDGMENT This work was supported by the National Natural Science Foundation of China with the Serial Number of 30871450.And it was also supported by the project with the number of 200903023-01, the technological study and demonstration of circular chain ropeway in mountainous citrus orchards, which belongs to the Special Fund for Agro-scientific Research in the Public Interest of the Chinese Ministry of Agriculture with the serial number of 200903023. REFERENCES [1]
[2] [3]
J. Zhang, “Design a 10-bit SAR A/D Converter Based on CMOS Technology,” University of Electronic Science and Technology of Xi’an, 2008. L. Zhang, “The Design of 10 Bit SAR ADC, Shenyang University of Technology,” 2006 . X.L. Yang, “Research and Design of 10-bit SAR ADC Based on CMOS Technology,” HeFei University of Technology, 2007.
© 2011 ACADEMY PUBLISHER
C.Y. Chang, N. Zhao, Z.J. Liu, “A Study and Simulation of D/A Converter Based on Electronics Workbench EWB,” Modern Electronic Technique 2004, (9): 87-88. [5] W.T. Zhou, “A 10bit 580ksps Successive Approximation Register ADC in 0.18um CMOS,” Shanghai Jiao Tong University, 2007. [6] E.J. Sun, “Fundamental research of DAC and design of 8bit DAC,” University of Electronic Science and Technology of China, 2003. [7] T.P. Huang, “Design of a high accuracy and low power consumption 8-bit DAC,” University of Electronic Science and Technology of China, 2005. [8] Z.S. Lei, L. Wei, and C.G. Zhao,et al, High-level programming with LabVIEW and application of virtual instruments in Engineering, China Railway Publishing House, 2009. [9] Z.Q. Lun, “Design of Ropeway and Steel Wire Detection Device”, South China Agricultural University, 2009 . [10] R. Quan, S.H. Quan, L. Huang, C.J. Xie, “Fault Diagnosis and Fault-Tolerant Control for Multi-Sensor of Fuel Cell System,” Journal of Computational Information Systems. 2010, 6 (11) : 3703- 3711.
Weibin Wu, Male, born in 1978, Guangzhou, is an associate professor in College of Engineering, South China Agricultural University. He obtained bachelor degree of machine design & manufacturing and automation, South China Agricultural University, July 2001; Master's degrees of mechanization engineering, South China Agricultural University, June 2004; and Ph.D in mechanization engineering, South China Agricultural University, June 2007. Afterwards, he became a Post Doctor researcher in College of Mechanical and Automotive Engineering of South China University of Technology, majoring in mechanization and focusing on electronics, information and computer applications. He is now engaged in the teaching and research of soil-plantmachine systems, electronic information and computer technology applications in agriculture, precision agriculture, and vehicle engineering, in South China Agricultural University. He has published more than 30 papers, of which 12 were compiled into EI and 3 were compiled into ISTP. He has gained 2 utility model patents, 1 invention patent and 2 computer software copyright registration numbers. Prof. Wu is now an IEEE member. He received the title of outstanding graduates of Guangdong Province in China for twice, in 2004 and 2007. In 2006, he won Bronze Award of National Challenge Cup business competition. He also
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participated in the tenth essay contest of virtual instrumentation applications held by NI Company in China in 2009 and won the web popularity award.
Tiansheng Hong, Male, born in 1955, obtained his bachelor's degree in 1982 at South China Agricultural University. In 1987 and 1990, Professor Hong received his Master's and Ph.D degree in France. Afterwards, he has studied and worked in France and Canada as a senior visiting scholar. At present, Professor Hong holds concurrent positions as the Dean of College of Engineering in South China Agricultural University, Director and Chief Scientist of National Citrus Industry Technology Research System Machinery Laboratory. For his spare time, Professor Hong serves as member of the Science and Technology Committee in the Ministry of Agriculture of China, member of the Chinese Society of Agricultural Engineering, senior member for life in the Chinese
© 2011 ACADEMY PUBLISHER
JOURNAL OF COMPUTERS, VOL. 6, NO. 12, DECEMBER 2011
Society for Agricultural Machinery, member of the editorial board of IJABE, editorial member of the Transactions of the Chinese Society for Agricultural Machinery etc. He has engaged in teaching and research for the agricultural engineering as well as for the mechatronics technique applications.
Joseph Mwape Chileshe, Male, born in 1968, Lusaka, is member of staff, in School of Engineering, University of Zambia. He obtained a bachelors of engineering degree in Mechanical Engineering, University of Zambia, July 1991; Master's degree of Agricultural Engineering, South China Agricultural University, June 1996. He then joined the department of Agricultural Engineering, University of Zambia as a lecturer in mechanization and machinery Design. Currently he is pursuing postgraduate studies at the college of Engineering, South China Agricultural University.
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Design and Implementation of SAR ADC Weibin Wu College of Engineering, South China Agricultural University Guangzhou, China [email protected] Tiansheng Hong†, Joseph Mwape Chileshe, Jieyu LU, Benquan MO, Chaohong LAI College of Engineering, South China Agricultural University Guangzhou, China [email protected]
Abstract—The successive approximation register analog to digital converter (SAR ADC) technique is not yet mature in China mainly because of the imperfect analog module of the SAR ADC. The purpose of this design was to optimize the analog module by designing and making a 8-bit 1MHz SAR ADC and testing a 12-bit SAR ADC theoretically and by simulation. The design of the 1MHz SAR DAC, which consists of analog circuit and digital circuit, was designed according to the positive design method and the specific standard. And the ADC circuit was designed according to the sub-module layout. By the time the project design was finished, its hardware which was made of discrete components by welding printed circuit board (PCB) was debugged. The hardware’s physical properties were analyzed by using a SAR DAC test platform created in LabVIEW8.6 interfaced with data acquisition cards. This designed SAR ADC can be applied to sensor interface, data acquisition system, portable test instrument, low power control system and some aspects of communication. Its absolute average error is about 1% in the laboratory tests which meet the expectations of high accuracy requirement. When it was used in the ropeway project of agriculture engineering project, it reached a good accuracy of 91.5%. It is recommended that PCB automatic routing function be used to reduce the error and interference in the further study from the tests result. Index Terms—ADC, successive approximation register, Multisim, LabVIEW
I. INTRODUCTION This paper is aimed at describing the design of a discrete-component, successive approximation register analog to digital converter (SAR ADC). Its resolution is 12-bit, 5V single-phase power supply. Its maximum power consumption is 93.456mW with 0~5V analog input ranges, which can be broadened from 0V to 10V. Its conversion time is 13.01us, and the output level conformed to the level of transistor transistor logic (TTL). This ADC can be used in the interface of sensors, data acquisition system, portable test instruments, low power control system and communication [1]. †
Corresponding author: Tiansheng Hong, South China Agricultural University, Guangzhou (E-mail: [email protected])
© 2011 ACADEMY PUBLISHER doi:10.4304/jcp.6.12.2631-2638
SAR ADC has many advantages, such as low power consumption, high resolution, high accuracy, no delays associated with the output data and it is compact. The main limitation of the successive approximation structure is the low sampling rate and its demand for the same accuracy between the whole system and each constituent unit, such as DAC and the comparator. Because of these characteristics, they are applied to the moderate or high resolution ADC whose resolution requirement is between 8-bit to 16-bit and its sampling rate is below 5Msps [2]. Consequently, SAR ADCs are widely used in portable battery-powered meters, pen quantizers, industrial control and data and signal acquisition devices. ADC converter has been developed to a very high level in the world. For instance, its highest resolution factor may reach 16 bit, and the power consumption is very low. However, due to the analog modules, such as the comparator and the voltage reference module, it has not been optimized. In addition the development of ADC in China is still in its infancy. The purpose of this design is to find out an optimization design of the ADC analog module and perfect it in the future [3]. II. DESIGN OF THE SAR ADC A. Structure Schematic The 12-bit SAR ADC consisted of control logic circuit, timing generator, shift register, DAC and voltage comparator. The filtered analog input goes through the sample and hold circuit in the sample hold device module. The numerical approximation was obtained after being quantized and coded. The SAR process includes several comparisons made between analog input signal and the reference voltage, and until the converted value numerically approaches the corresponding analog inputs. B. The whole ADC Circuit The ADC layout design is shown in Fig 1. The whole layout design consists of 8 modules, the clock circuit, ADC module, DAC module, sample holder module, reference voltage selector, input filtering device, comparison circuitry and the latch module. The clock circuit provides 1 MHz clock signal and 76.923 kHz
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initiating signal for the whole circuit, and controls signal for the shift register, SAR and the sample holder module. The ADC module generates shift signal to control the D-flip-flop’s working sequence, and temporarily stores and updates the 12-bit converted digital output. Two
DAC modules generate the approximated wave and the latch output wave, which was made a comparison with the analog input wave. Signals of the analog input module could be sine wave input, DC input, or a hybrid waveform of sine wave input DC input.
Display1
Ⅰ
Ⅱ
Display2 Ⅲ
Ⅴ hi
Ⅷ Ⅸ Ⅹ
Ⅵ
Ⅶ
Ⅰ.Latch and display circuit Ⅱ.Shift register display circuit Ⅲ.Waveform display circuits Ⅳ.DAC1 Ⅵ.Reference voltage selection module Ⅶ.Sample hold device Ⅷ.Comparator Ⅸ.Fliter Ⅹ.ADC
Ⅴ.DAC2
Figure 1. Diagram of 12-bit ADC integrated circuit
The sin-wave frequency could range from tens to tens of thousands hertz. Filtering device filters ambient noise. However it must be noted that the filtering circuit may introduce two-period delay, which could affect the output waveform; but it is negligible. The 8 channels sample hold device Module provides 8 channels analog input. Besides the sample and hold function, it has voltage drift function but only the voltage is positive. The reference voltage selector provides 5V and 10V optional reference voltage that can increases the accuracy. The latch module records the 12-bit converted numerical output in real time, and provides data for the DAC2 to convert, so as to acquire a wave approximation. The comparison circuitry makes a comparison between the analog input signal after being sampled and held and the converted signal after being converted by ADC and DAC. The result returns to the ADC module and renews the converted output. To ensure accuracy, the LF400 is chosen as the comparator device. C. The DAC Module The DAC module is an important part. Speed of the whole ADC depends on the converting speed and © 2011 ACADEMY PUBLISHER
accuracy of DAC module. There are several types of DAC such as weighted resistance DAC, R-2R ladder resistor DAC which is only using R and 2R resistances, and R-2R inverse-ladder resistance DAC. The last type was chosen in this paper, as shown in Fig 2. Summing (MSB) Junction
(LCB)
d0
RF
d3
d2
d1
A S0 2R
I 16
S1
I 2R 8 R
2R R
I 4
S2
S3
I 2R 2
2R
R
0
I VREF
2R
I 2R 8
I 4
2R
I 2R 2
R
Figure 2. Function diagram of R-2R Inverse-Ladder Resistance DAC
Using R-2R inverse-ladder resistance DAC can simplify the design which can handle different conditions such as reference power supply with high voltage and different switching speed of analog switch. The two through connection points of the analog switch were grounding point and input current summing junction and the electric potential of the summing junction was
JOURNAL OF COMPUTERS, VOL. 6, NO. 12, DECEMBER 2011
approximate with grounding point, so only between two approximate electric potentials could the switch shift. Though the arithmetic amplifier’s input current changes along with the input data, for the whole resistance group, current is provided by the reference power resource which is stable, so is that of each branch. That means currents of branches ere synchronize and increased the converting speed [4]. III. ANALYTICAL SIMULATION AND ELEMENTAL IMPLEMENTATION OF SAR ADC A. DC Simulation Waveform Multisim 10.0 from National Instruments Company (NI) was chosen as the simulation software. Setting the DAC reference voltage 5V and input DC voltage 1V, the simulation waveform showed that, at the 13.02μs, the digital converted value D11~D0 was 001101000000. This value corresponds to analog voltage 1.015625V. Compared to the actual input DC voltage 1V, the comparative error was just 1.56%. The converted output of the latch made the approximate waveform. The value displays as 1.040V and the approximate one was 1.040V. Error value was zero. 12-bit numerical value displays as 110010111111, and its negation was 001101000000. Successive approximate ADC’s converting time related to its clock-pulse frequency and its bit. The smaller the bit and the higher the frequency, the shorter the converting time [5].
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waveform envelope was similar to the sine, and resembles the sine-wave of the input analog signal. There was only 13.01μs delay between them. The output data of the Latch, converted by DAC, approximated the shape of ladder, which reflects the approximation process and time consumption. C. Power Analysis The formula P=U×I was used to calculate the simulation power. Joining all the grounding points of this simulation circuit together and testing them using the multimeter, the maximum stable current value was 18.9 mA. According to the formula, the result of the power is 93.465 W. This ADC circuit used two DAC modules and a few external circuits. The power consumption of the ADC module itself was even lower [6-7]. D. Physical Circuit on PCB When the design was completed, this ADC was implemented physically with elements on PCB, as shown in Fig 3. IV. ADC FUNCTION TESTING PLATFORM AND DATA ANALYSIS A. ADC Testing Platform Based on the NI data acquisition cards such as PCI6259, USB6221, PCI6022, and so on, a platform for ADC function testing was built. The platform is as shown in Fig.4.
B. Sine Simulation Waveform The simulation result showed that, the latch’s output waveform was a step-shape, each step being 13.01μs. Its
Voltage refference of +5V or +10V
Power source
Interfaces of LF400 OUT, DC IN, AI, GND
Output part
Input part Switch selections of 5V, 2.5V, Diret current
Figure3. Physical circuit diagram of the 8-bit SAR DAC circuit
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Power source
Screen
Physical Circuit on PCB
converted signal, analog input voltage, approximated voltage and comparative error were displayed. All of these data could be chosen in real time to record, for further analysis. V. TEST RESULT ANALYSIS
Waveform generator
Part of NI data acquisition
Figure 4. Hardware test platform of ADC
The clock signal was generated and collected by PCI6022 and displayed on template. The data acquisition card separately collected analog input, including direct and indirect current signal, clock signal, initiating signal, sampled and held waveform and the latch output waveform after DAC converted. Then the 8bit digital latch output, power spectrum, power spectrum density,
The test result analysis of the circuit with DC voltage input signal was shown as in Table Ⅰ. The test result analysis of the circuit with different frequency, such as 500Hz, 1000Hz and 2000Hz, sinusoidal input was shown as in Table Ⅱ. From Table.1, the maximum comparative error is 0.697464% and the absolute average error is about 0.198339%. From Table Ⅱ, the maximum comparative error is 4.4412% and the absolute average error is about 1.0684%. Different input signals have different maximum comparative error, but the absolute average error is about 1%. The expectation was that the maximum comparative should not be more than 5% and the absolute average error should be around 1%. So the test results were within the expected range.
TABLE Ⅰ TEST RESULT ANALYSIS WITH DC ANALOG INPUT Latch voltage(V)
DC analog input voltage(V)
Comparative error
5.001313
5.000001
0.026263%
5.003746
5.000000
0.074922%
4.99003
4.980392
0.193515%
4.992394
5.000000
0.152120%
4.690146
4.686275
0.082617%
4.696889
4.705882
0.191106%
4.695424
4.686275
0.195246%
3.497503
3.490196
0.209350%
3.504077
3.509804
0.163165%
2.000679
2.000000
0.033959%
1.997902
2.000001
0.104914%
0.990021
1.980392
0.486218%
0.493615
0.490196
0.697464%
0.508958
0.509804
0.165888%
TABLE Ⅱ TEST RESULT ANALYSIS OF SINUSOIDAL INPUT Actual sine wave voltage(V)
Tested voltage(V)
Comparative error
0.488317
0.510004
4.4412%
0.744709
0.745800
0.1465%
1.001091
1.010004
0.8903%
1.441187
1.400850
-2.7989%
1.637066
1.633304
-0.2298%
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1.925201
2.000125
3.8918%
2.021271
2.051021
1.4718%
2.499701
2.586293
3.4641%
2.667217
2.666667
-0.0206%
2.733009
2.725491
-0.2751%
2.926899
2.921569
-0.1821%
3.028088
3.019608
-0.2800%
3.356137
3.352941
-0.0952%
3.383683
3.392157
0.2504%
4.098719
4.098039
-0.0166%
4.141406
4.137255
-0.1002%
4.380690
4.372549
-0.1858%
5.023431
4.998774
-0.4908%
VI. ADC APPLICATION IN INDUSTRY AND AGRICULTURE PROJECT A. ADC and Axle Fatigue Test The digital signal was converted into analog value and provided the input signal for the hydraulic cylinder in axle fatigue test. This input signal drove the hydrovalve’ movement, and imitated a test that was about the fatigue damage of axle movement. On the other hand, the collected analog value was converted into digital quantity to so as to process the signal and analyze the data based on LabVIEW interface [8]. The interface is shown in Fig5.
approximation lasted long. The collected data is as shown in Table Ⅲ. After this, the data was analyzed t to determine its operating force and deviation. Data in Table Ⅲ showed that, the maximum comparative error is 3.3461%, and the absolute average error is about 1.0294%. In this test, the SAR ADC also met the expectation either the maximum comparative error or the absolute average error. In addition, the sampled and held voltage values and the approximated ones were able to meet the 8bit converting requirement. Accurate positioning of the hydraulic valve is another essential step in axle test. However, this DPZO-L-270-L5 40 type ATOS hydraulic valve does not have such functions. So a slow ADC approximate procedure helps achieving the accurate positioning function. During the test, corresponding to the assumed location offset 186mm, the converted voltage is 4.23V, the actual approximated voltage value is 4.120V and the comparative error is 0.945%. The accurate positioning requirement is met. Around all these axle tests, the designed SAR ADC met the expectations at all. The low absolute average error is the one of the major characters for designing this SAR ADC, and the absolute average error from the tests was about 1% which met the expectation. In other words, it has reached the required accuracy. B. Application in Agriculture Engineering Projects.
Figure 5. Experimental Platform for Axle Detection
When carrying out the hydrostatic test, experiment completing, one important step was preloading, aiming at eliminating external interference. Only after three repetitions of the preloading could the sine wave be loaded. In the course of the experiment, the preload signals were channeled through PCI-6259 data acquisition card and generated a simulation by Multisim10.0. Since the preload procedure frequency was low that was usually from 2Hz to 3Hz, the process of the © 2011 ACADEMY PUBLISHER
The transportation of citrus orchards and agricultural fertilizers in South China rely on human labor. But this kind of transport is inefficient especially in the period of citrus harvest. Due to its strong transportation capacity and good terrain adaptability, the ropeway has a very good application prospect in the southern citrus orchards [9], which is a project, the technological study and demonstration of circular chain ropeway in mountainous citrus orchards, belonging the Special Fund for Agroscientific Research in the Public Interest of the Chinese
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Ministry of Agriculture. In this project the strength of steel wire is important in the safe use steel rope in the ropeways being developed for the citrus orchards in south China. The SAR ADC was applied to this ropeway project, especially in the sensor of a non-destructive testing device of steel wire which can help in predicting failure in steel wire [10]. Using the designed SAR ADC, 91.5% of the likely points of failure could be determined. It reach a good accuracy and even higher than expected about the project.
It has been also applied to another project in detection of leaf area index (LAI) based on spectrum, which is a project belonging to National Natural Science Foundation of China. It was used in a data acquisition platform and some parts of the Analysis System for Citrus LAI Spectrum Data. The fitting equation of LAI and spectral information obtained is Y=1.5106X+0.7869 and the calculation error is 0.0378%. Its accuracy is high enough to reach the requirement of the project.
TABLE Ⅲ DATA ANALYSIS IN PRELOADING PROCEDURE Reference voltage(V）
Tested Approximated voltage(V)
Comparative error
4.989
4.912
1.5434%
4.832
4.775
1.1796%
4.624
4.601
0.4974%
4.591
4.581
0.2178%
4.465
4.444
0.4703%
4.371
4.289
1.8760%
4.179
4.133
1.1007%
4.093
4.090
0.0732%
4.120
4.112
0.1941%
4.121
4.112
0.2184%
4.009
3.956
1.3220%
3.896
3.820
1.9507%
3.862
3.820
1.0875%
3.828
3.806
0.5747%
3.678
3.644
0.9244%
3.500
3.499
0.0285%
3.435
3.352
2.4163%
3.414
3.352
1.8161%
3.314
3.313
0.0302%
3.203
3.196
0.2185%
3.043
3.020
0.7558%
2.825
2.902
-2.7257%
2.765
2.746
0.6871%
2.571
2.570
0.0390%
2.137
2.103
1.5910%
2.064
2.051
0.6298%
1.964
1.941
1.1711%
1.752
1.749
0.1712%
1.490
1.479
0.7382%
1.302
1.287
1.1521%
1.281
1.277
0.3122%
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1.046
1.011
3.3461%
1.011
0.997
1.3848%
0.504
0.503
0.1988%
0.359
0.347
3.3426%
[4]
VII. CONCLUSIONS This paper described the 8-bit SAR ADC’s designing process and the tests of the 12-bit SAR ADC in detail. As the simulation waveform and the physical circuit testing result showed, conclusion could be carried out. Firstly, this SAR ADC achieved analog-digital converting. Secondly, its resolution could reach 8-bit and 12-bit ADC requirement. Thirdly, when powered by 5V single-phase resource, its maximum power consumption was 93.451mW and the average current was 1.37mA. Its absolute average error is near 1% in the tests in laboratory which could meet the expectation at all and reach the accuracy requirement. When it was used in the ropeway project of agriculture engineering project, it reached a good accuracy of 91.5%. And its accuracy is high enough to reach the requirement of the project in detection of LAI based on spectrum. However, some improvement could be made. It is better to use bandgap-reference as the reference voltage VREF in the circuit structure.In order to have a better connection with ELVIS, manual welding on breadboard was adopted. It is also recommended in the further study, that the PCB auto routing function be improved for reducing the unnecessary error and interference. ACKNOWLEDGMENT This work was supported by the National Natural Science Foundation of China with the Serial Number of 30871450.And it was also supported by the project with the number of 200903023-01, the technological study and demonstration of circular chain ropeway in mountainous citrus orchards, which belongs to the Special Fund for Agro-scientific Research in the Public Interest of the Chinese Ministry of Agriculture with the serial number of 200903023. REFERENCES [1]
[2] [3]
J. Zhang, “Design a 10-bit SAR A/D Converter Based on CMOS Technology,” University of Electronic Science and Technology of Xi’an, 2008. L. Zhang, “The Design of 10 Bit SAR ADC, Shenyang University of Technology,” 2006 . X.L. Yang, “Research and Design of 10-bit SAR ADC Based on CMOS Technology,” HeFei University of Technology, 2007.
© 2011 ACADEMY PUBLISHER
C.Y. Chang, N. Zhao, Z.J. Liu, “A Study and Simulation of D/A Converter Based on Electronics Workbench EWB,” Modern Electronic Technique 2004, (9): 87-88. [5] W.T. Zhou, “A 10bit 580ksps Successive Approximation Register ADC in 0.18um CMOS,” Shanghai Jiao Tong University, 2007. [6] E.J. Sun, “Fundamental research of DAC and design of 8bit DAC,” University of Electronic Science and Technology of China, 2003. [7] T.P. Huang, “Design of a high accuracy and low power consumption 8-bit DAC,” University of Electronic Science and Technology of China, 2005. [8] Z.S. Lei, L. Wei, and C.G. Zhao,et al, High-level programming with LabVIEW and application of virtual instruments in Engineering, China Railway Publishing House, 2009. [9] Z.Q. Lun, “Design of Ropeway and Steel Wire Detection Device”, South China Agricultural University, 2009 . [10] R. Quan, S.H. Quan, L. Huang, C.J. Xie, “Fault Diagnosis and Fault-Tolerant Control for Multi-Sensor of Fuel Cell System,” Journal of Computational Information Systems. 2010, 6 (11) : 3703- 3711.
Weibin Wu, Male, born in 1978, Guangzhou, is an associate professor in College of Engineering, South China Agricultural University. He obtained bachelor degree of machine design & manufacturing and automation, South China Agricultural University, July 2001; Master's degrees of mechanization engineering, South China Agricultural University, June 2004; and Ph.D in mechanization engineering, South China Agricultural University, June 2007. Afterwards, he became a Post Doctor researcher in College of Mechanical and Automotive Engineering of South China University of Technology, majoring in mechanization and focusing on electronics, information and computer applications. He is now engaged in the teaching and research of soil-plantmachine systems, electronic information and computer technology applications in agriculture, precision agriculture, and vehicle engineering, in South China Agricultural University. He has published more than 30 papers, of which 12 were compiled into EI and 3 were compiled into ISTP. He has gained 2 utility model patents, 1 invention patent and 2 computer software copyright registration numbers. Prof. Wu is now an IEEE member. He received the title of outstanding graduates of Guangdong Province in China for twice, in 2004 and 2007. In 2006, he won Bronze Award of National Challenge Cup business competition. He also
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participated in the tenth essay contest of virtual instrumentation applications held by NI Company in China in 2009 and won the web popularity award.
Tiansheng Hong, Male, born in 1955, obtained his bachelor's degree in 1982 at South China Agricultural University. In 1987 and 1990, Professor Hong received his Master's and Ph.D degree in France. Afterwards, he has studied and worked in France and Canada as a senior visiting scholar. At present, Professor Hong holds concurrent positions as the Dean of College of Engineering in South China Agricultural University, Director and Chief Scientist of National Citrus Industry Technology Research System Machinery Laboratory. For his spare time, Professor Hong serves as member of the Science and Technology Committee in the Ministry of Agriculture of China, member of the Chinese Society of Agricultural Engineering, senior member for life in the Chinese
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Society for Agricultural Machinery, member of the editorial board of IJABE, editorial member of the Transactions of the Chinese Society for Agricultural Machinery etc. He has engaged in teaching and research for the agricultural engineering as well as for the mechatronics technique applications.
Joseph Mwape Chileshe, Male, born in 1968, Lusaka, is member of staff, in School of Engineering, University of Zambia. He obtained a bachelors of engineering degree in Mechanical Engineering, University of Zambia, July 1991; Master's degree of Agricultural Engineering, South China Agricultural University, June 1996. He then joined the department of Agricultural Engineering, University of Zambia as a lecturer in mechanization and machinery Design. Currently he is pursuing postgraduate studies at the college of Engineering, South China Agricultural University.
