Design and modeling of a micromachined high-Q ... - IEEE Xplore
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003
Design and Modeling of a Micromachined High-Q Tunable Capacitor With Large Tuning Range and a Vertical Planar Spiral Inductor Jinghong Chen, Member, IEEE, Jun Zou, Chang Liu, Senior Member, IEEE, José E. Schutt-Ainé, Senior Member, IEEE, and Sung-Mo (Steve) Kang, Fellow, IEEE
Abstract—In wireless communication systems, passive elements including tunable capacitors and inductors often need high quality factor ( -factor). In this paper, we present the design and modeling of a novel high -factor tunable capacitor with large tuning range and a high -factor vertical planar spiral inductor implemented in microelectromechanical system (MEMS) technology. Different from conventional two-parallel-plate tunable capacitors, the novel tunable capacitor consists of one suspended top plate and two fixed bottom plates. One of the two fixed plates and the top plate form a variable capacitor, while the other fixed plate and the top plate are used to provide electrostatic actuation for capacitance tuning. For the fabricated prototype tunable capacitors, a maximum controllable tuning range of 69.8% has been achieved, exceeding the theoretical tuning range limit (50%) of conventional two-parallel-plate tunable capacitors. This tunable capacitor also exhibits a very low return loss of less than 0.6 dB in the frequency range from 45 MHz to 10 GHz. The high -factor planar coil inductor is first fabricated on silicon substrate and then assembled to the vertical position by using a novel three-dimensional microstructure assembly technique called plastic deformation magnetic assembly (PDMA). Inductors of different dimensions are fabricated and tested. The -parameters of the inductors before and after PDMA are measured and compared, demonstrating superior performance due to reduced substrate loss and parasitics. The new vertical planar spiral inductor also has the advantage of occupying much smaller silicon areas than the conventional planar spiral inductors. Index Terms—Electrostatic actuation, magnetic actuation, microelectromechanical systems (MEMS), modeling and simulation, monolithic inductor, quality factor, RFIC, self-resonance, varactor, variable capacitor.
I. INTRODUCTION
I
N WIRELESS communication systems, passive elements including tunable capacitors and inductors often need a high quality factor and high self-resonant frequency. High- tunable capacitors and inductors can lead to improved power or figure of merit in low noise amplifiers, low insertion loss in bandpass Manuscript received May 7, 2002; revised October 16, 2002. This work was supported by DARPA Composite CAD program. The review of this paper was arranged by Editor H. Shichijo. J. Chen is with Agere Systems, Holmdel, NJ 07733 USA (e-mail: jchen42@ agere.com). J. Zou, C. Liu, and J. E. Schutt-Ainé are with the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. S.-M. Kang is with the Baskin School of Engineering, University of California, Santa Cruz, CA 95064 USA Digital Object Identifier 10.1109/TED.2003.810479
filters, and better phase noise and power in voltage-controlled oscillators (VCOs). Currently many off-chip discrete passive elements are widely used to meet these requirements. Due to the problems in packaging complexity, large system area, and high cost when utilizing off-chip passive components, there have been many investigations to realize high-performance on-chip passive elements that could be monolithically integrated with active circuitry. A new solution for this has arisen with the recent development of MEMS technology. RF circuits such as VCOs and tunable filters have been developed using on-chip micromachined inductors and tunable capacitors. Young et al. reported a VCO [1] that contains a micromachined three-dimensional (3-D) coil inductor [2] and a two-parallel-plate tunable capacitor with a tuning range of 16% [3]. Both passive elements are micromachined on silicon substrates and thus can be integrated with active circuit components using modified integrated circuit (IC) fabrication processes. Tunable capacitors and inductors constructed using MEMS technology [1]–[6], [9]–[28] often can provide high quality factor through new structure design or operational principles. In addition, a microelectromechanical system (MEMS) tunable capacitor also has the potential of offering a large tuning range compared with semiconductor diode counterparts fabricated via conventional IC technology. Among all the MEMS tunable capacitors developed to date, parallel-plate configuration is the most commonly used. Such micromechanical capacitors often consist of suspended top metal plates that can be electrostatically displaced (via applied voltages) over bottom metal plates to vary the capacitance between the plates. Because these capacitors can be constructed in low-resistivity metal materials, they exhibit much higher -factors than the semiconductor counterparts, which suffer from greater losses due to excessive semiconductor series resistance. A -factor on the order of 60 has been reported for the micromachined tunable capacitor reported in [3]. However, the theoretical tuning range of such capacitors is limited to 50% by the pull-in effect. The actual achieved tuning range is often much smaller than the theoretical value due to parasitic capacitance (e.g., a measured tuning range of 16% was reported in [3]). Various broad-band communication applications require a wide tuning range. Recently, much effort has been made to improve the tuning capability of MEMS tunable capacitors. Dec et al. [4] uses a three-parallel-plate configuration (two suspended plates and one fixed plate on the substrate) to compensate
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CHEN et al.: DESIGN AND MODELING OF A MICROMACHINED HIGH-
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for the pull-in effect and obtain a tuning range of 87%. The fabrication process requires two layers of structural materials and two layers of sacrificial materials. Yao, et al. [5] reported a tunable capacitor with a tuning range of 200%. It is based on lateral comb structures (instead of parallel-plate) etched by deep reactive ion etching (DRIE) on silicon-on-insulator (SOI) substrate. Feng et al. [6] used a thermal actuator in their tunable capacitor and achieved a tuning range of 270%. The disadvantage of thermal actuators is that their response speed is generally slower than that of electrostatic actuators. We report in this paper the development and modeling of a novel electrostatically actuated tunable capacitor. This new design keeps the simplicity of the conventional two-parallel-plate configuration, while providing a much wider tuning range. Only one structural layer and one sacrificial layer are used. The measured tuning range achieved was 69.8%, exceeding the 50% tuning range limit on conventional two-parallel-plate tunable capacitors. The capacitor operates under a wide frequency range (45 MHz to 10 GHz) with a signal loss below 0.6 dB. A component quality factor of 30 at 5 GHz and a self-resonant frequency beyond 10 GHz has been achieved. The new tunable capacitor is fabricated using a standard surface micromachining process and thus can be monolithically integrated with IC circuits. Another important RF MEMS component is a micromachined high- inductor. Although planar spiral inductors can be integrated with other circuits using current standard IC fabrication process, their performance is still unsatisfactory. Oftentimes, planar spiral inductors are directly fabricated onto the dielectric layer on top of the conductive substrate, which lowers the quality factors and degrades the performance by introducing extra loss, noise, and parasitic capacitance [7], [8]. Another disadvantage of a planar spiral inductor lies in the fact that it has a large footprint to achieve the inductance value [9]. In recent years, much effort has been made to improve the performance of planar coil inductors. Metal materials with higher conductivity or thicker metal layers are utilized to decrease the resistance of the coil [10]. Meanwhile, different methods are proposed to reduce the substrate loss and parasitic, including removing the substrate underneath the inductor [11]–[15] or applying a thick polymide layer to separate the inductor farther away from the substrate [16]. A serious problem is the limited separation that can be achieved. Moreover, for techniques involving substrate etching, there are concerns about process compatibility, and the reduced mechanical stability for the substrate. More recently, planar coil inductors levitated above the substrate are realized using a sacrificial metallic mode (SMM) process [17]. Three-dimensional solenoid on-chip inductors developed by using 3-D laser lithography or surface micromachining technology have also been demonstrated [18], [19]. These methods may involve certain materials or fabrication steps, which are not compatible with current standard fabrication process. Moreover, none of the methods mentioned above has solved the large footprint problem of conventional planar spiral inductors. This paper reports a high- vertical planar coil inductors developed by using a novel 3-D self-assembly process called plastic deformation magnetic assembly (PDMA). Experimental results show that the vertical planar coil inductor suffers less substrate and parasitic loss than the
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Fig. 1. A schematic model of a conventional electrostatically actuated twoparallel-plate tunable capacitor.
conventional horizontal counterparts, therefore it can achieve a higher quality factor and self-resonant frequency. Another major advantage of the vertical inductors is that they have almost zero footprints and thus occupy much smaller substrate area than the conventional planar inductors. II. HIGH-
MICROMACHINED TUNABLE CAPACITOR WITH A LARGE TUNING RANGE
In this section, we present the design and modeling of the micromachined high- tunable capacitor with a large tuning range. A. Operating Principle Fig. 1 shows a conventional parallel-plate tunable capacitor which consists of a suspended top plate and a fixed bottom plate, with an overlap area of and initial spacing of . When a dc voltage is applied across the two plates, the spacing between these two plates is reduced. Neglecting the fringe effect, the value of the capacitance ( between these two plates can be determined by (1) is applied, an attractive electrostatic force ( and, when is generated between the two plates with the value of the force given by (2) An effective spring constant defined as
for the electrostatic force can be
(3) The mechanical suspension of the top plate has a spring constant . When the top plate is displaced, the suspension produces . The magnitude of is a restoring force, designated as . At equilibrium, the magnitudes of related to by and are equal, thus (4) The expression of
in terms of
is (5)
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Fig. 2. A schematic model of the novel wide-tuning-range tunable capacitor.
Note that the two force constants are equal in magnitude when . The corresponding value of the value of reaches (at ) is called the pull-in voltage ( . If is and is beyond the critical continuously increased beyond , no equilibrium position can be reached until the point of two plates are snapped into contact (pull-in effect). Thus, the capacitance of the conventional two-parallel-plate tunable capacitor can only be controllably changed to 150% of its original value at most. As a result, theoretically the maximum controllable tuning range is then 50%. The schematic model of our novel wide-tuning-range tunable capacitor is shown in Fig. 2. It consists of three plates that are , , and . The plate is a movable top designated as plate suspended by four cantilever beams. The plate , which is fixed on the bottom substrate, forms a variable capacitor by (the outer fixed bottom coupling with the plate . The plate are used to provide the electrostatic actuation. An plate) and is applied between plates and . At actuation voltage ( V), is designed to be smaller than . When rest ( (top movable plate) is moved by a distance of the plate under a given applied , the relative tuning range is derived as
Fig. 3. A schematic illustration of the fabrication process for the widetuning-range tunable capacitor.
(6) Fig. 4.
This derived tuning range is valid as long as the pull-in effect and does not occur, i.e., . The between plates values of and can be controlled by fabrication parameters. , then the maximum tuning range can be found by If into (6) which results in a maximum plugging in . Since is smaller than , the tuning range of , tuning range can be larger than 50%. In the case that the pull-in effect will not occur at all. Assuming the plates and can be pulled in to an infinitely close distance, an arbitrary large tuning range could in theory be achieved. In reality, the achievable tuning range value also depends on other factors, and . such as surface roughness and curvature of B. Fabrication Process Surface micromachining technique is used to fabricate the prototype devices with a Pyrex glass wafer (1 mm thick) as the substrate. A unique process to realize the variable-height sacm and m rificial layer (corresponding to in Fig. 2) is developed. Thermally evaporated gold thin film and is used as the material of the two fixed bottom plates , whereas the suspended top plate is made of electroplated Permalloy (nickel–iron alloy). Copper is used as the sacrificial layer material. Copper can be deposited using thermal
Microscopic pictures of the novel wide-tuning-range tunable capacitor.
evaporation and etched by a copper etchant (HAC : H O : H O 1 : 1 : 10), which has a very high etching selectivity between copper and the structure materials (Permalloy and gold). The copper layer can also serve as a seed layer for Permalloy electroplating. The fabrication process is illustrated in Fig. 3. First, a 0.5- m-thick gold film is thermally evaporated and patterned and and contact pads for the to make the two fixed plates . Second, a 1- m-thick copper film is suspended top plate thermally evaporated and patterned. Third, another 2- m-thick copper film is thermally evaporated to form a variable-height sacrificial layer and a 2- m-thick Ni–Fe alloy is deposited by electroplating using the copper as the seed layer. At last, the copper sacrificial layer is then etched and the entire device is released in a supercritical carbon dioxide (CO dryer. Microscopic pictures of the fabricated prototype devices are shown in Fig. 4. and In the fabricated prototype devices, the values of are 2 and 3 m, respectively. In this case, can be tuned to ) before the pull-in effect occurs between and 1 m( . This results in a maximum theoretical tuning range of 100% and . for the variable capacitance ( between
CHEN et al.: DESIGN AND MODELING OF A MICROMACHINED HIGH-
TUNABLE CAPACITOR
Fig. 5. A 3-D plot of the deformed suspended top plate (E ) when V = 18 V. The color represents the value of displacement in the thickness direction at each point.
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(a)
(b)
Fig. 6. Simulated electromechanical dynamic behaviors of the micromachined tunable capacitor when subject to a 10-V step voltage. Dynamical behaviors are also studied for different ambient air pressures (Pamb).
C. Electromechanical and Microwave Simulations 1) Static Electromechanical Simulation: The static electromechanical characteristic of a tunable capacitor is simulated using MEMCAD 4.5 software [30]. The calculated deformation of the suspended top plate caused by the electrostatic V) is shown in Fig. 5. The suspended force (when remains flat and parallel to after the detop plate ( curve formation. The simulated capacitance–voltage – is plotted in Fig. 6 together with the measurement data (the measurement data will be discussed in the testing and measurement section), which shows a maximum tuning range of 90.8%. This is different from the aforementioned theoretical value (100%) due to taking into account the fringe capacias a function of is tance. The calculated change of plotted in Fig. 7(b) together with the measurement data. When is greater than 19 V, changes directly from 1 m to zero, which means that the pull-in voltage is about 19 V from this simulation.
Fig. 7. (a) Three-dimensional plots of the measured surface profile of the novel wide-tuning-range tunable capacitor by a WYKO NT1000 optical profiler: V = 16 V. (b) The measured versus simulated h as a function of V .
2) Dynamic Electromechanical Simulation: The electromechanical dynamic behavior of the tunable capacitor can be mathematically described by a second-order system that is dominated by spring force, inertia, and viscous damping as (7) is the where denotes the mass of the movable plate , is the spring force, and is the elecdamping force, trostatic force. The spring force is calculated as where is the spring constant which is determined by using the MEMCAD static finite-element solver Abaqus. The electrocan be calculated as static force (8) denotes the overlap area between and and where is the applied voltage between them. The damping force is
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(a)
Fig. 8. C –V measurement of the novel wide-tuning range tunable capacitor using an HP4284A precision LCR meter.
mainly from the air that is squeezed underneath the top plate. and bottom The air film between the closely spaced top ( plates produces a force that opposes the motion of ( and the top plate. The damping force can be calculated as (b)
(9)
is the area, where represents the top plate, denotes the air pressure underneath the top plate , and is the ambient air pressure. The equation governing the presin the squeezed air is the nonlinear sure distribution isothermal Reynold’s equation [31] (10) is the height of the top plate above the bottom In (10), between and and between plates (i.e., and . Other parameters include initial gap m and m, air viscosity kg/(ms), Kundsen’s , and the ambient air pressure number Pa. The mean-free path of air m. Equations (7)–(10) have been numerically solved using a finite-difference method. Fig. 8 plots the simulated electromechanical dynamic behavior of the tunable capacitor when subject to a 10-V step voltage. Fig. 6 also plots the simulated electromechanical dynamic behaviors of the device under different ambient air pressures. Air damping is clearly visible in the higher pressure simulations and can be optimized for different applications. Similarly, electromechanical transient behaviors can also be studied for other design parameters to optimize the capacitor design. -Parameter Simulation: The high-fre3) Microwave quency behavior of the wide-tuning-range tunable capacitor is simulated using Sonnet em Suite software [32]. The simulated parameter when V is plotted with the measurement data in Fig. 9.
Fig. 9. The simulated versus the measured S 11 parameter of the widetuning-range capacitor. Both the (a) magnitude and (b) phase are plotted.
D. Testing and Measurement The surface profile of the tunable capacitor at different values is measured using the WYKO NT1000 optical surface of profiler. Fig. 7(a) shows the measured surface profile plotted V. The change of the spacing in 3-D graphs when as a function of is extracted from the surface profile increases from 0 to 20 V, measurement [Fig. 7(b)]. When decreases continuously from 2 to 1.2 m until the pull-in V. When decreases from 20 to effect occurs at is observed not to recover from 0 V, the suspended top plate drops to 15.8 V. When the pull-in the pull-in effect until does not completely effect occurs, the suspended top plate since cannot be decreased contact with the fixed plate to 0. Possible reasons are surface roughness of the two plates and , the existence of residual film from sacrificial layer etching, or absolute measurement calibration. Five identical prototype devices fabricated on one substrate are tested using an HP 4284A precision LCR meter at the frequency of 1 MHz (Fig. 6). The pull-in effect is observed at a DC bias of approximately 17–20 V. The difference in the pull-in voltage among the five tested devices is due to the difference in the stiffness of the four-cantilever beam suspension, resulting from the thickness variance from 1.71 to 1.84 m. The maximum tuning ranges of the five devices are 50.9%, 44.7%, 55.6%, 59.2%, and 69.8%. The parasitic capacitance associated with each device in the measurement setup is believed to cause the decrease in the achievable tuning range. scattering parameter of the tunable capacitor (when The V) is measured using a Cascade co-planar GSG-150 probe and an HP 8510B network analyzer from 45 MHz to
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Q MEMS tunable
Fig. 10. The quality factor of the wide-tuning-range highcapacitor extracted from the measured parameters.
S
10 GHz. The measurement result is plotted in Fig. 9, which shows a nearly ideal capacitive behavior in the tested frequency range with a return loss lower than 0.6 dB. The measurement data closely match the simulation data. The quality factor as a paramfunction of frequency extracted from the measured eter result is plotted in Fig. 10. From the figure, we see that a component quality factor of about 30 at 5 GHz and a self-resonant frequency far beyond 10 GHz has been achieved. III. HIGH-
MICROMACHINED VERTICAL SPIRAL INDUCTORS
Inductors are intended to store magnetic energy. However, spiral inductors fabricated directly onto the dielectric layer on top of the conductive silicon substrate have suffered performance degradation from a lower self-resonant frequency and lower quality factor. Due to their planar structure, spiral inductors have a large parasitic capacitance to silicon substrate and thus result in low self-resonance frequency. In addition, the magnetic flux along the center of the coil (passing perpendicularly into the substrate) causes substrate loss due to eddy current. These effects reduce the quality factor of integrated spiral inductors. As discussed in the Introduction, much effort has been recently made to reduce the adverse effects from the substrate so as to improve the performance of planar spiral inductors. In this section, we present the development of a high- micromachined vertical planar spiral inductor implemented in a novel 3-D PDMA process. A. PDMA PDMA is the key technology to realizing vertical planar coil inductors. A detailed discussion of this assembly process will be presented in other publications. A brief introduction of PDMA is given below by using a cantilever beam as an example. Note that the region near the fixed end is intentionally made more flexible. First, a cantilever beam with a piece of magnetic material attached to its top surface is released from the substrate by etching away the sacrificial layer underneath [Fig. 11(a)]. Next, is applied, the magnetic material piece a magnetic field is magnetized, and the cantilever beam will be rotated off the substrate by the magnetic torque generated in the magnetic material piece [Fig. 11(b)]. If the structure is designed properly,
Fig. 11.
A schematic illustration of a PDMA process.
this bending will create a plastic deformation in the flexible region. The cantilever beam will then be able to remain at a certain is removed rest angle ( ) above the substrate even after [Fig. 11(c)]. By using ductile metal such as gold in the flexible region, a good electrical connection between the assembled structure and the substrate can be easily achieved. After the vertical assembly, the structures can be further strengthened and the magnetic material can be removed if necessary. If the magnetic field is applied globally, then all the structures on one substrate can be assembled in parallel. B. Design and Fabrication of Vertical Planar Coil Inductors The core structure of the vertical planar coil inductor is identical to the conventional horizontal one, which consists of two metal layers and one dielectric layer between. As a general rule, high-conductivity metal and low-loss dielectric material should be used. In addition to this requirement, the structure of the inductor should facilitate the implementation of PDMA. The vertical planar coil inductor utilizes one-port coplanar waveguide (CPW) configuration with three test pads (ground– signal–ground) with a pitch of 150 m. The three test pads also serve as the anchor of the vertical inductors on the substrate. 1) Material Consideration: Gold is used as the material for the bottom conductor (the coil). Gold is a ductile material with high conductivity. It is an ideal plastic deformation material for the implementation of PDMA. Copper is selected as the material of the top conductor (the bridge). Copper is also a high conductivity metal and its processing is compatible with the gold bottom conductor during fabrication. Silicon oxide and nitride are good dielectric materials available in silicon IC processes. However, they are not suitable for vertical planar coil inductors due to high internal stress and poor adhesion onto metal surfaces. CYTOP amorphous flurocarbon polymer is selected as the dielectric spacer of the vertical inductors. The electrical properties of CYTOP film are similar to those of Polyimide and Telfon. However, it has a better chemical stability and adhesion to metal surfaces.
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(a)
Fig. 12. A schematic illustration of the fabrication and PDMA assembly of vertical planar coil inductors.
In order to implement PDMA, Permalloy (NiFe) is electroplated onto the surface of the gold and copper structures. The Permalloy layer will provide the magnetic force necessary for PDMA and enough stiffness to the inductor structure in the vertical position. 2) Fabrication Process: A brief illustration of the entire fabrication and assembly process is shown in Fig. 12. The substrate is a silicon wafer with a 0.6- m-thick nitride layer on top. The fabrication is conducted in the following steps. 1) A 0.5- m-thick silicon oxide layer is deposited and patterned to serve as the sacrificial layer for PDMA. 2) A 0.5- m-thick gold layer is deposited onto the substrate (with sacrificial layer underneath) and patterned to make the bottom conductor (coil) of the inductor. 3) A 2.5- m-thick CYTOP® film is spun onto the gold layer and patterned to make the dielectric spacer. 4) A 1.5- m-thick copper layer is deposited and patterned to make the upper conductor (bridge) of the inductor. 5) A 5- m-thick Permalloy layer is electroplated onto the copper and gold surface. 6) The oxide sacrificial layer is etched and the inductor structure is released from the substrate. 7) The entire inductor structure is assembled into vertical position using PDMA. Scanning electron micrographs (SEMs) of a 4.5-nH planar coil inductor before and after PDMA are shown in Fig. 13. C. Testing and Measurement Results parameter of the fabricated vertical planar coil inThe ductors is measured from 50 MHz to 4 GHz using an HP 8510C parameter is first measured while the network analyzer. The inductors are on the silicon substrate before PDMA. Next, the inductors are assembled to the vertical position using PDMA measurement is repeated. The parameter of and the inductors with identical designs fabricated on Pyrex glass substrate is also measured for comparison. parameter Fig. 14(a) shows the simulated and measured results of the planar coil inductor shown in Fig. 13. The
(b) Fig. 13. (a) SEM of a planar coil inductor fabricated on the substrate surface before the PDMA assembly. (b) SEM of the same inductor after the PDMA assembly.
test pads feeding the inductors on which probing occurs are de-embedded. Fig. 14(b) shows the simulated and measured parameter results of an inductor with an identical design inductor fabricated on Pyrex glass substrate. The test pads are not de-embedded since the inductor is on a glass substrate and the de-embedment has little effect. The simulated data is obtained by using a compact circuit model for planar coil inductor presented in [7]. The quality factor as a function of frequency extracted from both the simulated and the measured parameter results is plotted in Fig. 15. When the planar coil inductor is on the silicon substrate, it has a peak -factor of 3.5 and a self-resonant frequency of 1 GHz. When the inductor is in the vertical position after the PDMA assembly, the peak -factor increases to 12 and the self-resonant frequency goes well above 4 GHz, which are close to those of the inductor on glass substrate. For the planar coil inductors fabricated on silicon (before assembly), a large insulator capacitance and the substrate resistance dominate at higher frequencies, which leads to a self-resonant frequency of about 1 GHz. Once the inductors are assembled into the vertical position, the substrate loss and capacitance are effectively removed, which leads to the improvement in the inductor performance. Furthermore, for frequencies far below 1 GHz (where substrate effects are negligible), the glass and silicon inductor measurements correspond exactly as expected.
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(a)
(a)
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(b) Fig. 14. (a) A Smith chart showing the simulated and measured S parameter results of the planar coil inductor shown in Fig. 13 before and after PDMA. (b) A Smith chart showing the simulated and measured S parameter results of an inductor with identical design fabricated on glass substrate. The inductance of both inductors is 4.5 nH.
IV. DISCUSSION AND CONCLUSION We have presented the design and modeling of a novel electrostatically actuated high- MEMS tunable capacitor with a large tuning range and a novel high- vertical planar coil MEMS inductor achieved by using a 3-D assembly process—PDMA. The design of the tunable capacitor and the vertical planar coil inductor is compatible with the standard IC fabrication process and is therefore suitable for various RF IC applications. Electromechanical (static and dynamic) and microwave -parameter behaviors of the tunable capacitor have been characterized. The tunable capacitor design keeps the simplicity of a conventional two-parallel-plate configuration, while overcoming its disadvantage of low tuning range. A maximum controllable tuning range of 69.8% at 1 MHz has been obtained experimentally. A component quality factor of about 30 at 5 GHz and a self-resonant frequency beyond 10 GHz has been achieved. Due to the small but finite intrinsic stress of the Permalloy film, the size of the suspended top plate is made smaller than 500 m 500 m. This limits the base capacitance of the tunable capacitor. Increasing the area of the parallel plates can achieve larger capacitance. However, it requires thin-film materials with even smaller internal stress, which is difficult to achieve. A parallel tunable capacitor array
(c) Fig. 15. The quality factor of the planar coil inductor extracted from the simulated and measured S parameters: (a) the inductor on silicon before PDMA, (b) the inductor in vertical position after PDMA, and (c) an inductor with identical design on glass substrate.
Fig. 16. A microscopic picture of an array of four wide-tuning-range tunable capacitors.
[27] is under development to increase the overall capacitance value Fig. 16. The designed vertical planar coil inductors offer two major advantages over conventional on-substrate ones: they occupy
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much smaller substrate space and suffer less substrate and parasitic loss. In this work, oxide is used as the sacrificial material for PDMA. Sometimes oxide is used as the dielectric for IC devices on the same substrate and thus cannot be removed. In this case, the oxide sacrificial layer can be substituted with other materials such as photo resist. In order to facilitate the measurement, the vertical planar coil inductors tested are not strengthened after PDMA. However, the inductor structure can be strengthened after PDMA by using different methods such as Parylene coating to achieve the necessary stiffness and robustness. While the -factor of vertical planar coil inductors can be improved by depositing thicker metal layers during the fabrication, experiments are also being conducted to explore various methods to thicken and strengthen the metal layers of the planar coil inductors while they are in the vertical position after the PDMA assembly.
[15] H. Lakdawala, X. Zhu, H. Luo, S. Santhanam, L. R. Carley, and G. F. Fedder, “Micromachined high- inductors in a 0.18-m copper interconnect low-K dielectric CMOS process,” IEEE J. Solid-State Circuits, vol. 3, Mar. 2002. [16] B. K. Kim, B. K. Ko, and K. Lee, “Monolithic planar RF inductor and waveguide structures on silicon with performance comparable to those in GaAs MMIC,” in IEDM Tech. Dig., 1995, pp. 717–720. [17] J. B. Yoon, C. H. Han, E. Yoon, and C. K. Kim, “High-performance three-dimensional on-chip inductors fabricated by novel micromachining technology for RF MMIC,” in IEEE MTT-S Dig., 1999, pp. 1523–1526. [18] D. Young, V. Malba, J. Ou, A. Bernhardt, and B. Boser, “Monolithic high performance three-dimensional coil inductors for wireless communication applications,” in IEDM Tech. Dig., 1997, pp. 67–70. [19] J. B. Yoon, B. K. Kim, C. H. Han, E. Yoon, K. Lee, and C. K. Kim, “High-performance electroplated solenoid-type integrated inductor (SI2) for RF applications using simple 3D surface micromachining technology,” in IEDM Tech. Dig., 1998, pp. 544–547. [20] J. B. Yoon and C. T. C. Ngyuen, “A high-Q tunable micromachined capacitor with moveable dielectric for RF applications,” Proc. IEEE Electron Devices Meeting, pp. 489–492, 2000. [21] J. B. Yoon, “Micromachined high-Q overhang inductors fabricated on silicon and glass substrates,” in IEDM Tech. Dig., 1999, pp. 753–756. [22] D. J. Sadler, S. Gupta, and C. H. Ahn, “Micromachined spiral inductors using UV-LIGA techniques,” IEEE Trans. Magn., vol. 3, pp. 2897–2899, July 2001. [23] V. M. Lubecek, B. Barber, E. Chan, D. Lopez, M. E. Gross, and P. Gammel, “Self-assembling MEMS variable and fixed RF inductors,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 2093–2098, Nov. 2001. [24] G. W. Dahlmann, E. M. Yeatman, P. R. Young, I. D. Robertson, and S. Lucyszyn, “MEMS high Q microwave inductors using solder surface tension self-assembly,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 1, 2001, pp. 329–332. [25] C. T.-C. Nguyen, L. Katehi, and G. Rebeiz, “Micromachined devices for wireless communications,” Proc. IEEE, vol. 86, pp. 1756–1768, 1998. [26] C. T.-C. Nguyen, “Micromechanical resonators for oscillators and filters,” in Proc. IEEE Ultrasonics Symp., 1995, pp. 489–499. [27] J. Zou, C. Liu, J. Schutt-Aine, J. H. Chen, and S. M. Kang, “Development of a wide tuning range MEMS tunable capacitor for wireless communication systems,” in IEDM Tech. Dig., 2000, pp. 403–406. [28] N. Chomnawang and J. B. Lee, “On-chip 3D air core micro-inductor for high-frequency applications using deformation of sacrificial polymer,” in Proc. SPIE Smart Structure and Materials Symp., 2001. [29] J. Zou, C. Liu, and J. E. Schutt-Aine, “Development of a wide-tuningrange two-parallel-plate tunable capacitor for integrated wireless communication systems,” Int. J. RF Microwave Computed Aided Eng., vol. 11, no. 5, pp. 322–329, Sept. 2001. [30] “MEMSCAD 4.5 user guide,” Microcosom Technologies, Inc. [31] E. S. Hung and S. D. Senturia, “Generating efficient dynamica models for microelectromechanical systems from a few finite element simulation runs,” J. Microelectromech. Syst., pp. 280–289, Sept. 1999. [32] “Sonnet em Suite 6.0 user manual,” Sonnet Software, Inc..
ACKNOWLEDGMENT The authors would like to thank the anonymous reviews for helpful comments. REFERENCES [1] D. Young, V. Malba, J. Ou, A. Bernhardt, and B. Boser, “A low-noise RF voltage-controlled oscillator using on-chip high- three dimensional coil inductor and micromachined variable capacitor,” in Tech. Dig. Solid-State Sensors and Actuator Workshop, Hilton Head Island, SC, 1998, pp. 128–131. [2] , “Monolithic high-performance three-dimensional coil inductors for wireless communication applications,” in IEDM Tech. Dig., 1997, pp. 67–70. [3] D. J. Young and B. E. Boser, “A micromachined variable capacitor for monolithic low-noise VCOs,” in Tech. Dig. Solid-State Sensors and Actuator Workshop, Hilton Head Island, SC, 1996, pp. 86–89. [4] A. Dec and K. Suyama, “Micromachined varactors with wide tuning range,” IEEE Trans. Microwave Theory Tech., vol. 46, pp. 2587–2596, Dec. 1998. [5] J. Yao, S. Park, and J. DeNatale, “High tuning ratio MEMS based tunable capacitors for RF communications applications,” in Tech. Dig. Sensors and Actuators Workshop, Hilton Head Island, SC, 1998, pp. 124–127. [6] Z. Feng, H. Zhang, W. Zhang, B. Su, K. Gupta, V. Bright, and Y. Lee, “MEMS-based variable capacitor for millimeter-wave applications,” in Tech. Dig. Solid-State Sensors and Actuators Workshop, Hilton Head Island, SC, 2000, pp. 255–258. [7] J. N. Burghartz, D. C. Edelstein, M. Soyuer, H. A. Ainspan, and K. A. Jerkins, “RF design aspects of spiral inductors on silicon,” IEEE J. SolidState Circuits, vol. 33, pp. 2028–2033, Dec. 1998. [8] C. P. Yue and S. S. Wong, “Physical modeling of spiral inductors on silicon,” IEEE Trans. Electron Devices, vol. 47, pp. 560–568, Mar. 2000. [9] J. N. Burghartz, M. Soyuer, and K. A. Jerkins, “Microwave inductors and capacitors in standard multilevel interconnect silicon technology,” IEEE Trans. Microwave Theory Tech., vol. 44, pp. 100–104, Jan. 1996. [10] K. B. Ashby, I. A. Koullias, W. C. Finley, J. J. Bastek, and S. Moinian, “High inductors for wireless applications in a complementary silicon bipolar process,” IEEE J. Solid-State Circuits, vol. 31, pp. 4–9, Jan. 1996. [11] M. Ozgur, M. Zaghloul, and M. Gaitan, “High backside micromachined CMOS inductors,” in Proc. 1999 IEEE Int. Symp. Circuits and Systems (ISCAS’99), vol. 2, 1999, pp. 577–580. [12] H. Jian, J. L. A. Yeh, Y. Wang, and N. Tien, “Electromagnetically shielded highCMOS compatible copper inductors,” in IEEE Solid-State Circuits Conf. Dig., Feb. 2000, pp. 330–331. [13] C. Y. Chi and G. M. Rebeiz, “Planar millimeter-wave microstrip lumped elements using micro-machining techniques,” in IEEE MTT-S Int. Microwave Symp. Dig., May 1994, pp. 657–660. [14] Y. Sun, Y. H. Van Zejl, J. L. Tauritz, and R. G. F. Baets, “Suspended membrane inductors and capacitors for application in silicon MMIC’s,” in IEEE Microwave and Millimeter Wave Monolithic Circuits Symp. Dig., June 1996, pp. 99–102.
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Jinghong Chen (M’03) received the B.S. and M.S. degrees in engineering physics from Tsinghua University, China, the M.E. degree in electrical engineering from the University of Virginia, Charlottesville, and the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign. In January 2001, he joined the high-speed communication VLSI research department of Bell Labs Lucent Technologies, Holmdel, NJ, as Member of Technical Staff. Since March 2001, he has been with Agere Systems, formerly the microelectronics group of Lucent Technologies. His current research involves designing high-speed CMOS circuits for communication and signal processing systems. He is also interested in the development of novel numerical algorithms and their applications to the modeling and simulation of microelectromechanical structures and systems.
CHEN et al.: DESIGN AND MODELING OF A MICROMACHINED HIGH-
TUNABLE CAPACITOR
Jun Zou received the B.S. degree from the Chongqing University, China, and the M.S. degree from Tsinghua University, China, in 1994 and 1997, respectively. He is currently pursuing the Ph.D. degree in electrical engineering at the University of Illinois at Urbana-Champaign (UIUC). His major research interest lines in the development of novel micromachining technologies and their applications to RF MEMS devices.
Chang Liu (S’92–A’95–M’00–SM’01) received the undergraduate degree from Tsinghua University, Beijing, China. He received the M.S. and Ph.D. degrees from the California Institute of Technology, Pasadena, in 1991 and 1996, respectively. He is currently an Assistant Professor at the University of Illinois at Urbana-Champaign (UIUC), where he directs the Micro Actuators, Sensors, and Systems (MASS) research group. His group is concentrating on the following research areas: microparallel assembly of hinged acceleration-resistant microstructures, polymer MEMS fluidics systems, biomimetic sensors, telemetry, and investigation of microscale bubble generation.
José E. Schutt-Ainé (S’87–M’88–SM’98) received the B.S. degree from the Massachusetts Institute of Technology, Cambridge, in 1981, and M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign (UIUC), in 1984 and 1988, respectively. From 1981 to 1983, he was an Application Engineer at the Hewlett-Packard Microwave Technology Center, Santa Rosa, CA, where he worked on transistor modeling. During his graduate studies at UIUC, he held summer positions at GTE Network Systems in Northlake, IL. In 1989, he joined the faculty of the Electromagnetic Communication Laboratory at UIUC where he is currently an Associate Professor of Electrical and Computer Engineering. His interests include microwave theory and measurements, electromagnetics, high-frequency circuit design, and electronic packaging.
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Sung-Mo (Steve) Kang (S’73–M’75–SM’80–F’90) received Ph.D. degree in electrical engineering from the University of California, Berkeley (UC Berkeley), in 1975. Until 1985, he was with AT&T Bell Laboratories at Murray Hill and Holmdel, NJ, and also served as a faculty member of Rutgers University, Piscataway, NJ. In 1985, he joined the University of Illinois at Urbana-Champaign, where he was Professor of electrical and computer engineering, Computer Science and Research Professor of the Coordinated Science Laboratory and the Beckman Institute for Advanced Science and Technology. He was named the first Charles Marshall Senior University Scholar, an Associate in the Center for Advanced Study, and has served as the Founding Director of Center for ASIC Research and Development at the University of Illinois at Urbana-Champaign. He was a Visiting Professor at the Swiss Federal Institute of Technology, Lausanne, in 1989, the University of Karlsruhe, Germany, in 1997, and at the Technical University of Münich, Germany, in 1998. From August 1995 to December 2000, he served as Head of the Department of Electrical and Computer Engineering. In January 2001, he joined the University of California at Santa Cruz as Dean of Baskin School of Engineering. His current research interests include low-power VLSI design, optimization for performance, reliability, and manufacturability, mixed-signal mixed-technology integrated systems, modeling and simulation of semiconductor devices and circuits, high-speed optoelectronic circuits, and fully optical network systems. He holds six patents, has published over 300 papers, and has coauthored eight books, Design Automation For Timing-Driven Layout Synthesis (Boston, MA: Kluwer, 1992), Hot-Carrier Reliability of MOS VLSI Circuits (Boston, MA: Kluwer, 1993), Physical Design for Multichip Modules (Boston, MA: Kluwer, 1994), and Modeling of Electrical Overstress in Integrated Circuits (Boston, MA: Kluwer, 1994), Electrothermal Analysis of VLSI Systems (Boston, MA: Kluwer, 1999), CMOS Digital Circuits: Analysis and Design (New York: McGraw–Hill, 1995, 2nd ed. 1999), and Computer-Aided Design of Optoelectronic Integrated Circuits and Systems (Englewood Cliffs, NJ: Prentice–Hall, 1996). Dr. Kang is a Fellow of the ACM and AAAS, a Foreign Member of the National Academy of Engineering of Korea, and is listed in Who’s Who in America, Who’s Who in Technology, Who’s Who in Engineering, and Who’s Who in the Midwest. He is a recipient of the Outstanding Alumnus Award in Electrical Engineering, UC Berkeley (2001), IEEE Third Millennium Medal (2000), SRC Technical Excellence Award (1999), IEEE Circuts and Systems (CAS) Society Golden Jubilee Medal (1999), KBS Award in Science and Technology (1998), IEEE CAS Society Technical Achievement Award (1997), Humboldt Research Award for Senior U.S. Scientists (1996), IEEE Graduate Teaching Technical Field Award (1996), IEEE CAS Society Meritorious Service Award (1994), SRC Inventor Recognition Awards (1993, 1996), IEEE CAS Darlington Prize Paper Award (1993), ICCD Best Paper Award (1986), and Myril B. Reed Best Paper Award (1979). He was an IEEE CAS Distinguished Lecturer (1994–1997) and has served as a member of the Board of Governors, Secretary of Treasurer, Administrative Vice President, and 1991 President of the IEEE Circuits and Systems Society. He has also served on the program committees and technical committees of major international conferences that include DAC, ICCAD, ICCD, ISCAS, MCMC, International Conference on VLSI and CAD (ICVC), Asia-Pacific Conference on Circuits and Systems, LEOS Topical Meeting, SPIE OE/LASE Meeting. He has served on the editorial boards of PROCEEDINGS OF THE IEEE, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, International Journal of Circuit Theory and Applications, and Circuits, Signals and Systems. He was the Founding Editor-in-Chief of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003
Design and Modeling of a Micromachined High-Q Tunable Capacitor With Large Tuning Range and a Vertical Planar Spiral Inductor Jinghong Chen, Member, IEEE, Jun Zou, Chang Liu, Senior Member, IEEE, José E. Schutt-Ainé, Senior Member, IEEE, and Sung-Mo (Steve) Kang, Fellow, IEEE
Abstract—In wireless communication systems, passive elements including tunable capacitors and inductors often need high quality factor ( -factor). In this paper, we present the design and modeling of a novel high -factor tunable capacitor with large tuning range and a high -factor vertical planar spiral inductor implemented in microelectromechanical system (MEMS) technology. Different from conventional two-parallel-plate tunable capacitors, the novel tunable capacitor consists of one suspended top plate and two fixed bottom plates. One of the two fixed plates and the top plate form a variable capacitor, while the other fixed plate and the top plate are used to provide electrostatic actuation for capacitance tuning. For the fabricated prototype tunable capacitors, a maximum controllable tuning range of 69.8% has been achieved, exceeding the theoretical tuning range limit (50%) of conventional two-parallel-plate tunable capacitors. This tunable capacitor also exhibits a very low return loss of less than 0.6 dB in the frequency range from 45 MHz to 10 GHz. The high -factor planar coil inductor is first fabricated on silicon substrate and then assembled to the vertical position by using a novel three-dimensional microstructure assembly technique called plastic deformation magnetic assembly (PDMA). Inductors of different dimensions are fabricated and tested. The -parameters of the inductors before and after PDMA are measured and compared, demonstrating superior performance due to reduced substrate loss and parasitics. The new vertical planar spiral inductor also has the advantage of occupying much smaller silicon areas than the conventional planar spiral inductors. Index Terms—Electrostatic actuation, magnetic actuation, microelectromechanical systems (MEMS), modeling and simulation, monolithic inductor, quality factor, RFIC, self-resonance, varactor, variable capacitor.
I. INTRODUCTION
I
N WIRELESS communication systems, passive elements including tunable capacitors and inductors often need a high quality factor and high self-resonant frequency. High- tunable capacitors and inductors can lead to improved power or figure of merit in low noise amplifiers, low insertion loss in bandpass Manuscript received May 7, 2002; revised October 16, 2002. This work was supported by DARPA Composite CAD program. The review of this paper was arranged by Editor H. Shichijo. J. Chen is with Agere Systems, Holmdel, NJ 07733 USA (e-mail: jchen42@ agere.com). J. Zou, C. Liu, and J. E. Schutt-Ainé are with the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL 61801 USA. S.-M. Kang is with the Baskin School of Engineering, University of California, Santa Cruz, CA 95064 USA Digital Object Identifier 10.1109/TED.2003.810479
filters, and better phase noise and power in voltage-controlled oscillators (VCOs). Currently many off-chip discrete passive elements are widely used to meet these requirements. Due to the problems in packaging complexity, large system area, and high cost when utilizing off-chip passive components, there have been many investigations to realize high-performance on-chip passive elements that could be monolithically integrated with active circuitry. A new solution for this has arisen with the recent development of MEMS technology. RF circuits such as VCOs and tunable filters have been developed using on-chip micromachined inductors and tunable capacitors. Young et al. reported a VCO [1] that contains a micromachined three-dimensional (3-D) coil inductor [2] and a two-parallel-plate tunable capacitor with a tuning range of 16% [3]. Both passive elements are micromachined on silicon substrates and thus can be integrated with active circuit components using modified integrated circuit (IC) fabrication processes. Tunable capacitors and inductors constructed using MEMS technology [1]–[6], [9]–[28] often can provide high quality factor through new structure design or operational principles. In addition, a microelectromechanical system (MEMS) tunable capacitor also has the potential of offering a large tuning range compared with semiconductor diode counterparts fabricated via conventional IC technology. Among all the MEMS tunable capacitors developed to date, parallel-plate configuration is the most commonly used. Such micromechanical capacitors often consist of suspended top metal plates that can be electrostatically displaced (via applied voltages) over bottom metal plates to vary the capacitance between the plates. Because these capacitors can be constructed in low-resistivity metal materials, they exhibit much higher -factors than the semiconductor counterparts, which suffer from greater losses due to excessive semiconductor series resistance. A -factor on the order of 60 has been reported for the micromachined tunable capacitor reported in [3]. However, the theoretical tuning range of such capacitors is limited to 50% by the pull-in effect. The actual achieved tuning range is often much smaller than the theoretical value due to parasitic capacitance (e.g., a measured tuning range of 16% was reported in [3]). Various broad-band communication applications require a wide tuning range. Recently, much effort has been made to improve the tuning capability of MEMS tunable capacitors. Dec et al. [4] uses a three-parallel-plate configuration (two suspended plates and one fixed plate on the substrate) to compensate
0018-9383/03$17.00 © 2003 IEEE
CHEN et al.: DESIGN AND MODELING OF A MICROMACHINED HIGH-
TUNABLE CAPACITOR
for the pull-in effect and obtain a tuning range of 87%. The fabrication process requires two layers of structural materials and two layers of sacrificial materials. Yao, et al. [5] reported a tunable capacitor with a tuning range of 200%. It is based on lateral comb structures (instead of parallel-plate) etched by deep reactive ion etching (DRIE) on silicon-on-insulator (SOI) substrate. Feng et al. [6] used a thermal actuator in their tunable capacitor and achieved a tuning range of 270%. The disadvantage of thermal actuators is that their response speed is generally slower than that of electrostatic actuators. We report in this paper the development and modeling of a novel electrostatically actuated tunable capacitor. This new design keeps the simplicity of the conventional two-parallel-plate configuration, while providing a much wider tuning range. Only one structural layer and one sacrificial layer are used. The measured tuning range achieved was 69.8%, exceeding the 50% tuning range limit on conventional two-parallel-plate tunable capacitors. The capacitor operates under a wide frequency range (45 MHz to 10 GHz) with a signal loss below 0.6 dB. A component quality factor of 30 at 5 GHz and a self-resonant frequency beyond 10 GHz has been achieved. The new tunable capacitor is fabricated using a standard surface micromachining process and thus can be monolithically integrated with IC circuits. Another important RF MEMS component is a micromachined high- inductor. Although planar spiral inductors can be integrated with other circuits using current standard IC fabrication process, their performance is still unsatisfactory. Oftentimes, planar spiral inductors are directly fabricated onto the dielectric layer on top of the conductive substrate, which lowers the quality factors and degrades the performance by introducing extra loss, noise, and parasitic capacitance [7], [8]. Another disadvantage of a planar spiral inductor lies in the fact that it has a large footprint to achieve the inductance value [9]. In recent years, much effort has been made to improve the performance of planar coil inductors. Metal materials with higher conductivity or thicker metal layers are utilized to decrease the resistance of the coil [10]. Meanwhile, different methods are proposed to reduce the substrate loss and parasitic, including removing the substrate underneath the inductor [11]–[15] or applying a thick polymide layer to separate the inductor farther away from the substrate [16]. A serious problem is the limited separation that can be achieved. Moreover, for techniques involving substrate etching, there are concerns about process compatibility, and the reduced mechanical stability for the substrate. More recently, planar coil inductors levitated above the substrate are realized using a sacrificial metallic mode (SMM) process [17]. Three-dimensional solenoid on-chip inductors developed by using 3-D laser lithography or surface micromachining technology have also been demonstrated [18], [19]. These methods may involve certain materials or fabrication steps, which are not compatible with current standard fabrication process. Moreover, none of the methods mentioned above has solved the large footprint problem of conventional planar spiral inductors. This paper reports a high- vertical planar coil inductors developed by using a novel 3-D self-assembly process called plastic deformation magnetic assembly (PDMA). Experimental results show that the vertical planar coil inductor suffers less substrate and parasitic loss than the
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Fig. 1. A schematic model of a conventional electrostatically actuated twoparallel-plate tunable capacitor.
conventional horizontal counterparts, therefore it can achieve a higher quality factor and self-resonant frequency. Another major advantage of the vertical inductors is that they have almost zero footprints and thus occupy much smaller substrate area than the conventional planar inductors. II. HIGH-
MICROMACHINED TUNABLE CAPACITOR WITH A LARGE TUNING RANGE
In this section, we present the design and modeling of the micromachined high- tunable capacitor with a large tuning range. A. Operating Principle Fig. 1 shows a conventional parallel-plate tunable capacitor which consists of a suspended top plate and a fixed bottom plate, with an overlap area of and initial spacing of . When a dc voltage is applied across the two plates, the spacing between these two plates is reduced. Neglecting the fringe effect, the value of the capacitance ( between these two plates can be determined by (1) is applied, an attractive electrostatic force ( and, when is generated between the two plates with the value of the force given by (2) An effective spring constant defined as
for the electrostatic force can be
(3) The mechanical suspension of the top plate has a spring constant . When the top plate is displaced, the suspension produces . The magnitude of is a restoring force, designated as . At equilibrium, the magnitudes of related to by and are equal, thus (4) The expression of
in terms of
is (5)
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003
Fig. 2. A schematic model of the novel wide-tuning-range tunable capacitor.
Note that the two force constants are equal in magnitude when . The corresponding value of the value of reaches (at ) is called the pull-in voltage ( . If is and is beyond the critical continuously increased beyond , no equilibrium position can be reached until the point of two plates are snapped into contact (pull-in effect). Thus, the capacitance of the conventional two-parallel-plate tunable capacitor can only be controllably changed to 150% of its original value at most. As a result, theoretically the maximum controllable tuning range is then 50%. The schematic model of our novel wide-tuning-range tunable capacitor is shown in Fig. 2. It consists of three plates that are , , and . The plate is a movable top designated as plate suspended by four cantilever beams. The plate , which is fixed on the bottom substrate, forms a variable capacitor by (the outer fixed bottom coupling with the plate . The plate are used to provide the electrostatic actuation. An plate) and is applied between plates and . At actuation voltage ( V), is designed to be smaller than . When rest ( (top movable plate) is moved by a distance of the plate under a given applied , the relative tuning range is derived as
Fig. 3. A schematic illustration of the fabrication process for the widetuning-range tunable capacitor.
(6) Fig. 4.
This derived tuning range is valid as long as the pull-in effect and does not occur, i.e., . The between plates values of and can be controlled by fabrication parameters. , then the maximum tuning range can be found by If into (6) which results in a maximum plugging in . Since is smaller than , the tuning range of , tuning range can be larger than 50%. In the case that the pull-in effect will not occur at all. Assuming the plates and can be pulled in to an infinitely close distance, an arbitrary large tuning range could in theory be achieved. In reality, the achievable tuning range value also depends on other factors, and . such as surface roughness and curvature of B. Fabrication Process Surface micromachining technique is used to fabricate the prototype devices with a Pyrex glass wafer (1 mm thick) as the substrate. A unique process to realize the variable-height sacm and m rificial layer (corresponding to in Fig. 2) is developed. Thermally evaporated gold thin film and is used as the material of the two fixed bottom plates , whereas the suspended top plate is made of electroplated Permalloy (nickel–iron alloy). Copper is used as the sacrificial layer material. Copper can be deposited using thermal
Microscopic pictures of the novel wide-tuning-range tunable capacitor.
evaporation and etched by a copper etchant (HAC : H O : H O 1 : 1 : 10), which has a very high etching selectivity between copper and the structure materials (Permalloy and gold). The copper layer can also serve as a seed layer for Permalloy electroplating. The fabrication process is illustrated in Fig. 3. First, a 0.5- m-thick gold film is thermally evaporated and patterned and and contact pads for the to make the two fixed plates . Second, a 1- m-thick copper film is suspended top plate thermally evaporated and patterned. Third, another 2- m-thick copper film is thermally evaporated to form a variable-height sacrificial layer and a 2- m-thick Ni–Fe alloy is deposited by electroplating using the copper as the seed layer. At last, the copper sacrificial layer is then etched and the entire device is released in a supercritical carbon dioxide (CO dryer. Microscopic pictures of the fabricated prototype devices are shown in Fig. 4. and In the fabricated prototype devices, the values of are 2 and 3 m, respectively. In this case, can be tuned to ) before the pull-in effect occurs between and 1 m( . This results in a maximum theoretical tuning range of 100% and . for the variable capacitance ( between
CHEN et al.: DESIGN AND MODELING OF A MICROMACHINED HIGH-
TUNABLE CAPACITOR
Fig. 5. A 3-D plot of the deformed suspended top plate (E ) when V = 18 V. The color represents the value of displacement in the thickness direction at each point.
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(a)
(b)
Fig. 6. Simulated electromechanical dynamic behaviors of the micromachined tunable capacitor when subject to a 10-V step voltage. Dynamical behaviors are also studied for different ambient air pressures (Pamb).
C. Electromechanical and Microwave Simulations 1) Static Electromechanical Simulation: The static electromechanical characteristic of a tunable capacitor is simulated using MEMCAD 4.5 software [30]. The calculated deformation of the suspended top plate caused by the electrostatic V) is shown in Fig. 5. The suspended force (when remains flat and parallel to after the detop plate ( curve formation. The simulated capacitance–voltage – is plotted in Fig. 6 together with the measurement data (the measurement data will be discussed in the testing and measurement section), which shows a maximum tuning range of 90.8%. This is different from the aforementioned theoretical value (100%) due to taking into account the fringe capacias a function of is tance. The calculated change of plotted in Fig. 7(b) together with the measurement data. When is greater than 19 V, changes directly from 1 m to zero, which means that the pull-in voltage is about 19 V from this simulation.
Fig. 7. (a) Three-dimensional plots of the measured surface profile of the novel wide-tuning-range tunable capacitor by a WYKO NT1000 optical profiler: V = 16 V. (b) The measured versus simulated h as a function of V .
2) Dynamic Electromechanical Simulation: The electromechanical dynamic behavior of the tunable capacitor can be mathematically described by a second-order system that is dominated by spring force, inertia, and viscous damping as (7) is the where denotes the mass of the movable plate , is the spring force, and is the elecdamping force, trostatic force. The spring force is calculated as where is the spring constant which is determined by using the MEMCAD static finite-element solver Abaqus. The electrocan be calculated as static force (8) denotes the overlap area between and and where is the applied voltage between them. The damping force is
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(a)
Fig. 8. C –V measurement of the novel wide-tuning range tunable capacitor using an HP4284A precision LCR meter.
mainly from the air that is squeezed underneath the top plate. and bottom The air film between the closely spaced top ( plates produces a force that opposes the motion of ( and the top plate. The damping force can be calculated as (b)
(9)
is the area, where represents the top plate, denotes the air pressure underneath the top plate , and is the ambient air pressure. The equation governing the presin the squeezed air is the nonlinear sure distribution isothermal Reynold’s equation [31] (10) is the height of the top plate above the bottom In (10), between and and between plates (i.e., and . Other parameters include initial gap m and m, air viscosity kg/(ms), Kundsen’s , and the ambient air pressure number Pa. The mean-free path of air m. Equations (7)–(10) have been numerically solved using a finite-difference method. Fig. 8 plots the simulated electromechanical dynamic behavior of the tunable capacitor when subject to a 10-V step voltage. Fig. 6 also plots the simulated electromechanical dynamic behaviors of the device under different ambient air pressures. Air damping is clearly visible in the higher pressure simulations and can be optimized for different applications. Similarly, electromechanical transient behaviors can also be studied for other design parameters to optimize the capacitor design. -Parameter Simulation: The high-fre3) Microwave quency behavior of the wide-tuning-range tunable capacitor is simulated using Sonnet em Suite software [32]. The simulated parameter when V is plotted with the measurement data in Fig. 9.
Fig. 9. The simulated versus the measured S 11 parameter of the widetuning-range capacitor. Both the (a) magnitude and (b) phase are plotted.
D. Testing and Measurement The surface profile of the tunable capacitor at different values is measured using the WYKO NT1000 optical surface of profiler. Fig. 7(a) shows the measured surface profile plotted V. The change of the spacing in 3-D graphs when as a function of is extracted from the surface profile increases from 0 to 20 V, measurement [Fig. 7(b)]. When decreases continuously from 2 to 1.2 m until the pull-in V. When decreases from 20 to effect occurs at is observed not to recover from 0 V, the suspended top plate drops to 15.8 V. When the pull-in the pull-in effect until does not completely effect occurs, the suspended top plate since cannot be decreased contact with the fixed plate to 0. Possible reasons are surface roughness of the two plates and , the existence of residual film from sacrificial layer etching, or absolute measurement calibration. Five identical prototype devices fabricated on one substrate are tested using an HP 4284A precision LCR meter at the frequency of 1 MHz (Fig. 6). The pull-in effect is observed at a DC bias of approximately 17–20 V. The difference in the pull-in voltage among the five tested devices is due to the difference in the stiffness of the four-cantilever beam suspension, resulting from the thickness variance from 1.71 to 1.84 m. The maximum tuning ranges of the five devices are 50.9%, 44.7%, 55.6%, 59.2%, and 69.8%. The parasitic capacitance associated with each device in the measurement setup is believed to cause the decrease in the achievable tuning range. scattering parameter of the tunable capacitor (when The V) is measured using a Cascade co-planar GSG-150 probe and an HP 8510B network analyzer from 45 MHz to
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Fig. 10. The quality factor of the wide-tuning-range highcapacitor extracted from the measured parameters.
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10 GHz. The measurement result is plotted in Fig. 9, which shows a nearly ideal capacitive behavior in the tested frequency range with a return loss lower than 0.6 dB. The measurement data closely match the simulation data. The quality factor as a paramfunction of frequency extracted from the measured eter result is plotted in Fig. 10. From the figure, we see that a component quality factor of about 30 at 5 GHz and a self-resonant frequency far beyond 10 GHz has been achieved. III. HIGH-
MICROMACHINED VERTICAL SPIRAL INDUCTORS
Inductors are intended to store magnetic energy. However, spiral inductors fabricated directly onto the dielectric layer on top of the conductive silicon substrate have suffered performance degradation from a lower self-resonant frequency and lower quality factor. Due to their planar structure, spiral inductors have a large parasitic capacitance to silicon substrate and thus result in low self-resonance frequency. In addition, the magnetic flux along the center of the coil (passing perpendicularly into the substrate) causes substrate loss due to eddy current. These effects reduce the quality factor of integrated spiral inductors. As discussed in the Introduction, much effort has been recently made to reduce the adverse effects from the substrate so as to improve the performance of planar spiral inductors. In this section, we present the development of a high- micromachined vertical planar spiral inductor implemented in a novel 3-D PDMA process. A. PDMA PDMA is the key technology to realizing vertical planar coil inductors. A detailed discussion of this assembly process will be presented in other publications. A brief introduction of PDMA is given below by using a cantilever beam as an example. Note that the region near the fixed end is intentionally made more flexible. First, a cantilever beam with a piece of magnetic material attached to its top surface is released from the substrate by etching away the sacrificial layer underneath [Fig. 11(a)]. Next, is applied, the magnetic material piece a magnetic field is magnetized, and the cantilever beam will be rotated off the substrate by the magnetic torque generated in the magnetic material piece [Fig. 11(b)]. If the structure is designed properly,
Fig. 11.
A schematic illustration of a PDMA process.
this bending will create a plastic deformation in the flexible region. The cantilever beam will then be able to remain at a certain is removed rest angle ( ) above the substrate even after [Fig. 11(c)]. By using ductile metal such as gold in the flexible region, a good electrical connection between the assembled structure and the substrate can be easily achieved. After the vertical assembly, the structures can be further strengthened and the magnetic material can be removed if necessary. If the magnetic field is applied globally, then all the structures on one substrate can be assembled in parallel. B. Design and Fabrication of Vertical Planar Coil Inductors The core structure of the vertical planar coil inductor is identical to the conventional horizontal one, which consists of two metal layers and one dielectric layer between. As a general rule, high-conductivity metal and low-loss dielectric material should be used. In addition to this requirement, the structure of the inductor should facilitate the implementation of PDMA. The vertical planar coil inductor utilizes one-port coplanar waveguide (CPW) configuration with three test pads (ground– signal–ground) with a pitch of 150 m. The three test pads also serve as the anchor of the vertical inductors on the substrate. 1) Material Consideration: Gold is used as the material for the bottom conductor (the coil). Gold is a ductile material with high conductivity. It is an ideal plastic deformation material for the implementation of PDMA. Copper is selected as the material of the top conductor (the bridge). Copper is also a high conductivity metal and its processing is compatible with the gold bottom conductor during fabrication. Silicon oxide and nitride are good dielectric materials available in silicon IC processes. However, they are not suitable for vertical planar coil inductors due to high internal stress and poor adhesion onto metal surfaces. CYTOP amorphous flurocarbon polymer is selected as the dielectric spacer of the vertical inductors. The electrical properties of CYTOP film are similar to those of Polyimide and Telfon. However, it has a better chemical stability and adhesion to metal surfaces.
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(a)
Fig. 12. A schematic illustration of the fabrication and PDMA assembly of vertical planar coil inductors.
In order to implement PDMA, Permalloy (NiFe) is electroplated onto the surface of the gold and copper structures. The Permalloy layer will provide the magnetic force necessary for PDMA and enough stiffness to the inductor structure in the vertical position. 2) Fabrication Process: A brief illustration of the entire fabrication and assembly process is shown in Fig. 12. The substrate is a silicon wafer with a 0.6- m-thick nitride layer on top. The fabrication is conducted in the following steps. 1) A 0.5- m-thick silicon oxide layer is deposited and patterned to serve as the sacrificial layer for PDMA. 2) A 0.5- m-thick gold layer is deposited onto the substrate (with sacrificial layer underneath) and patterned to make the bottom conductor (coil) of the inductor. 3) A 2.5- m-thick CYTOP® film is spun onto the gold layer and patterned to make the dielectric spacer. 4) A 1.5- m-thick copper layer is deposited and patterned to make the upper conductor (bridge) of the inductor. 5) A 5- m-thick Permalloy layer is electroplated onto the copper and gold surface. 6) The oxide sacrificial layer is etched and the inductor structure is released from the substrate. 7) The entire inductor structure is assembled into vertical position using PDMA. Scanning electron micrographs (SEMs) of a 4.5-nH planar coil inductor before and after PDMA are shown in Fig. 13. C. Testing and Measurement Results parameter of the fabricated vertical planar coil inThe ductors is measured from 50 MHz to 4 GHz using an HP 8510C parameter is first measured while the network analyzer. The inductors are on the silicon substrate before PDMA. Next, the inductors are assembled to the vertical position using PDMA measurement is repeated. The parameter of and the inductors with identical designs fabricated on Pyrex glass substrate is also measured for comparison. parameter Fig. 14(a) shows the simulated and measured results of the planar coil inductor shown in Fig. 13. The
(b) Fig. 13. (a) SEM of a planar coil inductor fabricated on the substrate surface before the PDMA assembly. (b) SEM of the same inductor after the PDMA assembly.
test pads feeding the inductors on which probing occurs are de-embedded. Fig. 14(b) shows the simulated and measured parameter results of an inductor with an identical design inductor fabricated on Pyrex glass substrate. The test pads are not de-embedded since the inductor is on a glass substrate and the de-embedment has little effect. The simulated data is obtained by using a compact circuit model for planar coil inductor presented in [7]. The quality factor as a function of frequency extracted from both the simulated and the measured parameter results is plotted in Fig. 15. When the planar coil inductor is on the silicon substrate, it has a peak -factor of 3.5 and a self-resonant frequency of 1 GHz. When the inductor is in the vertical position after the PDMA assembly, the peak -factor increases to 12 and the self-resonant frequency goes well above 4 GHz, which are close to those of the inductor on glass substrate. For the planar coil inductors fabricated on silicon (before assembly), a large insulator capacitance and the substrate resistance dominate at higher frequencies, which leads to a self-resonant frequency of about 1 GHz. Once the inductors are assembled into the vertical position, the substrate loss and capacitance are effectively removed, which leads to the improvement in the inductor performance. Furthermore, for frequencies far below 1 GHz (where substrate effects are negligible), the glass and silicon inductor measurements correspond exactly as expected.
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(b) Fig. 14. (a) A Smith chart showing the simulated and measured S parameter results of the planar coil inductor shown in Fig. 13 before and after PDMA. (b) A Smith chart showing the simulated and measured S parameter results of an inductor with identical design fabricated on glass substrate. The inductance of both inductors is 4.5 nH.
IV. DISCUSSION AND CONCLUSION We have presented the design and modeling of a novel electrostatically actuated high- MEMS tunable capacitor with a large tuning range and a novel high- vertical planar coil MEMS inductor achieved by using a 3-D assembly process—PDMA. The design of the tunable capacitor and the vertical planar coil inductor is compatible with the standard IC fabrication process and is therefore suitable for various RF IC applications. Electromechanical (static and dynamic) and microwave -parameter behaviors of the tunable capacitor have been characterized. The tunable capacitor design keeps the simplicity of a conventional two-parallel-plate configuration, while overcoming its disadvantage of low tuning range. A maximum controllable tuning range of 69.8% at 1 MHz has been obtained experimentally. A component quality factor of about 30 at 5 GHz and a self-resonant frequency beyond 10 GHz has been achieved. Due to the small but finite intrinsic stress of the Permalloy film, the size of the suspended top plate is made smaller than 500 m 500 m. This limits the base capacitance of the tunable capacitor. Increasing the area of the parallel plates can achieve larger capacitance. However, it requires thin-film materials with even smaller internal stress, which is difficult to achieve. A parallel tunable capacitor array
(c) Fig. 15. The quality factor of the planar coil inductor extracted from the simulated and measured S parameters: (a) the inductor on silicon before PDMA, (b) the inductor in vertical position after PDMA, and (c) an inductor with identical design on glass substrate.
Fig. 16. A microscopic picture of an array of four wide-tuning-range tunable capacitors.
[27] is under development to increase the overall capacitance value Fig. 16. The designed vertical planar coil inductors offer two major advantages over conventional on-substrate ones: they occupy
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much smaller substrate space and suffer less substrate and parasitic loss. In this work, oxide is used as the sacrificial material for PDMA. Sometimes oxide is used as the dielectric for IC devices on the same substrate and thus cannot be removed. In this case, the oxide sacrificial layer can be substituted with other materials such as photo resist. In order to facilitate the measurement, the vertical planar coil inductors tested are not strengthened after PDMA. However, the inductor structure can be strengthened after PDMA by using different methods such as Parylene coating to achieve the necessary stiffness and robustness. While the -factor of vertical planar coil inductors can be improved by depositing thicker metal layers during the fabrication, experiments are also being conducted to explore various methods to thicken and strengthen the metal layers of the planar coil inductors while they are in the vertical position after the PDMA assembly.
[15] H. Lakdawala, X. Zhu, H. Luo, S. Santhanam, L. R. Carley, and G. F. Fedder, “Micromachined high- inductors in a 0.18-m copper interconnect low-K dielectric CMOS process,” IEEE J. Solid-State Circuits, vol. 3, Mar. 2002. [16] B. K. Kim, B. K. Ko, and K. Lee, “Monolithic planar RF inductor and waveguide structures on silicon with performance comparable to those in GaAs MMIC,” in IEDM Tech. Dig., 1995, pp. 717–720. [17] J. B. Yoon, C. H. Han, E. Yoon, and C. K. Kim, “High-performance three-dimensional on-chip inductors fabricated by novel micromachining technology for RF MMIC,” in IEEE MTT-S Dig., 1999, pp. 1523–1526. [18] D. Young, V. Malba, J. Ou, A. Bernhardt, and B. Boser, “Monolithic high performance three-dimensional coil inductors for wireless communication applications,” in IEDM Tech. Dig., 1997, pp. 67–70. [19] J. B. Yoon, B. K. Kim, C. H. Han, E. Yoon, K. Lee, and C. K. Kim, “High-performance electroplated solenoid-type integrated inductor (SI2) for RF applications using simple 3D surface micromachining technology,” in IEDM Tech. Dig., 1998, pp. 544–547. [20] J. B. Yoon and C. T. C. Ngyuen, “A high-Q tunable micromachined capacitor with moveable dielectric for RF applications,” Proc. IEEE Electron Devices Meeting, pp. 489–492, 2000. [21] J. B. Yoon, “Micromachined high-Q overhang inductors fabricated on silicon and glass substrates,” in IEDM Tech. Dig., 1999, pp. 753–756. [22] D. J. Sadler, S. Gupta, and C. H. Ahn, “Micromachined spiral inductors using UV-LIGA techniques,” IEEE Trans. Magn., vol. 3, pp. 2897–2899, July 2001. [23] V. M. Lubecek, B. Barber, E. Chan, D. Lopez, M. E. Gross, and P. Gammel, “Self-assembling MEMS variable and fixed RF inductors,” IEEE Trans. Microwave Theory Tech., vol. 49, pp. 2093–2098, Nov. 2001. [24] G. W. Dahlmann, E. M. Yeatman, P. R. Young, I. D. Robertson, and S. Lucyszyn, “MEMS high Q microwave inductors using solder surface tension self-assembly,” in IEEE MTT-S Int. Microwave Symp. Dig., vol. 1, 2001, pp. 329–332. [25] C. T.-C. Nguyen, L. Katehi, and G. Rebeiz, “Micromachined devices for wireless communications,” Proc. IEEE, vol. 86, pp. 1756–1768, 1998. [26] C. T.-C. Nguyen, “Micromechanical resonators for oscillators and filters,” in Proc. IEEE Ultrasonics Symp., 1995, pp. 489–499. [27] J. Zou, C. Liu, J. Schutt-Aine, J. H. Chen, and S. M. Kang, “Development of a wide tuning range MEMS tunable capacitor for wireless communication systems,” in IEDM Tech. Dig., 2000, pp. 403–406. [28] N. Chomnawang and J. B. Lee, “On-chip 3D air core micro-inductor for high-frequency applications using deformation of sacrificial polymer,” in Proc. SPIE Smart Structure and Materials Symp., 2001. [29] J. Zou, C. Liu, and J. E. Schutt-Aine, “Development of a wide-tuningrange two-parallel-plate tunable capacitor for integrated wireless communication systems,” Int. J. RF Microwave Computed Aided Eng., vol. 11, no. 5, pp. 322–329, Sept. 2001. [30] “MEMSCAD 4.5 user guide,” Microcosom Technologies, Inc. [31] E. S. Hung and S. D. Senturia, “Generating efficient dynamica models for microelectromechanical systems from a few finite element simulation runs,” J. Microelectromech. Syst., pp. 280–289, Sept. 1999. [32] “Sonnet em Suite 6.0 user manual,” Sonnet Software, Inc..
ACKNOWLEDGMENT The authors would like to thank the anonymous reviews for helpful comments. REFERENCES [1] D. Young, V. Malba, J. Ou, A. Bernhardt, and B. Boser, “A low-noise RF voltage-controlled oscillator using on-chip high- three dimensional coil inductor and micromachined variable capacitor,” in Tech. Dig. Solid-State Sensors and Actuator Workshop, Hilton Head Island, SC, 1998, pp. 128–131. [2] , “Monolithic high-performance three-dimensional coil inductors for wireless communication applications,” in IEDM Tech. Dig., 1997, pp. 67–70. [3] D. J. Young and B. E. Boser, “A micromachined variable capacitor for monolithic low-noise VCOs,” in Tech. Dig. Solid-State Sensors and Actuator Workshop, Hilton Head Island, SC, 1996, pp. 86–89. [4] A. Dec and K. Suyama, “Micromachined varactors with wide tuning range,” IEEE Trans. Microwave Theory Tech., vol. 46, pp. 2587–2596, Dec. 1998. [5] J. Yao, S. Park, and J. DeNatale, “High tuning ratio MEMS based tunable capacitors for RF communications applications,” in Tech. Dig. Sensors and Actuators Workshop, Hilton Head Island, SC, 1998, pp. 124–127. [6] Z. Feng, H. Zhang, W. Zhang, B. Su, K. Gupta, V. Bright, and Y. Lee, “MEMS-based variable capacitor for millimeter-wave applications,” in Tech. Dig. Solid-State Sensors and Actuators Workshop, Hilton Head Island, SC, 2000, pp. 255–258. [7] J. N. Burghartz, D. C. Edelstein, M. Soyuer, H. A. Ainspan, and K. A. Jerkins, “RF design aspects of spiral inductors on silicon,” IEEE J. SolidState Circuits, vol. 33, pp. 2028–2033, Dec. 1998. [8] C. P. Yue and S. S. Wong, “Physical modeling of spiral inductors on silicon,” IEEE Trans. Electron Devices, vol. 47, pp. 560–568, Mar. 2000. [9] J. N. Burghartz, M. Soyuer, and K. A. Jerkins, “Microwave inductors and capacitors in standard multilevel interconnect silicon technology,” IEEE Trans. Microwave Theory Tech., vol. 44, pp. 100–104, Jan. 1996. [10] K. B. Ashby, I. A. Koullias, W. C. Finley, J. J. Bastek, and S. Moinian, “High inductors for wireless applications in a complementary silicon bipolar process,” IEEE J. Solid-State Circuits, vol. 31, pp. 4–9, Jan. 1996. [11] M. Ozgur, M. Zaghloul, and M. Gaitan, “High backside micromachined CMOS inductors,” in Proc. 1999 IEEE Int. Symp. Circuits and Systems (ISCAS’99), vol. 2, 1999, pp. 577–580. [12] H. Jian, J. L. A. Yeh, Y. Wang, and N. Tien, “Electromagnetically shielded highCMOS compatible copper inductors,” in IEEE Solid-State Circuits Conf. Dig., Feb. 2000, pp. 330–331. [13] C. Y. Chi and G. M. Rebeiz, “Planar millimeter-wave microstrip lumped elements using micro-machining techniques,” in IEEE MTT-S Int. Microwave Symp. Dig., May 1994, pp. 657–660. [14] Y. Sun, Y. H. Van Zejl, J. L. Tauritz, and R. G. F. Baets, “Suspended membrane inductors and capacitors for application in silicon MMIC’s,” in IEEE Microwave and Millimeter Wave Monolithic Circuits Symp. Dig., June 1996, pp. 99–102.
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Jinghong Chen (M’03) received the B.S. and M.S. degrees in engineering physics from Tsinghua University, China, the M.E. degree in electrical engineering from the University of Virginia, Charlottesville, and the Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign. In January 2001, he joined the high-speed communication VLSI research department of Bell Labs Lucent Technologies, Holmdel, NJ, as Member of Technical Staff. Since March 2001, he has been with Agere Systems, formerly the microelectronics group of Lucent Technologies. His current research involves designing high-speed CMOS circuits for communication and signal processing systems. He is also interested in the development of novel numerical algorithms and their applications to the modeling and simulation of microelectromechanical structures and systems.
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Jun Zou received the B.S. degree from the Chongqing University, China, and the M.S. degree from Tsinghua University, China, in 1994 and 1997, respectively. He is currently pursuing the Ph.D. degree in electrical engineering at the University of Illinois at Urbana-Champaign (UIUC). His major research interest lines in the development of novel micromachining technologies and their applications to RF MEMS devices.
Chang Liu (S’92–A’95–M’00–SM’01) received the undergraduate degree from Tsinghua University, Beijing, China. He received the M.S. and Ph.D. degrees from the California Institute of Technology, Pasadena, in 1991 and 1996, respectively. He is currently an Assistant Professor at the University of Illinois at Urbana-Champaign (UIUC), where he directs the Micro Actuators, Sensors, and Systems (MASS) research group. His group is concentrating on the following research areas: microparallel assembly of hinged acceleration-resistant microstructures, polymer MEMS fluidics systems, biomimetic sensors, telemetry, and investigation of microscale bubble generation.
José E. Schutt-Ainé (S’87–M’88–SM’98) received the B.S. degree from the Massachusetts Institute of Technology, Cambridge, in 1981, and M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign (UIUC), in 1984 and 1988, respectively. From 1981 to 1983, he was an Application Engineer at the Hewlett-Packard Microwave Technology Center, Santa Rosa, CA, where he worked on transistor modeling. During his graduate studies at UIUC, he held summer positions at GTE Network Systems in Northlake, IL. In 1989, he joined the faculty of the Electromagnetic Communication Laboratory at UIUC where he is currently an Associate Professor of Electrical and Computer Engineering. His interests include microwave theory and measurements, electromagnetics, high-frequency circuit design, and electronic packaging.
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Sung-Mo (Steve) Kang (S’73–M’75–SM’80–F’90) received Ph.D. degree in electrical engineering from the University of California, Berkeley (UC Berkeley), in 1975. Until 1985, he was with AT&T Bell Laboratories at Murray Hill and Holmdel, NJ, and also served as a faculty member of Rutgers University, Piscataway, NJ. In 1985, he joined the University of Illinois at Urbana-Champaign, where he was Professor of electrical and computer engineering, Computer Science and Research Professor of the Coordinated Science Laboratory and the Beckman Institute for Advanced Science and Technology. He was named the first Charles Marshall Senior University Scholar, an Associate in the Center for Advanced Study, and has served as the Founding Director of Center for ASIC Research and Development at the University of Illinois at Urbana-Champaign. He was a Visiting Professor at the Swiss Federal Institute of Technology, Lausanne, in 1989, the University of Karlsruhe, Germany, in 1997, and at the Technical University of Münich, Germany, in 1998. From August 1995 to December 2000, he served as Head of the Department of Electrical and Computer Engineering. In January 2001, he joined the University of California at Santa Cruz as Dean of Baskin School of Engineering. His current research interests include low-power VLSI design, optimization for performance, reliability, and manufacturability, mixed-signal mixed-technology integrated systems, modeling and simulation of semiconductor devices and circuits, high-speed optoelectronic circuits, and fully optical network systems. He holds six patents, has published over 300 papers, and has coauthored eight books, Design Automation For Timing-Driven Layout Synthesis (Boston, MA: Kluwer, 1992), Hot-Carrier Reliability of MOS VLSI Circuits (Boston, MA: Kluwer, 1993), Physical Design for Multichip Modules (Boston, MA: Kluwer, 1994), and Modeling of Electrical Overstress in Integrated Circuits (Boston, MA: Kluwer, 1994), Electrothermal Analysis of VLSI Systems (Boston, MA: Kluwer, 1999), CMOS Digital Circuits: Analysis and Design (New York: McGraw–Hill, 1995, 2nd ed. 1999), and Computer-Aided Design of Optoelectronic Integrated Circuits and Systems (Englewood Cliffs, NJ: Prentice–Hall, 1996). Dr. Kang is a Fellow of the ACM and AAAS, a Foreign Member of the National Academy of Engineering of Korea, and is listed in Who’s Who in America, Who’s Who in Technology, Who’s Who in Engineering, and Who’s Who in the Midwest. He is a recipient of the Outstanding Alumnus Award in Electrical Engineering, UC Berkeley (2001), IEEE Third Millennium Medal (2000), SRC Technical Excellence Award (1999), IEEE Circuts and Systems (CAS) Society Golden Jubilee Medal (1999), KBS Award in Science and Technology (1998), IEEE CAS Society Technical Achievement Award (1997), Humboldt Research Award for Senior U.S. Scientists (1996), IEEE Graduate Teaching Technical Field Award (1996), IEEE CAS Society Meritorious Service Award (1994), SRC Inventor Recognition Awards (1993, 1996), IEEE CAS Darlington Prize Paper Award (1993), ICCD Best Paper Award (1986), and Myril B. Reed Best Paper Award (1979). He was an IEEE CAS Distinguished Lecturer (1994–1997) and has served as a member of the Board of Governors, Secretary of Treasurer, Administrative Vice President, and 1991 President of the IEEE Circuits and Systems Society. He has also served on the program committees and technical committees of major international conferences that include DAC, ICCAD, ICCD, ISCAS, MCMC, International Conference on VLSI and CAD (ICVC), Asia-Pacific Conference on Circuits and Systems, LEOS Topical Meeting, SPIE OE/LASE Meeting. He has served on the editorial boards of PROCEEDINGS OF THE IEEE, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, International Journal of Circuit Theory and Applications, and Circuits, Signals and Systems. He was the Founding Editor-in-Chief of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.
