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Design Methodology Using Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage Reference Dalton M. Colombo
Gilson I. Wirth
Christian Fayomi
UFRGS PGMICRO Porto Alegre - RS, Brazil (+55) 51 3308-6156
UFRGS PGMICRO Porto Alegre - RS, Brazil (+55) 51 3308-3516
UQAM Wireless Smart Devices Labs Montreal - QC, Canada (+1) 514 987-3000 #1955
[email protected]
[email protected]
[email protected]
Voltage references are essential building blocks in the design of several analog applications, for instance, data converters and biomedical implantable devices. In the current trend, these circuits must generate a constant output voltage, when operating with supply voltage bellow 1 volt and with power consumption of few tens of nW to a few mWs [1].
ABSTRACT This paper presents an analog design methodology, using the selection of inversion coefficient of MOS devices, to design lowvoltage and low-power (LVLP) CMOS voltage references. These circuits often work under subthreshold operation. Hence, there is a demand for analog design methods that optimize the sizing process of transistors working in weak and moderate inversion. The advantage of the presented method – compared with the traditional approach to design circuits – is the reduction of design cycle time and minimization of trial-and-error simulations, if the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with supply voltage of 0.7 V was designed for 0.18-µm CMOS technology.
In another side, the design of such voltage references for commercial purpose becomes even more complicate due to the reduced time-to-market constraints. Accordingly, aiming at reducing the cycle time of the analog design manual process, and enable the designer to explore different design options quickly, several methodologies and tools for automatic and optimized analog design were developed [2]. One methodology that provides better insight leading towards optimized design is the selection of inversion coefficient of MOS devices [3-4]. The inversion coefficient is a numerical measure of MOS inversion, which enables design freely in weak, moderate, and strong inversion. Note that weak and moderate inversions are increasingly important in LVLP design. Using the equations motivated by EKV MOS model, method [3-4] guides the designer towards optimized design.
Categories and Subject Descriptors B.7.0 [Integrated Circuits]: General – advanced.
General Terms Design, Reliability, Experimentation
Keywords
This paper presents a methodology to design low-voltage low power CMOS voltage reference using the selection of inversion coefficient. Using a spreadsheet design tool, drain current, inversion coefficient and channel length choices are mapped into channel width. The proposed method, used as initial design guidance, reduces the design time and minimizes trial-and-error simulations. The circuit used as study case, proposed originally in [5], was designed for 0.18-μm CMOS TSMC technology using BSIM3V3 model with Cadence Design Tools. The text is organized in the following sequence. The Inversion coefficient method is briefly explained in section 2. Section 3 presents the low-voltage and low-power CMOS reference. The simulation results and conclusions are presented respectively in sections 4 and 5.
CMOS Voltage Reference, Analog Design Methodology, Inversion Coefficient, Low-Voltage Low Power Performance.
1. INTRODUCTION The current trend towards low-power and low-voltage (LVLP) design is mainly caused by the growing demand of portable equipments, which must operate for long periods. In addition, the speed and high integration density of recent VLSI systems has increased the heating dissipation to critical limits. Therefore, analog and mixed-signal circuits presented in these applications must operate under LVLP conditions.
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2. INVERSION COEFFICIENT METHODOLOGY The inversion coefficient (IC) provides a numerical representation of the region and level of MOS inversion, and then permitting design freely in weak, moderate, and strong inversion. Weak inversion corresponds to IC < 0.1, moderate inversion
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the channel length modulation phenomenon. The parameter n (substrate factor) is often recognized as the slope factor when transistors are operating in weak inversion.
corresponds to 0.1< IC < 10, and strong inversion corresponds to IC > 10 [4]. Table 1 shows Equations (1) – (5) that describes IC as a function of drain-source current, transistor aspect ratio (S = W/L) and I0 (technology current) [4]. Note that parameters NSUB, γ, μ0, COX can be extracted from BSIM3V3 model provided by TSMC. The calculated values of I0 and n0 for nMOS (respectively pMOS) transistors are 0.587 µA and 1.249 (respectively 0.147 µA and 1.258) μA.
2 I D = (1 2 ) ⋅ μ 0 ⋅ COX ⋅ S ⋅ (VGS − VT ) ⋅ (1 + λ ⋅ VDS ) (13) 2 I D = 2n ⋅ μ 0 ⋅ COX ⋅ S ⋅ U T ⋅ exp[(VGS − VT ) n ⋅ U T ] (14)
Nevertheless, as Equation (6) provides a more conscious choice of the level of MOS inversion than compared with the traditional approach, our methodology uses it. Figure 1 illustrates estimated values of VDSAT and (VGS-VT) for its respective IC, in order to provide comparison between different operation modes (weak/moderate/strong). This estimation was done using equations (9)-(10) for nMOSFET with S = (1 μm/1μm) in the 0.18-μm process. Furthermore, fig. 1 also shows the estimated gm/ID as a function of IC using Equation (8).
Table 1. Expressions for Inversion Coefficient (IC) Equations
IC =
Parameters
ID I0 ⋅ S
(1)
I 0 = 2n0 ⋅ μ 0 ⋅ C OX ⋅ U T2 (2) n0 = 1 +
γ
(3)
2 ψ 0 + VSB
(4) ψ 0 ≈ 2φ F + 4U T φ F = U T ⋅ ln(N SUB ni ) (5)
IC = inversion coefficient, ID = drain-source current, [A] S = Transistor size aspect ratio I0 = technology current, [A] n0 = substrate factor μ0 = low-field mobility, [μA/V2] COX = gate-oxide cap. [fF/μm2] UT = Thermal voltage [mV], ≈ 25.85mV @ 300K γ = body-effect factor, [V1/2] VSB = source bulk voltage, [V] Ψ0 = psi parameter, [V] ΦF = Fermi Potential, [V] NSUB = substrate doping concentration, [cm-3] Ni = silicon intrinsic carrier concentration, [cm-3]
Table 2 shows Equations (6) - (10) that describe respectively, channel width, gate area, transconductance efficiency (gm/ID), drain-source saturation voltage (VDSAT) and effective gate-source voltage (VEFF = VGS-VT) as function of inversion coefficient [4]. Equation (10) approaches respectively: Equation (11) for weak inversion and Equation (12) for strong inversion operation. Figure 1. VDSAT and (VGS-VT) as a function of IC (above), gm/ID as a function of IC (bellow)
Table 2. Expressions for W, W*L, gm/ID, VSAT and VEFF
W = ( L / IC ) ⋅ ( I D / I 0 )
(
(6)
)
W ⋅ L = L / IC ⋅ (I D / I 0 ) 2
g m I D = 1 ⎛⎜ n ⋅ U T ⋅ ⎛⎜ IC + 0.5 IC + 1 ⎞⎟ ⎞⎟ ⎝ ⎠⎠ ⎝ VDSAT = 2U T ⋅ IC + 0.25 + 3U T
(
VEFF = 2n ⋅ U T ⋅ ln e
VEFF = n ⋅ U T ⋅ ln(IC )
(11)
IC
3. LOW VOLTAGE LOW POWER CMOS VOLTAGE REFERENCE
(7)
)
−1
(8)
Traditional Bandgap voltage reference (BGR) provides an output voltage (VREF) close to 1.2 V through the addition of base-emitter voltage (VBE) to a properly scaled Proportional to Absolute Temperature (PTAT) voltage. When the fixed value of VREF generated by this circuit is not compatible with LVLP applications, it must be avoided. Therefore, other circuit topologies were proposed to reduce VREF bellow 1 V. For instance, in [6] a resistive subdivision was used to achieve that objective.
(9) (10)
V EFF = 2n ⋅ U T ⋅ IC (12)
For the LVLP voltage reference presented in this paper works properly, its transistors must operate in weak and moderate inversion, as will be shown in the next section. The traditional equations used to design transistors are given by Equation (13) for strong inversion and Equation (14) for weak inversion operation with drain-source voltage higher than 0.1 V. Parameter λ models
Another way to implement a sum of two voltages with opposite temperature coefficients (TC) is through MOSFETs operating in subthreshold region [7]. Transistors working in weak and moderate inversion are important for LVLP circuits because their low drain-source saturation voltage (as can be seen in fig. 1). In [7], the output voltage is generated through the sum of a properly
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ΔVGS = VGSM 2 − VGSM 4 = n ⋅ U T ⋅ ln (IC M 2 IC M 4 )
scaled thermal voltage (UT) with a properly scaled VGS of a MOSFET.
I R1 = ΔVGS R1
The gate-source voltage of a MOSFET, when biased with a current less than a certain technology-dependent value, decreases with temperature in a quasilinear fashion [8]. The temperature dependence of VGS is given by (15) and (16) [7], where it is considered that the variation of n with temperature is small. Variables KT1 and VOFF are BSIM3v3 parameters for respectively: temperature coefficient of VT and offset voltage in subthreshold region [9].
VGS (T ) ≈ VGS (T0 ) + K G ⋅ [(T T0 ) − 1]
(15)
K G ≅ K T 1 + VGS (T0 ) − VTH (T0 ) − VOFF
(16)
(18) (19)
Making (ICM2/ ICM4) equal to 10 it is possible to provide a good matching between M2 and M4. When n and UT (@ 300K) are respectively around 0.587 and 25.85 mV, the estimated value of ∆VGS is 74.26 mV. Therefore, after the chosen of IR1 based on the power-consumption requirement, the resistance R1 can be found. In our design, It is assumed IR1 = 200 nA, what requires R1 = 371.29 kΩ. As mentioned above, M2 and M4 must operate in week inversion for Equation (17) is valid. Therefore, using Equation (6) and choosing a value of IC less than 0.1, channels width of M2 and M4 are estimated.
The voltage reference used as a case study in our work was previously proposed in [5], and works in same approach: it generates VREF by means of a balanced summing of VGS and UT. The circuit is shown in figure 2 and it is composed by tree sub circuits: A) PTAT current generator, B) VGS current generator and C) current adder. Capacitor C1 is used only for compensation purposes. The original circuit works under 1-V of VDD, but the aim of our approach is the nominal operation under 0.7 V. Moreover, our circuit is designed to be robust against VDD fluctuations in the range of 0.6 to 1.8 V.
The dimensions of M1, M3 and M5 were considered equal in order to provide a good layout matching. Transistors in moderate inversion operation have less thermal noise and silicon area than compared with week inversion operation - for a given ID current [3]. Hence, M1, M3 and M5 should operate in moderate inversion with the aim of reducing thermal noise in VREF. The moderatevalues of VDSAT of these transistors, when working in moderate inversion, are proper for our supply voltage requirement (0.6 V). Consequently, for M1, M3 and M5, it was chosen IC values between 0.1 and 10. In addition, when the impact of process variability and flicker noise on the output voltage is inversely proportional to the transistor area [3], the channel length of transistors M1–M5 were chosen to be around 10 times the minimum value permitted by the technology used. After simulation, it was verified that the correct value of ∆VGS is 67.07 mV; and thus, the correct value of R1 is 335.3 kΩ. The error in calculation provided by equation (18) is around 10%. It is valid to add that the simulated temperature coefficient of ∆VGS in the temperature range of -40 to 120 ºC is around 0.163 mV/ ºC. Table 3 presents the design choices (ID, IC and L) for each transistor, and the estimated values of W, W*L and gmE using equations (6-8). It is also presented the simulated values of gm, in order to verify how accurate is our transistor sizing process compared with simulated results.
Figure 2. Simulated voltage reference used as a case study
Table 3. Transistor sizes, estimated and simulated values of gm (sub-circuit A)
Our design methodology, using equations based on inversion coefficient, provides a step-by-step design process that reduces the design time.
Devic e M2 M4 M1,3,5 Devic e
3.1 PTAT Current Generator The sub circuit A is a classical supply independent current source, which the current in R1 (IR1) is defined by the difference between gate-source voltage of M2 and M4 (∆VGS), and the resistance R1. Using equation (14), one can show that ∆VGS between M2 and M4 is described by equation (17), if body effect is neglected and these devices are in weak inversion operation.
M2 M4 M1,3,5
Using (11), Equation (17) can be expressed in terms of IC, as given by (18). Current IR1, described by (19), is proportional to UT, what means a positive temperature coefficient.
ΔVGS = VGSM 2 − VGSM 4 = n ⋅ U T ⋅ ln (S M 4 S M 2 )
(17)
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Design Choices ID IC (nA) 200 0.05 200 0.005 200 0.25 Estimated Simulated gmE (µS) gmS (µS) 5.75 6.07 5.02
4.92 5.73 4.40
Designed Sizes W W*L (µm) (µm2) 13.5 27 135 270 16.3 48.9 Error (gmE-gmS) (%)
L (µm) 2 2 3
14.4 5.6 12.4
3.2 VGS Current Generator
3.3 Current Adder
The sub-circuit B is responsible to generate a current with negative TC. Due to the feedback loop presented in this circuit, IR2 is defined by equation (20), where the bias current of M9 is a copy of IR1 (≈200 nA) through M5. Using Equation (11), it is possible to rewrite Equation (20) as Equation (21), as a function of IC.
I R 2 = VGSM 9 R2
The third circuit is a simple current adder with resistor R3 that converts current to voltage. The generated output voltage is described by (22). Using Equations (19) and (20), Equation (22) can be rewritten as (23). Note that IM6 is half of IR2.
VREF = (I M 10 + I M 11 ) ⋅ R3 =
[(S M 10
(20)
I R 2 = [n ⋅ U T ⋅ ln( IC M 9 ) − VT ] R2
⎡(S M 10 S M 6 ) ⋅ (VGSM 9 2 ⋅ R2 ) + ⎤ VREF = ⎢ ⎥ ⋅ R3 ⎣(S M 11 S M 3 ) ⋅ (ΔVGS R1 ) ⎦
(21)
In order to reduce power consumption and the required value of R2 (for a given current), M9 must operate in weak inversion, and consequently to present low value of VGS. In our case, we define M9 operating in deep weak inversion with IC equal to 0.009, what corresponds to VGS around 240.3 mV.
VREF = (1 / 4 ) ⋅ VGSM 9 + (1 / 2 ) ⋅ (S M 11 S M 3 ) ⋅ ΔVGS
0 = (1 / 4) ⋅ TCVGSM 9 + (1 / 2 ) ⋅ (S M 11 S M 3 ) ⋅ TC ΔVGS
Table 4. Transistor sizes, estimated and simulated values of gm (sub-circuit B) IC 1 1 0.1 0.009 Simulated gmS (µS) 6.52 13.04 8.34 5.60
(24)
To estimate the required value of (SM11/SM3) for temperature compensation, one can take the derivative with respect to temperature of equation (24). Making (dVREF/dt) = zero, one can show that (SM11/SM3) can be found through equation (25). When simulated values of TCVGSM9 and TC∆VGS are respectively -0.93 mV/ ºC and 0.163 mV/ ºC, (SM11/SM3) is found to be around 2.85; what corresponds to SM11 = (46.5/3).
Table 4 presents the design choices (ID, IC and L) for each transistor, and the estimated values of W, W*L and gmE using equations (6-8). It is also presented the simulated value of gm for comparison.
ID (nA) 358.5 717 358.5 200 Estimated gmE (µS) 6.99 13.95 9.93 6.03
(23)
In order to save silicon area, R3 is defined to be half of R2 (167.65kΩ). Moreover, (SM10/SM6) is set to be 1, with the aim of keeping low power consumption. Therefore, (23) can be rewritten as (24). Note that VREF is a function of IC because VGSM9 and ∆VGS are defined respectively by Equations (11) and (18).
Transistors M6 – M8, should operate in moderation inversion in order to reduce the thermal noise and silicon area. Hence, IC for these devices is chosen between 0.1 and 1. Current of devices M6 and M8, which is derived from M9 and R2, was designed to be half of IR2 with intention of reducing power consumption.
Devic e M6 M7 M8 M9 Devic e M6 M7 M8 M9
(22)
As can be seen in (23), the temperature compensation of VREF is provided by a proper sizing of the transistors. Note that R3 does not affect the temperature compensation, and for this reason, VREF can be adjusted to a desired level simply adjusting R3.
From the value of VGSM9 @200nA, it is possible to design R2. Again, it is the tradeoff between resistor area versus power consumption. We defined R2 equal to R1 with the purpose of providing a good resistor layout matching. For R2= 335.3 kΩ, current IR2 is around 717 nA.
Design Choices
S M 6 ) ⋅ I M 6 + (S M 11 S M 3 ) ⋅ I R1 ] ⋅ R3
(25)
In summary, the current mirror composed by M10 and M11 is sized to allow respectively, power consumption reduction and properly temperature compensation. These transistors should also operate in moderate inversion. Table 5 presents estimated values of W, W*L and gmE using Equations (6-8) for corresponding design choices.
Designed Sizes L (µm) 3 3 3 3
W W*L (µm) (µm2) 7.31 21.8 14.6 43.8 10.15 54.4 120 360 Error (gmE-gmS) (%) 6.7 6.5 16 7.3
Table 5. Transistor sizes, estimated and simulated values of gm (sub-circuit C) Devic e M10 M11 Devic e M10 M11
It is also important to estimate the temperature coefficient of VGSM9, before designing sub-circuit C. Using equations (15-16), TC of VGSM9 is estimated to be -1.04 mV/ ºC; while the simulation shows TC equal to -0.93 mV/ ºC - what means an error of 7%.
Design Choices ID IC (nA) 0.359 1 0.620 0.25 Estimated Simulated gmE (µS) gmS (µS) 6.97 6.53 15.50 13.61
Designed Sizes W W*L (µm) (µm2) 7.3 21.9 46.5 139.5 Error (gmE-gmS) (%) 6.3 12.2
L (µm) 3 3
All equations presented in this work were implement in an Excel sheet, what makes fast the design (and the redesign) process.
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Finally, it is also worth adding that due to the high values of resistance needed to generate currents lower than 1 µA, the resistors would be made of high-resistance (without silicide) PPoly material available in the used technology. The compensation capacitor C1 was designed to be 10 pF.
4. SIMULATION RESULTS After sizing all transistors using Equations (1-12) and (15-25), the voltage reference was simulated and the main performance parameters are presented in this section. The voltage reference variation caused by temperature variation (ΔVREF_TEMP) was measured in the range of -40 to 120 °C. The output voltage variation caused by VDD fluctuation (ΔVREF_VDD) was measured considering VDD variation of 0.6 to 0.8 V. In addition, the output noise (ΔVREF_NOISE) and the temperature coefficient (TC), defined as TC = VREF (T0)-1*(ΔVREF_TEMP/ΔT), were also measured. Figure 3 illustrates VREF as a function of temperature, and the temperature performance for different values of R3. As already explained, VREF can be adjust to desired level simply adjusting value of R3, without damage to TC. The value of ΔVREF_TEMP is 2.8 mV what represents 2% variation in the temperature range.
Figure 4. Simulated PSRR (above) and VREF as a function of VDD (bellow) Table 6. Simulated Performance Parameters VREF (mV) 156.2 ΔVREF_NOISE (μV) 96
TC (ppm/°C) 112 PSR (dB) 40.3
ΔVREF_TEMP (mV) 2.8 Isupply (μA) 2.6
ΔT (°C) 160 VDD (V) 0.7
ΔVREF_VDD (mV) 2.1 P (μW) 1.82
In order to have estimation of the impact of fabrication process on the temperature performance of VREF, the circuit was also simulated using corner models. The MOSFET corner models used in this simulation were: TT (Typical-Typical), SS (Slow-Slow), FF (Fast-Fast), SF (Slow-Fast) and FS (Fast-Slow). The resistor and BJT corner models used were: TT, SS and FF.
R3 = 335K R3 = 250K
Figure 5 illustrates the simulation of VREF as a function of temperature using corner models. Curves ‘a’ and ‘b’ represent, respectively, the cases where VREF has the highest and lowest values. Curve ‘a’ was obtained using the following models: SF (MOS), FF (Resistor) and FF (BJT); while curve ‘b’ has used FS (MOS), SS (Resistor) and SS (BJT) models. The variation of VREF @ 27 °C between the last two cases is 15.7 mV. The worst estimated temperature performance (ΔVREF_TEMP) among all simulated cases is equal to 3.5 mV, what represents TC equal to 144 ppm/°C. Table 7 summaries the main simulation results using corner models. Because mismatch is not taken into account in the former analysis, Monte Carlo simulation is still required to have a complete estimation of fabrication process effects.
R3 = 168K
Figure 3. Simulated VREF as a function of temperature for nominal R3 (above) and three different values (bellow) Figure 4 shows the PSR performance when a load capacitance of 5 pF is connected at the output node. It is also shown VREF as a function of VDD. The circuit provides 40.3 dB (@ 1 kHz) of power supply rejection, and properly works until VDD equal 0.6 volts. Table 6 presents all results discussed so far.
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6. ACKNOWLEDGMENTS The authors would like to acknowledge the financial support from the Emerging Leaders in the Americas Program (ELAP) provided by the government of Canada, Natural Sciences and Engineering Research Council of Canada (NSERC), ReSMIQ, and the Brazilian Funding Agencies CNPq and CAPES.
7. REFERENCES [1] Fayomi, C. J. B. and Stratz, S. J. 2006. Novel Approach to Low-Voltage Low-Power Bandgap Reference in Standard CMOS Process. In Proc of the 13th IEEE International Conference on Electronics, Circuits and Systems (Nice, France, December 10-13, 2006). ICECS’06. pp. 208-211. DOI: http://dx.doi.org/10.1109/ICECS.2006.379762.
Figure 5. Simulated VREF as a function of temperature using corner models Table 7. Simulation of VREF and ΔVREF_TEMP using corner models MOS: TT SS FF SF Model RES: TT SS FF FF BJT: TT SS FF FF 156.2 160.5 152.4 164.4 VREF (mV) 2.8 3.2 3.5 3.5 ΔVREF_TEMP (mV) 112 124 144 133 TC (ppm/°C)
[2] Kundu, A. L. et al. 2008. A Methodology for efficient design of analog circuits using an automated simulation based synthesis tool. In Proc of the IEEE International Symposium on Circuits and Systems (Seattle, USA, May 18-21, 2008). ISCAS’2008. pp. 732 – 735. DOI: http://dx.doi.org/10.1109/ISCAS.2008.4541522.
FS SS SS 148.7 3.0 126
[3] Binkley, D. M. 2008. Analog CMOS Design, Tradeoffs and Optimization. John Wiley and Sons. 2008. [4] Binkely, D. M. 2007. Tradeoffs and optimization in analog CMOS design. In Proc of the IEEE 14th Int. Conf. Mixed Design of Integrated Circuits and Systems (Ciechocinek, Poland, June 21-23, 2007). MIXDES’07. 47-60. DOI: http://dx.doi.org/10.1109/MIXDES.2007.4286119.
The methodology presented in our work is suitable not only for the circuit presented in fig. 2, but for any voltage reference that must operate under low-voltage and low-power requirements using subthreshold MOSFETs. The advantage of proposed methodology if compared to the traditional approach - Equations (13-14) -, is the conscious choice of the level of MOS inversion, which allows a quick estimation, with reasonable accuracy, of transistor width for a given set of design choices (Current, Channel length and IC). The estimation provided by Equations (112) and (15-25) differs from the simulated results by less than 20%.
[5] Jianping, W. et al. 2005. A Novel Low-Voltage Low-Power CMOS Voltage Reference Based on Subthreshold MOSFETs. In Proc of the 6th IEEE Int. Conf. on ASIC (Shangai, China, October 24-27, 2005). ASICON 2005. 369373. DOI: http://dx.doi.org/10.1109/ICASIC.2005.1611340. [6] Banba, H. et al. 1999. A CMOS Bandgap Reference Circuit with sub-1-V operation. IEEE Journal of Solid-State Circuits (May 1999). Vol. 34, No. 5, pp. 670-674. DOI: http://dx.doi.org/10.1109/4.760378.
The demand for analog design methods that drive quickly the process of sizing transistors in weak and moderate inversion are increasingly important for recent LVLP applications due to low drain-source saturation voltage. For 0.18-μm technology, VDSAT values are respectively around: 100 mV for weak inversion, and between 100 to 240 mV for moderate inversion.
[7] Giustolisi, G. et al. A Low-Voltage Low Power Voltage Reference Based on Subthreshold MOSFETs. IEEE Journal of Solid-State Circuits (Jan. 2003). Vol. 38, No.1, pp. 151154. DOI: http://dx.doi.org/10.1109/JSSC.2002.806266. [8] Filanovsky, I. M. and Allam, A. Mutual compensation of mobility and threshold voltage temperature effects with application in CMOS Circuits. IEEE Transactions on Circuits and Systems (July 2001). Vol. 48, pp. 876-884. DOI: http://dx.doi.org/10.1109/81.933328.
5. CONCLUSIONS The proposed methodology, used as initial design guidance, reduces the design cycle time of low-voltage and low-power voltage references based on subthreshold operation. The inversion coefficient applied in the methodology enables design freely in weak, moderate and strong inversion, what leads to an optimization of the transistor sizing process. The difference between simulated results and estimation provided by proposed equations differs by less than 20%. Simulations to evaluate a candidate circuit design over process variation and layout parasitics are still required. The voltage reference used as a case study works under a 0.7 V supply voltage while consuming 1.82 μW.
[9] Liu, W., Jin, X., Xi, X., et al. 2005. BSIM3v3.3 MOSFET Model – User’s Manual. Retrieved June 02, 2010 from http://www-device.eecs.berkeley.edu/~bsim3.
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Gilson I. Wirth
Christian Fayomi
UFRGS PGMICRO Porto Alegre - RS, Brazil (+55) 51 3308-6156
UFRGS PGMICRO Porto Alegre - RS, Brazil (+55) 51 3308-3516
UQAM Wireless Smart Devices Labs Montreal - QC, Canada (+1) 514 987-3000 #1955
[email protected]
[email protected]
[email protected]
Voltage references are essential building blocks in the design of several analog applications, for instance, data converters and biomedical implantable devices. In the current trend, these circuits must generate a constant output voltage, when operating with supply voltage bellow 1 volt and with power consumption of few tens of nW to a few mWs [1].
ABSTRACT This paper presents an analog design methodology, using the selection of inversion coefficient of MOS devices, to design lowvoltage and low-power (LVLP) CMOS voltage references. These circuits often work under subthreshold operation. Hence, there is a demand for analog design methods that optimize the sizing process of transistors working in weak and moderate inversion. The advantage of the presented method – compared with the traditional approach to design circuits – is the reduction of design cycle time and minimization of trial-and-error simulations, if the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with supply voltage of 0.7 V was designed for 0.18-µm CMOS technology.
In another side, the design of such voltage references for commercial purpose becomes even more complicate due to the reduced time-to-market constraints. Accordingly, aiming at reducing the cycle time of the analog design manual process, and enable the designer to explore different design options quickly, several methodologies and tools for automatic and optimized analog design were developed [2]. One methodology that provides better insight leading towards optimized design is the selection of inversion coefficient of MOS devices [3-4]. The inversion coefficient is a numerical measure of MOS inversion, which enables design freely in weak, moderate, and strong inversion. Note that weak and moderate inversions are increasingly important in LVLP design. Using the equations motivated by EKV MOS model, method [3-4] guides the designer towards optimized design.
Categories and Subject Descriptors B.7.0 [Integrated Circuits]: General – advanced.
General Terms Design, Reliability, Experimentation
Keywords
This paper presents a methodology to design low-voltage low power CMOS voltage reference using the selection of inversion coefficient. Using a spreadsheet design tool, drain current, inversion coefficient and channel length choices are mapped into channel width. The proposed method, used as initial design guidance, reduces the design time and minimizes trial-and-error simulations. The circuit used as study case, proposed originally in [5], was designed for 0.18-μm CMOS TSMC technology using BSIM3V3 model with Cadence Design Tools. The text is organized in the following sequence. The Inversion coefficient method is briefly explained in section 2. Section 3 presents the low-voltage and low-power CMOS reference. The simulation results and conclusions are presented respectively in sections 4 and 5.
CMOS Voltage Reference, Analog Design Methodology, Inversion Coefficient, Low-Voltage Low Power Performance.
1. INTRODUCTION The current trend towards low-power and low-voltage (LVLP) design is mainly caused by the growing demand of portable equipments, which must operate for long periods. In addition, the speed and high integration density of recent VLSI systems has increased the heating dissipation to critical limits. Therefore, analog and mixed-signal circuits presented in these applications must operate under LVLP conditions.
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. SBCCI’10, September 6–9, 2010, São Paulo, SP, Brazil. Copyright 2010 ACM 978-1-4503-0152-7/10/09...$10.00.
2. INVERSION COEFFICIENT METHODOLOGY The inversion coefficient (IC) provides a numerical representation of the region and level of MOS inversion, and then permitting design freely in weak, moderate, and strong inversion. Weak inversion corresponds to IC < 0.1, moderate inversion
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the channel length modulation phenomenon. The parameter n (substrate factor) is often recognized as the slope factor when transistors are operating in weak inversion.
corresponds to 0.1< IC < 10, and strong inversion corresponds to IC > 10 [4]. Table 1 shows Equations (1) – (5) that describes IC as a function of drain-source current, transistor aspect ratio (S = W/L) and I0 (technology current) [4]. Note that parameters NSUB, γ, μ0, COX can be extracted from BSIM3V3 model provided by TSMC. The calculated values of I0 and n0 for nMOS (respectively pMOS) transistors are 0.587 µA and 1.249 (respectively 0.147 µA and 1.258) μA.
2 I D = (1 2 ) ⋅ μ 0 ⋅ COX ⋅ S ⋅ (VGS − VT ) ⋅ (1 + λ ⋅ VDS ) (13) 2 I D = 2n ⋅ μ 0 ⋅ COX ⋅ S ⋅ U T ⋅ exp[(VGS − VT ) n ⋅ U T ] (14)
Nevertheless, as Equation (6) provides a more conscious choice of the level of MOS inversion than compared with the traditional approach, our methodology uses it. Figure 1 illustrates estimated values of VDSAT and (VGS-VT) for its respective IC, in order to provide comparison between different operation modes (weak/moderate/strong). This estimation was done using equations (9)-(10) for nMOSFET with S = (1 μm/1μm) in the 0.18-μm process. Furthermore, fig. 1 also shows the estimated gm/ID as a function of IC using Equation (8).
Table 1. Expressions for Inversion Coefficient (IC) Equations
IC =
Parameters
ID I0 ⋅ S
(1)
I 0 = 2n0 ⋅ μ 0 ⋅ C OX ⋅ U T2 (2) n0 = 1 +
γ
(3)
2 ψ 0 + VSB
(4) ψ 0 ≈ 2φ F + 4U T φ F = U T ⋅ ln(N SUB ni ) (5)
IC = inversion coefficient, ID = drain-source current, [A] S = Transistor size aspect ratio I0 = technology current, [A] n0 = substrate factor μ0 = low-field mobility, [μA/V2] COX = gate-oxide cap. [fF/μm2] UT = Thermal voltage [mV], ≈ 25.85mV @ 300K γ = body-effect factor, [V1/2] VSB = source bulk voltage, [V] Ψ0 = psi parameter, [V] ΦF = Fermi Potential, [V] NSUB = substrate doping concentration, [cm-3] Ni = silicon intrinsic carrier concentration, [cm-3]
Table 2 shows Equations (6) - (10) that describe respectively, channel width, gate area, transconductance efficiency (gm/ID), drain-source saturation voltage (VDSAT) and effective gate-source voltage (VEFF = VGS-VT) as function of inversion coefficient [4]. Equation (10) approaches respectively: Equation (11) for weak inversion and Equation (12) for strong inversion operation. Figure 1. VDSAT and (VGS-VT) as a function of IC (above), gm/ID as a function of IC (bellow)
Table 2. Expressions for W, W*L, gm/ID, VSAT and VEFF
W = ( L / IC ) ⋅ ( I D / I 0 )
(
(6)
)
W ⋅ L = L / IC ⋅ (I D / I 0 ) 2
g m I D = 1 ⎛⎜ n ⋅ U T ⋅ ⎛⎜ IC + 0.5 IC + 1 ⎞⎟ ⎞⎟ ⎝ ⎠⎠ ⎝ VDSAT = 2U T ⋅ IC + 0.25 + 3U T
(
VEFF = 2n ⋅ U T ⋅ ln e
VEFF = n ⋅ U T ⋅ ln(IC )
(11)
IC
3. LOW VOLTAGE LOW POWER CMOS VOLTAGE REFERENCE
(7)
)
−1
(8)
Traditional Bandgap voltage reference (BGR) provides an output voltage (VREF) close to 1.2 V through the addition of base-emitter voltage (VBE) to a properly scaled Proportional to Absolute Temperature (PTAT) voltage. When the fixed value of VREF generated by this circuit is not compatible with LVLP applications, it must be avoided. Therefore, other circuit topologies were proposed to reduce VREF bellow 1 V. For instance, in [6] a resistive subdivision was used to achieve that objective.
(9) (10)
V EFF = 2n ⋅ U T ⋅ IC (12)
For the LVLP voltage reference presented in this paper works properly, its transistors must operate in weak and moderate inversion, as will be shown in the next section. The traditional equations used to design transistors are given by Equation (13) for strong inversion and Equation (14) for weak inversion operation with drain-source voltage higher than 0.1 V. Parameter λ models
Another way to implement a sum of two voltages with opposite temperature coefficients (TC) is through MOSFETs operating in subthreshold region [7]. Transistors working in weak and moderate inversion are important for LVLP circuits because their low drain-source saturation voltage (as can be seen in fig. 1). In [7], the output voltage is generated through the sum of a properly
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ΔVGS = VGSM 2 − VGSM 4 = n ⋅ U T ⋅ ln (IC M 2 IC M 4 )
scaled thermal voltage (UT) with a properly scaled VGS of a MOSFET.
I R1 = ΔVGS R1
The gate-source voltage of a MOSFET, when biased with a current less than a certain technology-dependent value, decreases with temperature in a quasilinear fashion [8]. The temperature dependence of VGS is given by (15) and (16) [7], where it is considered that the variation of n with temperature is small. Variables KT1 and VOFF are BSIM3v3 parameters for respectively: temperature coefficient of VT and offset voltage in subthreshold region [9].
VGS (T ) ≈ VGS (T0 ) + K G ⋅ [(T T0 ) − 1]
(15)
K G ≅ K T 1 + VGS (T0 ) − VTH (T0 ) − VOFF
(16)
(18) (19)
Making (ICM2/ ICM4) equal to 10 it is possible to provide a good matching between M2 and M4. When n and UT (@ 300K) are respectively around 0.587 and 25.85 mV, the estimated value of ∆VGS is 74.26 mV. Therefore, after the chosen of IR1 based on the power-consumption requirement, the resistance R1 can be found. In our design, It is assumed IR1 = 200 nA, what requires R1 = 371.29 kΩ. As mentioned above, M2 and M4 must operate in week inversion for Equation (17) is valid. Therefore, using Equation (6) and choosing a value of IC less than 0.1, channels width of M2 and M4 are estimated.
The voltage reference used as a case study in our work was previously proposed in [5], and works in same approach: it generates VREF by means of a balanced summing of VGS and UT. The circuit is shown in figure 2 and it is composed by tree sub circuits: A) PTAT current generator, B) VGS current generator and C) current adder. Capacitor C1 is used only for compensation purposes. The original circuit works under 1-V of VDD, but the aim of our approach is the nominal operation under 0.7 V. Moreover, our circuit is designed to be robust against VDD fluctuations in the range of 0.6 to 1.8 V.
The dimensions of M1, M3 and M5 were considered equal in order to provide a good layout matching. Transistors in moderate inversion operation have less thermal noise and silicon area than compared with week inversion operation - for a given ID current [3]. Hence, M1, M3 and M5 should operate in moderate inversion with the aim of reducing thermal noise in VREF. The moderatevalues of VDSAT of these transistors, when working in moderate inversion, are proper for our supply voltage requirement (0.6 V). Consequently, for M1, M3 and M5, it was chosen IC values between 0.1 and 10. In addition, when the impact of process variability and flicker noise on the output voltage is inversely proportional to the transistor area [3], the channel length of transistors M1–M5 were chosen to be around 10 times the minimum value permitted by the technology used. After simulation, it was verified that the correct value of ∆VGS is 67.07 mV; and thus, the correct value of R1 is 335.3 kΩ. The error in calculation provided by equation (18) is around 10%. It is valid to add that the simulated temperature coefficient of ∆VGS in the temperature range of -40 to 120 ºC is around 0.163 mV/ ºC. Table 3 presents the design choices (ID, IC and L) for each transistor, and the estimated values of W, W*L and gmE using equations (6-8). It is also presented the simulated values of gm, in order to verify how accurate is our transistor sizing process compared with simulated results.
Figure 2. Simulated voltage reference used as a case study
Table 3. Transistor sizes, estimated and simulated values of gm (sub-circuit A)
Our design methodology, using equations based on inversion coefficient, provides a step-by-step design process that reduces the design time.
Devic e M2 M4 M1,3,5 Devic e
3.1 PTAT Current Generator The sub circuit A is a classical supply independent current source, which the current in R1 (IR1) is defined by the difference between gate-source voltage of M2 and M4 (∆VGS), and the resistance R1. Using equation (14), one can show that ∆VGS between M2 and M4 is described by equation (17), if body effect is neglected and these devices are in weak inversion operation.
M2 M4 M1,3,5
Using (11), Equation (17) can be expressed in terms of IC, as given by (18). Current IR1, described by (19), is proportional to UT, what means a positive temperature coefficient.
ΔVGS = VGSM 2 − VGSM 4 = n ⋅ U T ⋅ ln (S M 4 S M 2 )
(17)
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Design Choices ID IC (nA) 200 0.05 200 0.005 200 0.25 Estimated Simulated gmE (µS) gmS (µS) 5.75 6.07 5.02
4.92 5.73 4.40
Designed Sizes W W*L (µm) (µm2) 13.5 27 135 270 16.3 48.9 Error (gmE-gmS) (%)
L (µm) 2 2 3
14.4 5.6 12.4
3.2 VGS Current Generator
3.3 Current Adder
The sub-circuit B is responsible to generate a current with negative TC. Due to the feedback loop presented in this circuit, IR2 is defined by equation (20), where the bias current of M9 is a copy of IR1 (≈200 nA) through M5. Using Equation (11), it is possible to rewrite Equation (20) as Equation (21), as a function of IC.
I R 2 = VGSM 9 R2
The third circuit is a simple current adder with resistor R3 that converts current to voltage. The generated output voltage is described by (22). Using Equations (19) and (20), Equation (22) can be rewritten as (23). Note that IM6 is half of IR2.
VREF = (I M 10 + I M 11 ) ⋅ R3 =
[(S M 10
(20)
I R 2 = [n ⋅ U T ⋅ ln( IC M 9 ) − VT ] R2
⎡(S M 10 S M 6 ) ⋅ (VGSM 9 2 ⋅ R2 ) + ⎤ VREF = ⎢ ⎥ ⋅ R3 ⎣(S M 11 S M 3 ) ⋅ (ΔVGS R1 ) ⎦
(21)
In order to reduce power consumption and the required value of R2 (for a given current), M9 must operate in weak inversion, and consequently to present low value of VGS. In our case, we define M9 operating in deep weak inversion with IC equal to 0.009, what corresponds to VGS around 240.3 mV.
VREF = (1 / 4 ) ⋅ VGSM 9 + (1 / 2 ) ⋅ (S M 11 S M 3 ) ⋅ ΔVGS
0 = (1 / 4) ⋅ TCVGSM 9 + (1 / 2 ) ⋅ (S M 11 S M 3 ) ⋅ TC ΔVGS
Table 4. Transistor sizes, estimated and simulated values of gm (sub-circuit B) IC 1 1 0.1 0.009 Simulated gmS (µS) 6.52 13.04 8.34 5.60
(24)
To estimate the required value of (SM11/SM3) for temperature compensation, one can take the derivative with respect to temperature of equation (24). Making (dVREF/dt) = zero, one can show that (SM11/SM3) can be found through equation (25). When simulated values of TCVGSM9 and TC∆VGS are respectively -0.93 mV/ ºC and 0.163 mV/ ºC, (SM11/SM3) is found to be around 2.85; what corresponds to SM11 = (46.5/3).
Table 4 presents the design choices (ID, IC and L) for each transistor, and the estimated values of W, W*L and gmE using equations (6-8). It is also presented the simulated value of gm for comparison.
ID (nA) 358.5 717 358.5 200 Estimated gmE (µS) 6.99 13.95 9.93 6.03
(23)
In order to save silicon area, R3 is defined to be half of R2 (167.65kΩ). Moreover, (SM10/SM6) is set to be 1, with the aim of keeping low power consumption. Therefore, (23) can be rewritten as (24). Note that VREF is a function of IC because VGSM9 and ∆VGS are defined respectively by Equations (11) and (18).
Transistors M6 – M8, should operate in moderation inversion in order to reduce the thermal noise and silicon area. Hence, IC for these devices is chosen between 0.1 and 1. Current of devices M6 and M8, which is derived from M9 and R2, was designed to be half of IR2 with intention of reducing power consumption.
Devic e M6 M7 M8 M9 Devic e M6 M7 M8 M9
(22)
As can be seen in (23), the temperature compensation of VREF is provided by a proper sizing of the transistors. Note that R3 does not affect the temperature compensation, and for this reason, VREF can be adjusted to a desired level simply adjusting R3.
From the value of VGSM9 @200nA, it is possible to design R2. Again, it is the tradeoff between resistor area versus power consumption. We defined R2 equal to R1 with the purpose of providing a good resistor layout matching. For R2= 335.3 kΩ, current IR2 is around 717 nA.
Design Choices
S M 6 ) ⋅ I M 6 + (S M 11 S M 3 ) ⋅ I R1 ] ⋅ R3
(25)
In summary, the current mirror composed by M10 and M11 is sized to allow respectively, power consumption reduction and properly temperature compensation. These transistors should also operate in moderate inversion. Table 5 presents estimated values of W, W*L and gmE using Equations (6-8) for corresponding design choices.
Designed Sizes L (µm) 3 3 3 3
W W*L (µm) (µm2) 7.31 21.8 14.6 43.8 10.15 54.4 120 360 Error (gmE-gmS) (%) 6.7 6.5 16 7.3
Table 5. Transistor sizes, estimated and simulated values of gm (sub-circuit C) Devic e M10 M11 Devic e M10 M11
It is also important to estimate the temperature coefficient of VGSM9, before designing sub-circuit C. Using equations (15-16), TC of VGSM9 is estimated to be -1.04 mV/ ºC; while the simulation shows TC equal to -0.93 mV/ ºC - what means an error of 7%.
Design Choices ID IC (nA) 0.359 1 0.620 0.25 Estimated Simulated gmE (µS) gmS (µS) 6.97 6.53 15.50 13.61
Designed Sizes W W*L (µm) (µm2) 7.3 21.9 46.5 139.5 Error (gmE-gmS) (%) 6.3 12.2
L (µm) 3 3
All equations presented in this work were implement in an Excel sheet, what makes fast the design (and the redesign) process.
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Finally, it is also worth adding that due to the high values of resistance needed to generate currents lower than 1 µA, the resistors would be made of high-resistance (without silicide) PPoly material available in the used technology. The compensation capacitor C1 was designed to be 10 pF.
4. SIMULATION RESULTS After sizing all transistors using Equations (1-12) and (15-25), the voltage reference was simulated and the main performance parameters are presented in this section. The voltage reference variation caused by temperature variation (ΔVREF_TEMP) was measured in the range of -40 to 120 °C. The output voltage variation caused by VDD fluctuation (ΔVREF_VDD) was measured considering VDD variation of 0.6 to 0.8 V. In addition, the output noise (ΔVREF_NOISE) and the temperature coefficient (TC), defined as TC = VREF (T0)-1*(ΔVREF_TEMP/ΔT), were also measured. Figure 3 illustrates VREF as a function of temperature, and the temperature performance for different values of R3. As already explained, VREF can be adjust to desired level simply adjusting value of R3, without damage to TC. The value of ΔVREF_TEMP is 2.8 mV what represents 2% variation in the temperature range.
Figure 4. Simulated PSRR (above) and VREF as a function of VDD (bellow) Table 6. Simulated Performance Parameters VREF (mV) 156.2 ΔVREF_NOISE (μV) 96
TC (ppm/°C) 112 PSR (dB) 40.3
ΔVREF_TEMP (mV) 2.8 Isupply (μA) 2.6
ΔT (°C) 160 VDD (V) 0.7
ΔVREF_VDD (mV) 2.1 P (μW) 1.82
In order to have estimation of the impact of fabrication process on the temperature performance of VREF, the circuit was also simulated using corner models. The MOSFET corner models used in this simulation were: TT (Typical-Typical), SS (Slow-Slow), FF (Fast-Fast), SF (Slow-Fast) and FS (Fast-Slow). The resistor and BJT corner models used were: TT, SS and FF.
R3 = 335K R3 = 250K
Figure 5 illustrates the simulation of VREF as a function of temperature using corner models. Curves ‘a’ and ‘b’ represent, respectively, the cases where VREF has the highest and lowest values. Curve ‘a’ was obtained using the following models: SF (MOS), FF (Resistor) and FF (BJT); while curve ‘b’ has used FS (MOS), SS (Resistor) and SS (BJT) models. The variation of VREF @ 27 °C between the last two cases is 15.7 mV. The worst estimated temperature performance (ΔVREF_TEMP) among all simulated cases is equal to 3.5 mV, what represents TC equal to 144 ppm/°C. Table 7 summaries the main simulation results using corner models. Because mismatch is not taken into account in the former analysis, Monte Carlo simulation is still required to have a complete estimation of fabrication process effects.
R3 = 168K
Figure 3. Simulated VREF as a function of temperature for nominal R3 (above) and three different values (bellow) Figure 4 shows the PSR performance when a load capacitance of 5 pF is connected at the output node. It is also shown VREF as a function of VDD. The circuit provides 40.3 dB (@ 1 kHz) of power supply rejection, and properly works until VDD equal 0.6 volts. Table 6 presents all results discussed so far.
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6. ACKNOWLEDGMENTS The authors would like to acknowledge the financial support from the Emerging Leaders in the Americas Program (ELAP) provided by the government of Canada, Natural Sciences and Engineering Research Council of Canada (NSERC), ReSMIQ, and the Brazilian Funding Agencies CNPq and CAPES.
7. REFERENCES [1] Fayomi, C. J. B. and Stratz, S. J. 2006. Novel Approach to Low-Voltage Low-Power Bandgap Reference in Standard CMOS Process. In Proc of the 13th IEEE International Conference on Electronics, Circuits and Systems (Nice, France, December 10-13, 2006). ICECS’06. pp. 208-211. DOI: http://dx.doi.org/10.1109/ICECS.2006.379762.
Figure 5. Simulated VREF as a function of temperature using corner models Table 7. Simulation of VREF and ΔVREF_TEMP using corner models MOS: TT SS FF SF Model RES: TT SS FF FF BJT: TT SS FF FF 156.2 160.5 152.4 164.4 VREF (mV) 2.8 3.2 3.5 3.5 ΔVREF_TEMP (mV) 112 124 144 133 TC (ppm/°C)
[2] Kundu, A. L. et al. 2008. A Methodology for efficient design of analog circuits using an automated simulation based synthesis tool. In Proc of the IEEE International Symposium on Circuits and Systems (Seattle, USA, May 18-21, 2008). ISCAS’2008. pp. 732 – 735. DOI: http://dx.doi.org/10.1109/ISCAS.2008.4541522.
FS SS SS 148.7 3.0 126
[3] Binkley, D. M. 2008. Analog CMOS Design, Tradeoffs and Optimization. John Wiley and Sons. 2008. [4] Binkely, D. M. 2007. Tradeoffs and optimization in analog CMOS design. In Proc of the IEEE 14th Int. Conf. Mixed Design of Integrated Circuits and Systems (Ciechocinek, Poland, June 21-23, 2007). MIXDES’07. 47-60. DOI: http://dx.doi.org/10.1109/MIXDES.2007.4286119.
The methodology presented in our work is suitable not only for the circuit presented in fig. 2, but for any voltage reference that must operate under low-voltage and low-power requirements using subthreshold MOSFETs. The advantage of proposed methodology if compared to the traditional approach - Equations (13-14) -, is the conscious choice of the level of MOS inversion, which allows a quick estimation, with reasonable accuracy, of transistor width for a given set of design choices (Current, Channel length and IC). The estimation provided by Equations (112) and (15-25) differs from the simulated results by less than 20%.
[5] Jianping, W. et al. 2005. A Novel Low-Voltage Low-Power CMOS Voltage Reference Based on Subthreshold MOSFETs. In Proc of the 6th IEEE Int. Conf. on ASIC (Shangai, China, October 24-27, 2005). ASICON 2005. 369373. DOI: http://dx.doi.org/10.1109/ICASIC.2005.1611340. [6] Banba, H. et al. 1999. A CMOS Bandgap Reference Circuit with sub-1-V operation. IEEE Journal of Solid-State Circuits (May 1999). Vol. 34, No. 5, pp. 670-674. DOI: http://dx.doi.org/10.1109/4.760378.
The demand for analog design methods that drive quickly the process of sizing transistors in weak and moderate inversion are increasingly important for recent LVLP applications due to low drain-source saturation voltage. For 0.18-μm technology, VDSAT values are respectively around: 100 mV for weak inversion, and between 100 to 240 mV for moderate inversion.
[7] Giustolisi, G. et al. A Low-Voltage Low Power Voltage Reference Based on Subthreshold MOSFETs. IEEE Journal of Solid-State Circuits (Jan. 2003). Vol. 38, No.1, pp. 151154. DOI: http://dx.doi.org/10.1109/JSSC.2002.806266. [8] Filanovsky, I. M. and Allam, A. Mutual compensation of mobility and threshold voltage temperature effects with application in CMOS Circuits. IEEE Transactions on Circuits and Systems (July 2001). Vol. 48, pp. 876-884. DOI: http://dx.doi.org/10.1109/81.933328.
5. CONCLUSIONS The proposed methodology, used as initial design guidance, reduces the design cycle time of low-voltage and low-power voltage references based on subthreshold operation. The inversion coefficient applied in the methodology enables design freely in weak, moderate and strong inversion, what leads to an optimization of the transistor sizing process. The difference between simulated results and estimation provided by proposed equations differs by less than 20%. Simulations to evaluate a candidate circuit design over process variation and layout parasitics are still required. The voltage reference used as a case study works under a 0.7 V supply voltage while consuming 1.82 μW.
[9] Liu, W., Jin, X., Xi, X., et al. 2005. BSIM3v3.3 MOSFET Model – User’s Manual. Retrieved June 02, 2010 from http://www-device.eecs.berkeley.edu/~bsim3.
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