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Design of Class-E Amplifier With MOSFET Linear Gate-to-Drain and Nonlinear Drain-to-Source Capacitances Xiuqin Wei, Student Member, IEEE, Hiroo Sekiya, Senior Member, IEEE, Shingo Kuroiwa, Tadashi Suetsugu, Senior Member, IEEE, and Marian K. Kazimierczuk, Fellow, IEEE
Abstract—This paper presents expressions for the waveforms and design equations to satisfy the ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. Expressions are given for power output capability and power conversion efficiency. Design examples are presented along with the PSpice-simulation and experimental waveforms at 2.3 W output power and 4 MHz operating frequency. It is shown from the expressions that the slope of the voltage across the MOSFET gate-to-drain parasitic capacitance during the switch-off state affects the switch-voltage waveform. Therefore, it is necessary to consider the MOSFET gate-to-drain capacitance for achieving the class-E ZVS/ZDS conditions. As a result, the power output capability and the power conversion efficiency are also affected by the MOSFET gate-to-drain capacitance. The waveforms obtained from PSpice simulations and circuit experiments showed the quantitative agreements with the theoretical predictions, which verify the expressions given in this paper. Index Terms—Class-E power amplifier, class-E ZVS/ZDS conditions, MOSFET drain-to-source nonlinear parasitic capacitance, MOSFET gate-to-drain parasitic capacitance.
I. INTRODUCTION HE SHUNT capacitance is an important element of the class-E power amplifier [1]–[27] to satisfy the class-E zero-voltage switching and zero-derivative switching (ZVS/ZDS) conditions, which ensure zero switching loss and low noise, and improve component tolerances. Usually, the shunt capacitance is composed of both the external linear capacitance and the MOSFET drain-to-source nonlinear parasitic capacitance. At low frequencies, the MOSFET parasitic capacitances can be neglected because the external linear shunt capacitance, which is connected between the drain and the source of the MOSFET in parallel, is dominant in the shunt
T
Manuscript received August 30, 2010; revised January 13, 2011; accepted February 11, 2011. This paper was recommended by Associate Editor E. Alarcon. X. Wei, H. Sekiya, and S. Kuroiwa are with the Graduate School of Advanced Integration Science, Chiba University, Chiba, 263-8522 Japan (e-mail: [email protected]; [email protected]; [email protected]). T. Suetsugu is with the Department of Electronics Engineering and Computer Science, Fukuoka University, Fukuoka, 814-0180 Japan (e-mail: [email protected]). M. K. Kazimierczuk is with the Department of Electrical Engineering, Wright State University, Dayton, OH, 45435-0001 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2011.2123490
capacitance. The value of the total shunt capacitance, however, decreases as the operating switching frequency increases. Therefore, the effects of the MOSFET parasitic capacitances increase as the operating frequency increases. The effects of the MOSFET parasitic capacitances were considered in [8]–[10]. These papers took into account the MOSFET drain-to-source and gate-to-drain parasitic capacitances. The results of these papers suggest that it is important to consider not only the MOSFET drain-to-source capacitance, but also the gate-to-drain capacitance. However, the analyses in [8]–[10] are based on the assumption that the MOSFET drain-to-source parasitic capacitance is a linear element. Recently, several publications have been published on the class-E power amplifier with the MOSFET drain-to-source nonlinear parasitic capacitance [12]–[16]. It can be stated from the results in [12]–[16] that it is important to consider the nonlinearity of the MOSFET drain-to-source capacitance for achieving the class-E ZVS/ZDS conditions. These papers, however, did not take into account the MOSFET gate-to-drain capacitance because the shunt capacitance is usually expressed as the capacitance connected between the drain and the source. Therefore, some errors occur on the switch-voltage waveform when using the actual MOSFET with the gate-to-drain capacitance, which is ignored in [13]. Fig. 1(a) shows the switch-voltage waveform from the PSpice simulation by using the component values obtained from [13] and an actual PSpice MOSFET model including the gate-to-drain parasitic capacitance. In this subfigure, the switch-voltage waveform does not satisfy the class-E ZVS/ZDS conditions. Therefore, some adjustments are needed to achieve the class-E ZVS/ZDS conditions in the circuit implementations. Fig. 1(b) shows the PSpice-simulation waveform obtained using the same passive lumped component values as those in Fig. 1(a) except that the MOSFET gate-to-drain capacitance is zero. In this waveform, it is seen that the class-E ZVS/ZDS conditions are achieved. From the waveforms in Fig. 1, we can confirm that it is important to consider the MOSFET gate-to-drain parasitic capacitance for achieving the class-E ZVS/ZDS conditions in real circuits as suggested in [8]–[10]. This paper, which was previously presented in part at ISCAS 2010 [11], presents expressions of the waveforms and design equations to satisfy the class-E ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. The combination of the nonlinear drain-to-source capacitance and the linear gate-to-drain capacitance follows PSpice MOSFET
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Fig. 1. PSpice-simulation waveforms of the class-E power amplifier with the component values obtained from the design equations in [13] for IRF510 MOSFET. (a) For MOSFET model with C 6 . (b) For MOSFET model with C .
=0
=0
models. This expression is reasonable and useful because the parameters of MOSFETs can be obtained easily from PSpice MOSFET models. In [11], expressions were derived for the square gate-to-source voltage only. The expressions in this paper are valid for not only the square gate-to-source voltage, but also the sinusoidal gate-to-source voltage. Because the sinusoidal voltage is usually adopted for UHF class-E power amplifiers, it is useful to obtain the expressions for the sinusoidal gate-to-source voltage. Additionally, expressions for the power output capability and the power conversion efficiency are also given in this paper. The expressions are verified by comparing them with both the PSpice simulations and the circuit experiments in detail. The PSpice simulation and experimental results showed quantitative agreement with the theoretical predictions.
Fig. 2. Circuit and model of class-E power amplifier. (a) Circuit topology of the class-E power amplifier in [1]–[27]. (b) Equivalent circuit analyzed in this paper.
II. CLASS-E POWER AMPLIFIER Fig. 2(a) shows a circuit topology of the class-E power amplifier [1]–[27]. This amplifier is composed of dc-supply , dc-feed inductor , MOSFET as a voltage source switching device , shunt capacitance , and series resonant filter . Fig. 3 depicts example waveforms in the class-E power amplifier when the switch-on duty ratio is 0.5. In the class-E power amplifier, the switch is driven by a gate-to-source voltage . During the switch-off interval, the sum of currents through the dc-feed inductance and the resonant filter flow through the shunt capacitance . The current through the shunt capacitance produces the switch voltage . Moreover, the switch-voltage waveform satisfies the zero-voltage switching (ZVS) and zero-derivative switching (ZDS) conditions at the switch turn-on instant, that is, (1) (2) Because of the class-E ZVS/ZDS conditions, the switching power loss is minimized to zero. Therefore, high power conversion efficiency can be achieved at high frequencies [17]–[19]. Additionally, the class-E ZVS/ZDS conditions ensure a low noise level and improve component tolerances. The shunt capacitance is an important element to satisfy the class-E ZVS/ZDS conditions. The MOSFET drain-tosource parasitic capacitance is dominant in a shunt capacitance at high frequencies. The MOSFET drain-to-source parasitic capacitance has a nonlinear characteristic [12]–[16], which is expressed as (3)
Fig. 3. Example waveforms in the class-E power amplifier for D
= 0:5.
where is the built-in potential, which typically ranges from 0.5 to 0.9 V, is the switch voltage, and is the capacitance at . III. ANALYSIS OF THE CLASS-E POWER AMPLIFIER WITH MOSFET PARASITIC CAPACITANCES In this section, expressions for the class-E power amplifier, taking into account not only the MOSFET drain-to-source nonbut also the gate-to-drain linear linear parasitic capacitance parasitic capacitance , are presented. A. Assumptions The analysis in this paper is based on the following assumptions. 1) The shunt capacitance is composed of only the MOSFET drain-to-source parasitic capacitance which is given in
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From (4), the voltage across the MOSFET gate-to-drain capacitance is
TABLE I THE SWITCHING PATTERN OF THE CLASS-E POWER AMPLIFIER
(9)
(3) for . The assumption of is useful to obtain analytical equations [12]–[14]. 2) The MOSFET gate-to-drain capacitance is linear. This assumption is the same as that in [8]–[10]. The assumptions 1 and 2 follow PSpice MOSFET models, which have a nonlinear drain-to-source capacitance and a linear gate-todrain capacitance. 3) The driver circuit is an ideal voltage source as shown in Fig. 2(b). The gate-to-source voltage is expressed as
Therefore, the current through the MOSFET device during the off-state is expressed as
(10) (4) is the amplitude of the fundamental frequency where component of the gate-to-source voltage and is the MOSFET turn-on threshold voltage. Therefore, the switch-on duty ratio is 0.5 and the switching pattern in this analysis is given in Table I. 4) The dc-feed inductance is large enough so that the current through the dc-feed inductor is the direct current . 5) The loaded quality factor of the output resonant circuit, which is defined as
where and are the currents through the MOSFET parasitic capacitances and , respectively. From (10) and , we obtain
(11) From (7) and (11), we have
(5) (12)
is high enough to generate a pure sinusoidal output current where (6) is the amplitude of the output current and is where a phase-shift between the gate-to-source voltage and the output current. 6) The MOSFET works as an ideal switch. Therefore, the on-resistance is zero and the off-resistance is infinite. 7) The resonant inductor is divided into and . The resonant filter is an ideal filter for the operating frequency , that is, . Additionally, the reactance of shifts the phase of the output current of the resonant filter. 8) All elements have no parasitic resistance. 9) The switch voltage satisfies the class-E ZVS/ZDS conditions given in (1) and (2). Using the above assumptions, the equivalent circuit for this analysis can be obtained, as shown in Fig. 2(b).
(13) and (14) Substituting
and (2) into (7) and (10), we obtain (15)
From (1) and (12), we have (16) On the other hand, from (13), we can also obtain (17)
B. Waveform Equations The current through the MOSFET device is
Hence, the dc-supply current (7)
, the switch is in the off-state. Therefore, the For switching current is given as (8)
is (18)
From (15) and (18), we obtain (19)
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C. Power Relations The dc-supply power
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and the output power
TABLE II PARAMETERS OF THE MOSFETs
are (20)
and (21) Because of the assumptions 6 and 8, the power conversion efficiency is (22) From (18) and (22), the amplitude of the output current is (23) the amplitude of the output voltage is (24) and the dc-supply current is (25) From (20), (22), and (25), the dc-supply and output powers are (26) The average value of the switch voltage is equal to the dc-supply voltage ,
(27) (27) does not have an analytical solution, which can be expanded partly as follows:
of the other parameters and can be obtained numerically by solving (28) and (30). When the MOSFET is selected, the value of is determined uniquely. In this paper, the MOSFET parameters are obtained from the PSpice MOSFET models. For example, IRF510 PSpice model is given in the Appendix. The parameters , , and are identical to , , and in the MOSFET model, respectively. Additionally, the MOSFET gate-to-drain parasitic capacitance is obtained as . Table II gives values of , , , , and for three types of MOSFETs obtained from PSpice MOSFET models. as functions of Figs. 4 and 5 show and for fixed values of and three types of MOSFETs, respectively. The switch-voltage waveform during the switch-on state is not affected by the current and voltage at the MOSFET gate-to-drain capacitance. It is seen from the analytical expressions that the slope of the voltage across the MOSFET gate-to-drain capacitance during the switch-off state affects the switch-voltage waveform. Therefore, the characteristics for the square gate-to-source voltage can be obtained by replacing by 0. In fact, the equations for are identical to those in [11], which are for the square gate-to-source voltage. It is seen from (19) and Fig. 4 that is always 0.567 rad for the square gate-to-source voltage regardless of the dc-supply voltage. On the other hand, increases as the dc-supply voltage increases for the sinusoidal gate-to-source voltage. Additionally, converges to when the dc-supply voltage approaches 0. It is seen from Fig. 5 that increases as the dc-supply voltage increases and the values of for the square gate-to-source voltage is always larger than those for the sinusoidal gate-to-source voltage at the same specifications. It is also seen from Fig. 5 that the MOSFET gate-to-drain to low. capacitance makes D. Fourier Analysis The voltage across the reactance is expressed as
(28)
(31) The output voltage Fig. 2(b) is
where
of the resonant filter
shown in
(29) From (23) and (25), (15) is transformed to (32)
(30) where , (28) and (30) are regarded as functions of , , , and . If the three of four parameters, which are , , , and , are specified, the values
is the amplitude of
, (33)
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Fig. 4.
V
=V
'
as a function of V =V for fixed values of g . ' depends on for V =V : and is independent of V =V for V =V .
=75
=0
5
Fig. 6. ! C L as a function of !C R for fixed values of g . increases as !C R increases and depends on V =V .
From (34), the reactance
!C L
is given by (37)
Fig. 6 shows as a function of for fixed , , and . It is seen from Fig. 6 that inincreases and depends on the gate-to-sourcecreases as voltage waveform. is, however, almost independent of the MOSFET type. E. Design Equations From the definition of the loaded quality factor tained as
,
is ob-
(38) Fig. 5. !C creases as V
and
R as a function of V =V increases.
=V
for fixed values of g .
!C R in-
From (37) and (38), the inductor
is (39)
is (34)
From the assumption 7 and (39), the resonant capacitance is obtained as
Because the resonant filter is an ideal filter for the operating frequency from the assumption 7, the output voltage of the resonant filter has only the fundamental-frequency component of the switch voltage . Therefore,
(40) In [27], the dc-feed inductance ratio is less than 0.1 is given by
at which the current ripple
(35) (41) From (35), we obtain IV. POWER OUTPUT CAPABILITY The definition of the power output capability (36) From (13), (23), (25), and (36), it is seen is a function of , , and . (36) has no analytical solution but numerical one.
is (42)
where and current at the MOSFET.
are the peak values of voltage and
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The peak switch voltage . Therefore, we have
appears in the range of
(43) where
satisfies (44)
Equation (44) has no analytical solution for rewritten as
but it is
V =V
Fig. 7.
V
(45) From (28), (30), (43), and (45), we can see that and are functions of , , and . Fig. 7 shows as a function of for fixed values of and three types of MOSFETs. It is seen from Fig. 7 that the peak value of the switch voltage depends on the dc-supply voltage and the MOSFET type. The gate-to-source voltage waveform, however, does not affect the peak value of the switch voltage. Additionally, makes the peak value of the switch voltage low. From the MOSFET breakdown voltage and (43), the permissible dc-supply voltages can be obtained. Table III gives the permissible dc-supply voltage for each MOSFET. The breakdown voltage of all the MOSFETs in Table III is 100 V. The peak current appears during the on-state when is in the range of . It is confirmed from Fig. 4 that the range of satisfies this condition. Therefore,
=V as a function of depends only on g and V
V =V =V .
for fixed values of
g.
TABLE III PERMISSIBLE DC-SUPPLY VOLTAGES
increases for a sinusoidal gate-to-source voltage and is always 2.86 when the gate-to-source voltage is a square waveform or . Substituting (43) and (47) into (42), we obtain the equation at the bottom of the page. Fig. 9 shows the power output capability as a function of . It is seen from Fig. 9 that depends on dc-supply voltage, gate-to-source voltage waveform, and MOSFET type. The output capabilities for the square gate-to-source voltage are always higher than those for the sinusoidal gate-to-source voltage.
V. POWER CONVERSION EFFICIENCY (46) From (18) and (46), we obtain (47) Fig. 8 shows It is seen from Fig. 8 that
as a function of . decreases as
In real circuits, the amplifier losses occur in the parasitic resistances of each component. The class-E ZVS/ZDS conditions do is not offer the maximum efficiency when the on-resistance considered [19], [20]. In this paper, we consider the power losses in equivalent series resistance (ESR) of the dc-feed inductor , ESR of the load network , and switch-on resistance as shown in Fig. 10. The ESRs of parasitic capacitances are ignored because they are much smaller than the other ESRs. It
(48)
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Fig. 10. The equivalent circuit of the class-E power amplifier including ESRs.
Fig. 8. I I
of V
=I as a function of V =V =I depends on V =V for V =V =V for V =V .
for fixed values of g .
(51)
= 7:5 and is independent
=0
Using (23), (25), and (49)–(51), the power conversion efficiency is
(52)
Fig. 9. c as a function of V V =V , g , and V =V .
=V
for fixed values of g . c depends on
is assumed that the parasitic resistances are small enough not to affect the waveforms. The power loss in is obtained as
It is seen from (52) that the ratio of ESRs to the load resistance determine the power conversion efficiency. From these expressions in this paper, most expressions are composed of , , , , and . It can be stated that these five parameters determine the characteristic of the class-E power amplifier. VI. DESIGN EXAMPLE
(49) Similarly, the power loss
in
is (50)
For power loss
, the switching current is zero. Hence, the in the switch-on resistance is
In this section, two design examples were given, one was for the sinusoidal gate-to-source voltage and the other was for the square gate-to-source voltage. The design specifications of the class-E power amplifier were dc-supply voltage V, operating frequency MHz, and loaded quality factor . The IRF510 MOSFET was used as a switching device. From Table III, it is confirmed that the IRF510 MOSFET is suitable for the specifications from the breakdown voltage point of view. The parameters of the MOSFET could be obtained from PSpice MOSFET model given in Table II. For the sinusoidal gate-to-source voltage, the amplitude of the V. Therefore, we gate-to-source voltage was specified as had and . From (28) and (30), and . Hence, the load we obtained resistance was
(53)
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TABLE IV THEORETICAL PREDICTIONS, PSPICE SIMULATIONS, AND EXPERIMENTAL MEASUREMENTS FOR A SINUSOIDAL GATE-TO-SOURCE VOLTAGE
3Difference means the comparison between the theoretical method and the measured method.
Following the design equations in Section II-E, the element values could be obtained as given in Table IV. From (26), we had W. could be obtained from (47). From (45), we obtained rad. Therefore, we had . As a result, the power output capability was 0.086 from (42). for 3% ripple ratio and were derived theoretically by using the calculation method in [21] and [22], respectively. Additionally, was obtained from the PSpice model of the IRF510. From (52) and these ESR values, we obtained . The theoretical predictions for the sinusoidal gate-to-source voltage were summarized in Table IV. Following a similar procedure described the above, we could obtain the design values for the square gate-to-source voltage, , as given in Table V. that is Fig. 11 shows the waveforms obtained from theoretical expressions, PSpice simulations, and circuit experiments. The circuit topology of the PSpice simulation includes the ESRs as shown in Fig. 10. In the circuit experiments, the driver circuits were designed with the consideration of the MOSFET gate resistance and the gate-to-source capacitance [28], [29]. The element values of passive elements including ESRs were measured by HP4284A impedance meter. The ESR of the dc-feed inductor was measured at dc, which followed the experimental measurements in [23]. We confirmed that the self-resonant frequency (SRF) of the dc-feed inductor was about three times higher than the operating frequency. It is seen from Fig. 11 that the switch-voltage waveforms of both the PSpice simulations and the circuit experiments satisfied the class-E ZVS/ZDS conditions and agreed with the theoretical waveforms well. In the PSpice simulation and the circuit experiment for the sinusoidal gate-to-source voltage, it seems that the switch-on duty ratio is a little lower than that of the theoretical prediction [24], [25]. This is because the assumption for the sinusoidal gate-to-source voltage is only valid if the power gain of the transistor is infinite or the amplitude of the driving voltage is infinite. Tables IV and V also give the PSpice-simulation and
TABLE V THEORETICAL PREDICTIONS, PSPICE SIMULATIONS, AND EXPERIMENTAL MEASUREMENTS FOR A SQUARE GATE-TO-SOURCE VOLTAGE
3 Difference means the comparison between the theoretical method and the measured method.
for experimental results. In these tables, the output power the simulations and the experiments is the sum of powers at all harmonics [26]. The power gain is (54) where is the input power as shown in Fig. 2(a). Additionally, the total harmonic distortion (THD) is
THD
(55)
where is a root-mean-square value of the th harmonic in the output voltage , respectively. For obtaining measured and THD values, we used the waveform data of the outputvoltage from Textronix TDS3014B. The PSpice-simulation and experimental measurements agreed with the theoretical predictions quantitatively. These results verify the derived expressions. Fig. 12 shows the PSpice-simulation waveforms for the square gate-to-source voltage, MHz, V, V, pF, and fixed values of and without ESRs. Table VI gives the element values for these simulations. It is seen from Fig. 12 that only the switch voltage waveform for and satisfied the class-E ZVS/ZDS conditions. It can be stated from these results that it is important and effective to consider the MOSFET gate-to-drain capacitance and the nonlinearity of the MOSFET drain-to-source capacitance. VII. CONCLUSION This paper has presented expressions for the waveforms and design equations for achieving the ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. Two design examples are given along with the PSpice-simulation and
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the linear and nonlinear shunt capacitance and the MOSFET gate-to-drain capacitance is an important problem we should address in the future. APPENDIX The MOSFET model used in this paper is obtained from the default package of PSpice, which is licensed by Cadence. The IRF510 MOSFET parameters are shown as follows. .model IRF510 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 Tox=100n Uo=600 Phi=.6 Rs=.4508 Kp=20.68u W=0.64 L=2u Vto=3.697 Rd=21.08m Rds=444.4K Cbd=366.5p Pb=.8 Mj=.5 Fc=.5 Cgso=600.5p Cgdo=62.71p Rg=2.977 Is=202.9f N=1 Tt=135n) Int’l Rectifier pid=IRFC110 case=TO220 88-08-25 bam creation REFERENCES
Fig. 11. Waveforms obtained from theoretical expressions (dashed line), PSpice simulations (solid line), and circuit experiments (dotted line). (a) For the sinusoidal gate-to-source voltage. (b) For the square gate-to-source voltage.
Fig. 12. Switch-voltage waveforms for the element values given in Table VI.
ELEMENT VALUES FOR f
TABLE VI
= 4 MHz, V = 15 V, V = 0:8 V, V = 0, AND C = 366:5 pF
experimental results. The switch-voltage waveforms obtained from PSpice simulations and experimental measurements achieved the class-E ZVS/ZDS conditions, which verify the expressions given in this paper. In this paper, we used a fabricated MOSFET in the circuit experiments. The parameter for the shunt capacitance was fixed and not controllable when the MOSFET was selected. Therefore, it was not required to specify the output power or the load resistance. If it is allowed to add the linear external shunt capacitance or to design the MOSFET with the required parasitic-capacitance value, either the output power or the load resistance can be specified. The analysis of the class-E amplifier with
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[17] C. Yoo and Q. Huang, “A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25- m CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 823–830, May 2001. [18] J. Ramos, K. Francken, G. G. E. Gielen, and M. S. J. Steyaert, “An efficient, fully parasitic-aware power amplifier design optimization tool,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 8, pp. 1526–1534, Aug. 2005. [19] N. O. Sokal, “Class E RF power amplifiers,” QEX, no. 204, pp. 9–20, Jan./Feb. 2001. [20] F. del Aguila, P. Pala, J. Bonet, and R. Giralt, “A technique for maximum efficiency class-E amplifier design,” in Proc. ECCTD’03, Cracow, Poland, Sep. 2003, pp. 281–284. [21] H. Sekiya and M. K. Kazimierczuk, “Design of RF-choke inductors using core geometry coefficient,” presented at the EMCW 2009, Nashville, TN, Sep. 2009. [22] N. Sagawa, H. Sekiya, and M. K. Kazimierczuk, “Computer-aided design for class-E switching circuits taking into account optimized inductor design,” in Proc. IEEE APEC, Feb. 2010, pp. 2212–2219. [23] K. Shinoda, T. Suetsugu, M. Matsuo, and S. Mori, “Analysis of phasecontrolled resonant DC-AC inverters with class E amplifier and frequency multipliers,” IEEE Trans. Ind. Electron., vol. 45, no. 3, pp. 412–420, Jun. 1998. [24] D. Kessler and M. K. Kazimierczuk, “Power losses and efficiency of class-E power amplifier at any duty ratio,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 9, pp. 1675–1689, Sep. 2004. [25] T. Suetsugu and M. K. Kazimierczuk, “Maximum operating frequency of class-E amplifier at any duty ratio,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 8, pp. 768–770, Aug. 2008. [26] M. K. Kazimierczuk, “Exact analysis of class E tuned power amplifier with only one inductor and one capacitor in load network,” IEEE J. Solid-State Circuits, vol. SC-18, no. 2, pp. 214–221, Apr. 1983. [27] M. K. Kazimierczuk, RF Power Amplifiers. New York: Wiley, 2008. [28] J. Ebert and M. K. Kazimierczuk, “Class E high-efficiency tuned power oscillator,” IEEE J. Solid-State Circuits, vol. SC-16, no. 2, pp. 62–66, Apr. 1981. [29] H. Hase, H. Sekiya, J. Lu, and T. Yahagi, “Novel design procedure for MOSFET class E oscillator,” IEICE Trans. Fundam., vol. E87-A, no. 9, pp. 2241–2247, Sep. 2004. Xiuqin Wei (S’10) was born in Fujian, China, on December 7, 1983. She received the B.E. degree from Fuzhou University, China, in 2005. She is currently working toward the Ph.D. degree in the Graduate School of Advanced Integration Science, Chiba University, Chiba, Japan. Her research interests include high-frequency power amplifiers.
Hiroo Sekiya (S’97–M’01) was born in Tokyo, Japan, on July 5, 1973. He received the B.E., M.E., and Ph.D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1996, 1998, and 2001 respectively. Since April 2001, he has been with Chiba University; he is currently an Assistant Professor at the Graduate School of Advanced Integration Science, Chiba University, Chiba, Japan. Since February 2008, he has been also with Electrical Engineering, Wright State University, Dayton, OH, as a Visiting Scholar. His research interests include high-frequency high-efficiency tuned power amplifiers, resonant dc/dc power converters, dc/ac inverters, and digital signal processing for wireless communication. Dr. Sekiya is a member of the Institute of Electronics, Information and Communication Engineers (IEICE) of Japan, Information Processing Society of Japan (IPSJ), Society Information Theory and its Application (SITA), Japan, and Research Institute of Signal Processing (RISP), Japan.
Shingo Kuroiwa received the B.E., M.E., and D.E. degrees in electro-communications from the University of Electro Communications, Tokyo, Japan, in 1986, 1988, and 2000, respectively. From 1988 to 2001, he was a Researcher at the KDD R & D Laboratories. From 2001 to 2007, he was an Associate Professor of Institute of Technology and Science at the University of Tokushima, Japan. Since 2007, he has been with Chiba University, Chiba, Japan, where he is currently a Professor of Graduate School of Advanced Integration Science. His current research interests include speech recognition, speaker recognition, signal processing, and information retrieval. Prof. Kuroiwa is a member of the ISCA, IEICE, IPSJ, and ASJ.
Tadashi Suetsugu (S’92-M’95-SM’02) received the B.E., M.E., and Ph.D. degrees in electrical engineering from the Department of Electrical Engineering, Keio University, Yokohama, Japan, in 1990, 1992, and 1995, respectively. He was an Assistant Professor from 1995 to 1998 with the Department of Electronics, Fukuoka University, Japan. In 2001–02, he was a Visiting Professor with the Department of Electrical Engineering, Wright State University, Dayton, OH. Since 1998, he has been with the Department of Electronics Engineering and Computer Science, Fukuoka University, Fukuoka, Japan, where he is currently an Associate Professor. His research interests are in high-frequency high-efficiency switching-mode tuned power amplifiers, resonant dc/dc power converters, dc/ac inverters, high-frequency rectifiers, numerical simulation of switching circuits, and power line communications. Dr. Suetsugu is a member of Institute of Electronics, Information, and Communication Engineers (Japan).
Marian K. Kazimierczuk (M’91-SM’91-F’04) received the M.S., and Ph.D., and D.Sci. degrees in electronics engineering from the Department of Electronics, Technical University of Warsaw, Warsaw, Poland, in 1971, and 1978, and 1984, respectively. He was a Teaching and Research Assistant from 1972 to 1978 and Assistant Professor from 1978 to 1984 with the Department of Electronics, Institute of Radio Electronics, Technical University of Warsaw, Poland. In 1984, he was a Project Engineer for Design Automation, Inc., Lexington, MA. In 1984–85, he was a Visiting Professor with the Department of Electrical Engineering, Virginia Polytechnic Institute and State University, VA. Since 1985, he has been with the Department of Electrical Engineering, Wright State University, Dayton, OH, where he is currently a Professor. His research interests are in high-frequency high-efficiency switchingmode tuned power amplifiers, resonant and PWM dc/dc power converters, dc/ac inverters, high-frequency rectifiers, electronic ballasts, modeling and control of converters, high-frequency magnetics, power semiconductor devices. Prof. Kazimierczuk received the IEEE Harrell V. Noble Award for his contributions to the fields of aerospace, industrial, and power electronics, in 1991. He was and is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I, and served as an Associate Editor for the Journal of Circuits, Systems, and Computers. He was a member of the Superconductivity Committee of the IEEE Power Electronics Society. He was a chair of the CAS Technical Committee of Power Systems and Power Electronics Circuits in 2001–2002. He is a member of Tau Beta Pi.
1
Design of Class-E Amplifier With MOSFET Linear Gate-to-Drain and Nonlinear Drain-to-Source Capacitances Xiuqin Wei, Student Member, IEEE, Hiroo Sekiya, Senior Member, IEEE, Shingo Kuroiwa, Tadashi Suetsugu, Senior Member, IEEE, and Marian K. Kazimierczuk, Fellow, IEEE
Abstract—This paper presents expressions for the waveforms and design equations to satisfy the ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. Expressions are given for power output capability and power conversion efficiency. Design examples are presented along with the PSpice-simulation and experimental waveforms at 2.3 W output power and 4 MHz operating frequency. It is shown from the expressions that the slope of the voltage across the MOSFET gate-to-drain parasitic capacitance during the switch-off state affects the switch-voltage waveform. Therefore, it is necessary to consider the MOSFET gate-to-drain capacitance for achieving the class-E ZVS/ZDS conditions. As a result, the power output capability and the power conversion efficiency are also affected by the MOSFET gate-to-drain capacitance. The waveforms obtained from PSpice simulations and circuit experiments showed the quantitative agreements with the theoretical predictions, which verify the expressions given in this paper. Index Terms—Class-E power amplifier, class-E ZVS/ZDS conditions, MOSFET drain-to-source nonlinear parasitic capacitance, MOSFET gate-to-drain parasitic capacitance.
I. INTRODUCTION HE SHUNT capacitance is an important element of the class-E power amplifier [1]–[27] to satisfy the class-E zero-voltage switching and zero-derivative switching (ZVS/ZDS) conditions, which ensure zero switching loss and low noise, and improve component tolerances. Usually, the shunt capacitance is composed of both the external linear capacitance and the MOSFET drain-to-source nonlinear parasitic capacitance. At low frequencies, the MOSFET parasitic capacitances can be neglected because the external linear shunt capacitance, which is connected between the drain and the source of the MOSFET in parallel, is dominant in the shunt
T
Manuscript received August 30, 2010; revised January 13, 2011; accepted February 11, 2011. This paper was recommended by Associate Editor E. Alarcon. X. Wei, H. Sekiya, and S. Kuroiwa are with the Graduate School of Advanced Integration Science, Chiba University, Chiba, 263-8522 Japan (e-mail: [email protected]; [email protected]; [email protected]). T. Suetsugu is with the Department of Electronics Engineering and Computer Science, Fukuoka University, Fukuoka, 814-0180 Japan (e-mail: [email protected]). M. K. Kazimierczuk is with the Department of Electrical Engineering, Wright State University, Dayton, OH, 45435-0001 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSI.2011.2123490
capacitance. The value of the total shunt capacitance, however, decreases as the operating switching frequency increases. Therefore, the effects of the MOSFET parasitic capacitances increase as the operating frequency increases. The effects of the MOSFET parasitic capacitances were considered in [8]–[10]. These papers took into account the MOSFET drain-to-source and gate-to-drain parasitic capacitances. The results of these papers suggest that it is important to consider not only the MOSFET drain-to-source capacitance, but also the gate-to-drain capacitance. However, the analyses in [8]–[10] are based on the assumption that the MOSFET drain-to-source parasitic capacitance is a linear element. Recently, several publications have been published on the class-E power amplifier with the MOSFET drain-to-source nonlinear parasitic capacitance [12]–[16]. It can be stated from the results in [12]–[16] that it is important to consider the nonlinearity of the MOSFET drain-to-source capacitance for achieving the class-E ZVS/ZDS conditions. These papers, however, did not take into account the MOSFET gate-to-drain capacitance because the shunt capacitance is usually expressed as the capacitance connected between the drain and the source. Therefore, some errors occur on the switch-voltage waveform when using the actual MOSFET with the gate-to-drain capacitance, which is ignored in [13]. Fig. 1(a) shows the switch-voltage waveform from the PSpice simulation by using the component values obtained from [13] and an actual PSpice MOSFET model including the gate-to-drain parasitic capacitance. In this subfigure, the switch-voltage waveform does not satisfy the class-E ZVS/ZDS conditions. Therefore, some adjustments are needed to achieve the class-E ZVS/ZDS conditions in the circuit implementations. Fig. 1(b) shows the PSpice-simulation waveform obtained using the same passive lumped component values as those in Fig. 1(a) except that the MOSFET gate-to-drain capacitance is zero. In this waveform, it is seen that the class-E ZVS/ZDS conditions are achieved. From the waveforms in Fig. 1, we can confirm that it is important to consider the MOSFET gate-to-drain parasitic capacitance for achieving the class-E ZVS/ZDS conditions in real circuits as suggested in [8]–[10]. This paper, which was previously presented in part at ISCAS 2010 [11], presents expressions of the waveforms and design equations to satisfy the class-E ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. The combination of the nonlinear drain-to-source capacitance and the linear gate-to-drain capacitance follows PSpice MOSFET
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Fig. 1. PSpice-simulation waveforms of the class-E power amplifier with the component values obtained from the design equations in [13] for IRF510 MOSFET. (a) For MOSFET model with C 6 . (b) For MOSFET model with C .
=0
=0
models. This expression is reasonable and useful because the parameters of MOSFETs can be obtained easily from PSpice MOSFET models. In [11], expressions were derived for the square gate-to-source voltage only. The expressions in this paper are valid for not only the square gate-to-source voltage, but also the sinusoidal gate-to-source voltage. Because the sinusoidal voltage is usually adopted for UHF class-E power amplifiers, it is useful to obtain the expressions for the sinusoidal gate-to-source voltage. Additionally, expressions for the power output capability and the power conversion efficiency are also given in this paper. The expressions are verified by comparing them with both the PSpice simulations and the circuit experiments in detail. The PSpice simulation and experimental results showed quantitative agreement with the theoretical predictions.
Fig. 2. Circuit and model of class-E power amplifier. (a) Circuit topology of the class-E power amplifier in [1]–[27]. (b) Equivalent circuit analyzed in this paper.
II. CLASS-E POWER AMPLIFIER Fig. 2(a) shows a circuit topology of the class-E power amplifier [1]–[27]. This amplifier is composed of dc-supply , dc-feed inductor , MOSFET as a voltage source switching device , shunt capacitance , and series resonant filter . Fig. 3 depicts example waveforms in the class-E power amplifier when the switch-on duty ratio is 0.5. In the class-E power amplifier, the switch is driven by a gate-to-source voltage . During the switch-off interval, the sum of currents through the dc-feed inductance and the resonant filter flow through the shunt capacitance . The current through the shunt capacitance produces the switch voltage . Moreover, the switch-voltage waveform satisfies the zero-voltage switching (ZVS) and zero-derivative switching (ZDS) conditions at the switch turn-on instant, that is, (1) (2) Because of the class-E ZVS/ZDS conditions, the switching power loss is minimized to zero. Therefore, high power conversion efficiency can be achieved at high frequencies [17]–[19]. Additionally, the class-E ZVS/ZDS conditions ensure a low noise level and improve component tolerances. The shunt capacitance is an important element to satisfy the class-E ZVS/ZDS conditions. The MOSFET drain-tosource parasitic capacitance is dominant in a shunt capacitance at high frequencies. The MOSFET drain-to-source parasitic capacitance has a nonlinear characteristic [12]–[16], which is expressed as (3)
Fig. 3. Example waveforms in the class-E power amplifier for D
= 0:5.
where is the built-in potential, which typically ranges from 0.5 to 0.9 V, is the switch voltage, and is the capacitance at . III. ANALYSIS OF THE CLASS-E POWER AMPLIFIER WITH MOSFET PARASITIC CAPACITANCES In this section, expressions for the class-E power amplifier, taking into account not only the MOSFET drain-to-source nonbut also the gate-to-drain linear linear parasitic capacitance parasitic capacitance , are presented. A. Assumptions The analysis in this paper is based on the following assumptions. 1) The shunt capacitance is composed of only the MOSFET drain-to-source parasitic capacitance which is given in
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3
From (4), the voltage across the MOSFET gate-to-drain capacitance is
TABLE I THE SWITCHING PATTERN OF THE CLASS-E POWER AMPLIFIER
(9)
(3) for . The assumption of is useful to obtain analytical equations [12]–[14]. 2) The MOSFET gate-to-drain capacitance is linear. This assumption is the same as that in [8]–[10]. The assumptions 1 and 2 follow PSpice MOSFET models, which have a nonlinear drain-to-source capacitance and a linear gate-todrain capacitance. 3) The driver circuit is an ideal voltage source as shown in Fig. 2(b). The gate-to-source voltage is expressed as
Therefore, the current through the MOSFET device during the off-state is expressed as
(10) (4) is the amplitude of the fundamental frequency where component of the gate-to-source voltage and is the MOSFET turn-on threshold voltage. Therefore, the switch-on duty ratio is 0.5 and the switching pattern in this analysis is given in Table I. 4) The dc-feed inductance is large enough so that the current through the dc-feed inductor is the direct current . 5) The loaded quality factor of the output resonant circuit, which is defined as
where and are the currents through the MOSFET parasitic capacitances and , respectively. From (10) and , we obtain
(11) From (7) and (11), we have
(5) (12)
is high enough to generate a pure sinusoidal output current where (6) is the amplitude of the output current and is where a phase-shift between the gate-to-source voltage and the output current. 6) The MOSFET works as an ideal switch. Therefore, the on-resistance is zero and the off-resistance is infinite. 7) The resonant inductor is divided into and . The resonant filter is an ideal filter for the operating frequency , that is, . Additionally, the reactance of shifts the phase of the output current of the resonant filter. 8) All elements have no parasitic resistance. 9) The switch voltage satisfies the class-E ZVS/ZDS conditions given in (1) and (2). Using the above assumptions, the equivalent circuit for this analysis can be obtained, as shown in Fig. 2(b).
(13) and (14) Substituting
and (2) into (7) and (10), we obtain (15)
From (1) and (12), we have (16) On the other hand, from (13), we can also obtain (17)
B. Waveform Equations The current through the MOSFET device is
Hence, the dc-supply current (7)
, the switch is in the off-state. Therefore, the For switching current is given as (8)
is (18)
From (15) and (18), we obtain (19)
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C. Power Relations The dc-supply power
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and the output power
TABLE II PARAMETERS OF THE MOSFETs
are (20)
and (21) Because of the assumptions 6 and 8, the power conversion efficiency is (22) From (18) and (22), the amplitude of the output current is (23) the amplitude of the output voltage is (24) and the dc-supply current is (25) From (20), (22), and (25), the dc-supply and output powers are (26) The average value of the switch voltage is equal to the dc-supply voltage ,
(27) (27) does not have an analytical solution, which can be expanded partly as follows:
of the other parameters and can be obtained numerically by solving (28) and (30). When the MOSFET is selected, the value of is determined uniquely. In this paper, the MOSFET parameters are obtained from the PSpice MOSFET models. For example, IRF510 PSpice model is given in the Appendix. The parameters , , and are identical to , , and in the MOSFET model, respectively. Additionally, the MOSFET gate-to-drain parasitic capacitance is obtained as . Table II gives values of , , , , and for three types of MOSFETs obtained from PSpice MOSFET models. as functions of Figs. 4 and 5 show and for fixed values of and three types of MOSFETs, respectively. The switch-voltage waveform during the switch-on state is not affected by the current and voltage at the MOSFET gate-to-drain capacitance. It is seen from the analytical expressions that the slope of the voltage across the MOSFET gate-to-drain capacitance during the switch-off state affects the switch-voltage waveform. Therefore, the characteristics for the square gate-to-source voltage can be obtained by replacing by 0. In fact, the equations for are identical to those in [11], which are for the square gate-to-source voltage. It is seen from (19) and Fig. 4 that is always 0.567 rad for the square gate-to-source voltage regardless of the dc-supply voltage. On the other hand, increases as the dc-supply voltage increases for the sinusoidal gate-to-source voltage. Additionally, converges to when the dc-supply voltage approaches 0. It is seen from Fig. 5 that increases as the dc-supply voltage increases and the values of for the square gate-to-source voltage is always larger than those for the sinusoidal gate-to-source voltage at the same specifications. It is also seen from Fig. 5 that the MOSFET gate-to-drain to low. capacitance makes D. Fourier Analysis The voltage across the reactance is expressed as
(28)
(31) The output voltage Fig. 2(b) is
where
of the resonant filter
shown in
(29) From (23) and (25), (15) is transformed to (32)
(30) where , (28) and (30) are regarded as functions of , , , and . If the three of four parameters, which are , , , and , are specified, the values
is the amplitude of
, (33)
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Fig. 4.
V
=V
'
as a function of V =V for fixed values of g . ' depends on for V =V : and is independent of V =V for V =V .
=75
=0
5
Fig. 6. ! C L as a function of !C R for fixed values of g . increases as !C R increases and depends on V =V .
From (34), the reactance
!C L
is given by (37)
Fig. 6 shows as a function of for fixed , , and . It is seen from Fig. 6 that inincreases and depends on the gate-to-sourcecreases as voltage waveform. is, however, almost independent of the MOSFET type. E. Design Equations From the definition of the loaded quality factor tained as
,
is ob-
(38) Fig. 5. !C creases as V
and
R as a function of V =V increases.
=V
for fixed values of g .
!C R in-
From (37) and (38), the inductor
is (39)
is (34)
From the assumption 7 and (39), the resonant capacitance is obtained as
Because the resonant filter is an ideal filter for the operating frequency from the assumption 7, the output voltage of the resonant filter has only the fundamental-frequency component of the switch voltage . Therefore,
(40) In [27], the dc-feed inductance ratio is less than 0.1 is given by
at which the current ripple
(35) (41) From (35), we obtain IV. POWER OUTPUT CAPABILITY The definition of the power output capability (36) From (13), (23), (25), and (36), it is seen is a function of , , and . (36) has no analytical solution but numerical one.
is (42)
where and current at the MOSFET.
are the peak values of voltage and
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The peak switch voltage . Therefore, we have
appears in the range of
(43) where
satisfies (44)
Equation (44) has no analytical solution for rewritten as
but it is
V =V
Fig. 7.
V
(45) From (28), (30), (43), and (45), we can see that and are functions of , , and . Fig. 7 shows as a function of for fixed values of and three types of MOSFETs. It is seen from Fig. 7 that the peak value of the switch voltage depends on the dc-supply voltage and the MOSFET type. The gate-to-source voltage waveform, however, does not affect the peak value of the switch voltage. Additionally, makes the peak value of the switch voltage low. From the MOSFET breakdown voltage and (43), the permissible dc-supply voltages can be obtained. Table III gives the permissible dc-supply voltage for each MOSFET. The breakdown voltage of all the MOSFETs in Table III is 100 V. The peak current appears during the on-state when is in the range of . It is confirmed from Fig. 4 that the range of satisfies this condition. Therefore,
=V as a function of depends only on g and V
V =V =V .
for fixed values of
g.
TABLE III PERMISSIBLE DC-SUPPLY VOLTAGES
increases for a sinusoidal gate-to-source voltage and is always 2.86 when the gate-to-source voltage is a square waveform or . Substituting (43) and (47) into (42), we obtain the equation at the bottom of the page. Fig. 9 shows the power output capability as a function of . It is seen from Fig. 9 that depends on dc-supply voltage, gate-to-source voltage waveform, and MOSFET type. The output capabilities for the square gate-to-source voltage are always higher than those for the sinusoidal gate-to-source voltage.
V. POWER CONVERSION EFFICIENCY (46) From (18) and (46), we obtain (47) Fig. 8 shows It is seen from Fig. 8 that
as a function of . decreases as
In real circuits, the amplifier losses occur in the parasitic resistances of each component. The class-E ZVS/ZDS conditions do is not offer the maximum efficiency when the on-resistance considered [19], [20]. In this paper, we consider the power losses in equivalent series resistance (ESR) of the dc-feed inductor , ESR of the load network , and switch-on resistance as shown in Fig. 10. The ESRs of parasitic capacitances are ignored because they are much smaller than the other ESRs. It
(48)
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7
Fig. 10. The equivalent circuit of the class-E power amplifier including ESRs.
Fig. 8. I I
of V
=I as a function of V =V =I depends on V =V for V =V =V for V =V .
for fixed values of g .
(51)
= 7:5 and is independent
=0
Using (23), (25), and (49)–(51), the power conversion efficiency is
(52)
Fig. 9. c as a function of V V =V , g , and V =V .
=V
for fixed values of g . c depends on
is assumed that the parasitic resistances are small enough not to affect the waveforms. The power loss in is obtained as
It is seen from (52) that the ratio of ESRs to the load resistance determine the power conversion efficiency. From these expressions in this paper, most expressions are composed of , , , , and . It can be stated that these five parameters determine the characteristic of the class-E power amplifier. VI. DESIGN EXAMPLE
(49) Similarly, the power loss
in
is (50)
For power loss
, the switching current is zero. Hence, the in the switch-on resistance is
In this section, two design examples were given, one was for the sinusoidal gate-to-source voltage and the other was for the square gate-to-source voltage. The design specifications of the class-E power amplifier were dc-supply voltage V, operating frequency MHz, and loaded quality factor . The IRF510 MOSFET was used as a switching device. From Table III, it is confirmed that the IRF510 MOSFET is suitable for the specifications from the breakdown voltage point of view. The parameters of the MOSFET could be obtained from PSpice MOSFET model given in Table II. For the sinusoidal gate-to-source voltage, the amplitude of the V. Therefore, we gate-to-source voltage was specified as had and . From (28) and (30), and . Hence, the load we obtained resistance was
(53)
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TABLE IV THEORETICAL PREDICTIONS, PSPICE SIMULATIONS, AND EXPERIMENTAL MEASUREMENTS FOR A SINUSOIDAL GATE-TO-SOURCE VOLTAGE
3Difference means the comparison between the theoretical method and the measured method.
Following the design equations in Section II-E, the element values could be obtained as given in Table IV. From (26), we had W. could be obtained from (47). From (45), we obtained rad. Therefore, we had . As a result, the power output capability was 0.086 from (42). for 3% ripple ratio and were derived theoretically by using the calculation method in [21] and [22], respectively. Additionally, was obtained from the PSpice model of the IRF510. From (52) and these ESR values, we obtained . The theoretical predictions for the sinusoidal gate-to-source voltage were summarized in Table IV. Following a similar procedure described the above, we could obtain the design values for the square gate-to-source voltage, , as given in Table V. that is Fig. 11 shows the waveforms obtained from theoretical expressions, PSpice simulations, and circuit experiments. The circuit topology of the PSpice simulation includes the ESRs as shown in Fig. 10. In the circuit experiments, the driver circuits were designed with the consideration of the MOSFET gate resistance and the gate-to-source capacitance [28], [29]. The element values of passive elements including ESRs were measured by HP4284A impedance meter. The ESR of the dc-feed inductor was measured at dc, which followed the experimental measurements in [23]. We confirmed that the self-resonant frequency (SRF) of the dc-feed inductor was about three times higher than the operating frequency. It is seen from Fig. 11 that the switch-voltage waveforms of both the PSpice simulations and the circuit experiments satisfied the class-E ZVS/ZDS conditions and agreed with the theoretical waveforms well. In the PSpice simulation and the circuit experiment for the sinusoidal gate-to-source voltage, it seems that the switch-on duty ratio is a little lower than that of the theoretical prediction [24], [25]. This is because the assumption for the sinusoidal gate-to-source voltage is only valid if the power gain of the transistor is infinite or the amplitude of the driving voltage is infinite. Tables IV and V also give the PSpice-simulation and
TABLE V THEORETICAL PREDICTIONS, PSPICE SIMULATIONS, AND EXPERIMENTAL MEASUREMENTS FOR A SQUARE GATE-TO-SOURCE VOLTAGE
3 Difference means the comparison between the theoretical method and the measured method.
for experimental results. In these tables, the output power the simulations and the experiments is the sum of powers at all harmonics [26]. The power gain is (54) where is the input power as shown in Fig. 2(a). Additionally, the total harmonic distortion (THD) is
THD
(55)
where is a root-mean-square value of the th harmonic in the output voltage , respectively. For obtaining measured and THD values, we used the waveform data of the outputvoltage from Textronix TDS3014B. The PSpice-simulation and experimental measurements agreed with the theoretical predictions quantitatively. These results verify the derived expressions. Fig. 12 shows the PSpice-simulation waveforms for the square gate-to-source voltage, MHz, V, V, pF, and fixed values of and without ESRs. Table VI gives the element values for these simulations. It is seen from Fig. 12 that only the switch voltage waveform for and satisfied the class-E ZVS/ZDS conditions. It can be stated from these results that it is important and effective to consider the MOSFET gate-to-drain capacitance and the nonlinearity of the MOSFET drain-to-source capacitance. VII. CONCLUSION This paper has presented expressions for the waveforms and design equations for achieving the ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. Two design examples are given along with the PSpice-simulation and
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. WEI et al.: DESIGN OF CLASS-E AMPLIFIER WITH MOSFET LINEAR GATE-TO-DRAIN
9
the linear and nonlinear shunt capacitance and the MOSFET gate-to-drain capacitance is an important problem we should address in the future. APPENDIX The MOSFET model used in this paper is obtained from the default package of PSpice, which is licensed by Cadence. The IRF510 MOSFET parameters are shown as follows. .model IRF510 NMOS(Level=3 Gamma=0 Delta=0 Eta=0 Theta=0 Kappa=0.2 Vmax=0 Xj=0 Tox=100n Uo=600 Phi=.6 Rs=.4508 Kp=20.68u W=0.64 L=2u Vto=3.697 Rd=21.08m Rds=444.4K Cbd=366.5p Pb=.8 Mj=.5 Fc=.5 Cgso=600.5p Cgdo=62.71p Rg=2.977 Is=202.9f N=1 Tt=135n) Int’l Rectifier pid=IRFC110 case=TO220 88-08-25 bam creation REFERENCES
Fig. 11. Waveforms obtained from theoretical expressions (dashed line), PSpice simulations (solid line), and circuit experiments (dotted line). (a) For the sinusoidal gate-to-source voltage. (b) For the square gate-to-source voltage.
Fig. 12. Switch-voltage waveforms for the element values given in Table VI.
ELEMENT VALUES FOR f
TABLE VI
= 4 MHz, V = 15 V, V = 0:8 V, V = 0, AND C = 366:5 pF
experimental results. The switch-voltage waveforms obtained from PSpice simulations and experimental measurements achieved the class-E ZVS/ZDS conditions, which verify the expressions given in this paper. In this paper, we used a fabricated MOSFET in the circuit experiments. The parameter for the shunt capacitance was fixed and not controllable when the MOSFET was selected. Therefore, it was not required to specify the output power or the load resistance. If it is allowed to add the linear external shunt capacitance or to design the MOSFET with the required parasitic-capacitance value, either the output power or the load resistance can be specified. The analysis of the class-E amplifier with
[1] N. O. Sokal and A. D. Sokal, “Class E—A new class of high-efficiency tuned single-ended switching power amplifiers,” IEEE J. Solid-State Circuits, vol. SC-10, no. 3, pp. 168–176, Jun. 1975. [2] F. H. Raab, “Effects of circuit variations on the class-E tuned power amplifier,” IEEE J. Solid-State Circuits, vol. SC-13, no. 2, pp. 239–247, Apr. 1978. [3] M. K. Kazimierczuk, “Class E tuned power amplifier with shunt inductor,” IEEE J. Solid-State Circuits, vol. SC-16, no. 1, pp. 2–7, Feb. 1981. [4] M. K. Kazimierczuk, “Effects of the collector current fall time on the class E tuned power amplifier,” IEEE J. Solid-State Circuits, vol. SC-18, no. 2, pp. 181–193, Apr. 1983. [5] M. K. Kazimierczuk, “Collector amplitude modulation of the class E tuned power amplifier,” IEEE Trans. Circuits Syst., vol. CAS-31, no. 6, pp. 543–549, Jun. 1984. [6] M. K. Kazimierczuk and K. Puczko, “Exact analysis of class E tuned power amplifier at any Q and switch duty cycle,” IEEE Trans. Circuits Syst., vol. CAS-34, no. 2, pp. 149–159, Feb. 1987. [7] M. K. Kazimierczuk and K. Puczko, “Class E tuned power amplifier with antiparallel diode or series diode at switch, with any loaded Q and switch duty cycle,” IEEE Trans. Circuits Syst., vol. 36, no. 9, pp. 1201–1209, Sep. 1989. [8] D. K. Choi and S. I. Long, “The effect of transistor feedback capacitance in class-E power amplifiers,” IEEE Trans. Circuits Syst. I, Fumdam. Theory Appl., vol. 50, no. 12, pp. 1556–1559, Dec. 2003. [9] Z. Liao and X. Zhu, “Analysis and simulation of feedback capacitance effect in class-E power amplifiers,” in Proc. IEEE ICMMT, Nanjing, China, Apr. 2008, pp. 1495–1498. [10] D. K. Choi and S. I. Long, “A physically based analytic model of FET class E power amplifiers-designing for maximum PAE,” IEEE Trans. Microw. Theory Tech., vol. 47, no. 9, pp. 1712–1720, Sep. 1999. [11] X. Wei, H. Sekiya, S. Kuroiwa, T. Suetsugu, and M. K. Kazimierczuk, “Effect of MOSFET gate-to-drain parasitic capacitance on class-E power amplifier,” in Proc. IEEE ISCAS, Paris, France, Jun. 2010, pp. 3200–3203. [12] M. J. Chudobiak, “The use of parasitic nonlinear capacitors in class-E amplifiers,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 41, no. 12, pp. 941–944, Dec. 1994. [13] T. Suetsugu and M. K. Kazimierczuk, “Comparison of class E amplifier with nonlinear and linear shunt capacitance,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 8, pp. 1089–1097, Aug. 2003. [14] T. Suetsugu and M. K. Kazimierczuk, “Analysis and design of class E amplifier with shunt capacitance composed of nonlinear and linear shunt capacitances,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 7, pp. 1261–1268, Jul. 2004. [15] H. Sekiya, Y. Arifuku, H. Hase, J. M. Lu, and T. Yahagi, “Investigation of class-E amplifier with nonlinear capacitance for any output Q and finite DC-feed inductance,” IEICE Trans. Fundam., vol. E89-A, no. 4, pp. 873–881, Apr. 2006. [16] A. Mediano, P. M. Gaudo, and C. K. Bernal, “Design of class E amplifier with nonlinear and linear shunt capacitances for any duty cycle,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 3, pp. 484–492, Mar. 2007.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
[17] C. Yoo and Q. Huang, “A common-gate switched 0.9-W class-E power amplifier with 41% PAE in 0.25- m CMOS,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 823–830, May 2001. [18] J. Ramos, K. Francken, G. G. E. Gielen, and M. S. J. Steyaert, “An efficient, fully parasitic-aware power amplifier design optimization tool,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 8, pp. 1526–1534, Aug. 2005. [19] N. O. Sokal, “Class E RF power amplifiers,” QEX, no. 204, pp. 9–20, Jan./Feb. 2001. [20] F. del Aguila, P. Pala, J. Bonet, and R. Giralt, “A technique for maximum efficiency class-E amplifier design,” in Proc. ECCTD’03, Cracow, Poland, Sep. 2003, pp. 281–284. [21] H. Sekiya and M. K. Kazimierczuk, “Design of RF-choke inductors using core geometry coefficient,” presented at the EMCW 2009, Nashville, TN, Sep. 2009. [22] N. Sagawa, H. Sekiya, and M. K. Kazimierczuk, “Computer-aided design for class-E switching circuits taking into account optimized inductor design,” in Proc. IEEE APEC, Feb. 2010, pp. 2212–2219. [23] K. Shinoda, T. Suetsugu, M. Matsuo, and S. Mori, “Analysis of phasecontrolled resonant DC-AC inverters with class E amplifier and frequency multipliers,” IEEE Trans. Ind. Electron., vol. 45, no. 3, pp. 412–420, Jun. 1998. [24] D. Kessler and M. K. Kazimierczuk, “Power losses and efficiency of class-E power amplifier at any duty ratio,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 9, pp. 1675–1689, Sep. 2004. [25] T. Suetsugu and M. K. Kazimierczuk, “Maximum operating frequency of class-E amplifier at any duty ratio,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 8, pp. 768–770, Aug. 2008. [26] M. K. Kazimierczuk, “Exact analysis of class E tuned power amplifier with only one inductor and one capacitor in load network,” IEEE J. Solid-State Circuits, vol. SC-18, no. 2, pp. 214–221, Apr. 1983. [27] M. K. Kazimierczuk, RF Power Amplifiers. New York: Wiley, 2008. [28] J. Ebert and M. K. Kazimierczuk, “Class E high-efficiency tuned power oscillator,” IEEE J. Solid-State Circuits, vol. SC-16, no. 2, pp. 62–66, Apr. 1981. [29] H. Hase, H. Sekiya, J. Lu, and T. Yahagi, “Novel design procedure for MOSFET class E oscillator,” IEICE Trans. Fundam., vol. E87-A, no. 9, pp. 2241–2247, Sep. 2004. Xiuqin Wei (S’10) was born in Fujian, China, on December 7, 1983. She received the B.E. degree from Fuzhou University, China, in 2005. She is currently working toward the Ph.D. degree in the Graduate School of Advanced Integration Science, Chiba University, Chiba, Japan. Her research interests include high-frequency power amplifiers.
Hiroo Sekiya (S’97–M’01) was born in Tokyo, Japan, on July 5, 1973. He received the B.E., M.E., and Ph.D. degrees in electrical engineering from Keio University, Yokohama, Japan, in 1996, 1998, and 2001 respectively. Since April 2001, he has been with Chiba University; he is currently an Assistant Professor at the Graduate School of Advanced Integration Science, Chiba University, Chiba, Japan. Since February 2008, he has been also with Electrical Engineering, Wright State University, Dayton, OH, as a Visiting Scholar. His research interests include high-frequency high-efficiency tuned power amplifiers, resonant dc/dc power converters, dc/ac inverters, and digital signal processing for wireless communication. Dr. Sekiya is a member of the Institute of Electronics, Information and Communication Engineers (IEICE) of Japan, Information Processing Society of Japan (IPSJ), Society Information Theory and its Application (SITA), Japan, and Research Institute of Signal Processing (RISP), Japan.
Shingo Kuroiwa received the B.E., M.E., and D.E. degrees in electro-communications from the University of Electro Communications, Tokyo, Japan, in 1986, 1988, and 2000, respectively. From 1988 to 2001, he was a Researcher at the KDD R & D Laboratories. From 2001 to 2007, he was an Associate Professor of Institute of Technology and Science at the University of Tokushima, Japan. Since 2007, he has been with Chiba University, Chiba, Japan, where he is currently a Professor of Graduate School of Advanced Integration Science. His current research interests include speech recognition, speaker recognition, signal processing, and information retrieval. Prof. Kuroiwa is a member of the ISCA, IEICE, IPSJ, and ASJ.
Tadashi Suetsugu (S’92-M’95-SM’02) received the B.E., M.E., and Ph.D. degrees in electrical engineering from the Department of Electrical Engineering, Keio University, Yokohama, Japan, in 1990, 1992, and 1995, respectively. He was an Assistant Professor from 1995 to 1998 with the Department of Electronics, Fukuoka University, Japan. In 2001–02, he was a Visiting Professor with the Department of Electrical Engineering, Wright State University, Dayton, OH. Since 1998, he has been with the Department of Electronics Engineering and Computer Science, Fukuoka University, Fukuoka, Japan, where he is currently an Associate Professor. His research interests are in high-frequency high-efficiency switching-mode tuned power amplifiers, resonant dc/dc power converters, dc/ac inverters, high-frequency rectifiers, numerical simulation of switching circuits, and power line communications. Dr. Suetsugu is a member of Institute of Electronics, Information, and Communication Engineers (Japan).
Marian K. Kazimierczuk (M’91-SM’91-F’04) received the M.S., and Ph.D., and D.Sci. degrees in electronics engineering from the Department of Electronics, Technical University of Warsaw, Warsaw, Poland, in 1971, and 1978, and 1984, respectively. He was a Teaching and Research Assistant from 1972 to 1978 and Assistant Professor from 1978 to 1984 with the Department of Electronics, Institute of Radio Electronics, Technical University of Warsaw, Poland. In 1984, he was a Project Engineer for Design Automation, Inc., Lexington, MA. In 1984–85, he was a Visiting Professor with the Department of Electrical Engineering, Virginia Polytechnic Institute and State University, VA. Since 1985, he has been with the Department of Electrical Engineering, Wright State University, Dayton, OH, where he is currently a Professor. His research interests are in high-frequency high-efficiency switchingmode tuned power amplifiers, resonant and PWM dc/dc power converters, dc/ac inverters, high-frequency rectifiers, electronic ballasts, modeling and control of converters, high-frequency magnetics, power semiconductor devices. Prof. Kazimierczuk received the IEEE Harrell V. Noble Award for his contributions to the fields of aerospace, industrial, and power electronics, in 1991. He was and is an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I, and served as an Associate Editor for the Journal of Circuits, Systems, and Computers. He was a member of the Superconductivity Committee of the IEEE Power Electronics Society. He was a chair of the CAS Technical Committee of Power Systems and Power Electronics Circuits in 2001–2002. He is a member of Tau Beta Pi.
