Design of Low Area List Successive Cancellation Decoder for Polar ...
Design of Low Area List Successive Cancellation Decoder for Polar Codes Zheyan Piao
Jin-Gyun Chung
Div. of Electronic Engr. Chonbuk National University Jeonju, South Korea [email protected]
Div. of Electronic Engr. Chonbuk National University Jeonju, South Korea [email protected]
Abstract— Polar codes are the first constructive and provable capacity-achieving codes. Compared to conventional successive cancellation (SC) decoders, SCL (list SC) decoders have performances very close to those of the maximum-likelihood (ML) decoders. In SCL decoders with large list size, however, the hardware increase is a severe problem since an SCL decoder with list size L consists of L copies of SC decoders. In this paper, a low area SCL decoder architecture is proposed. It is shown that the proposed SCL decoder can reduce about 70% merged processing elements compared with conventional SCL decoders when the list size is larger than 32.
controlled. By the analysis of SC decoding algorithm, it can be shown that the connections between the merged PEs in stage 1 and the merged PEs in stage 2 can be either type 1 or type 2 in Fig. 4. In addition, it should be noted that type 1 and type 2 Decoding part Stage 1
Input signal from channel
Stage 1
Stage 2 … Stage log2N Feedback part
decoded
Metric codeword & Sorting
Stage 2 … Stage log2N Feedback part
Lth SC decoder
INTRODUCTION
L candidate codewords
Polar codes, proposed by Arikan [1], are the first constructive and provable capacity-achieving error-correcting codes. Polar codes can be decoded using successive cancellation (SC) decoders [1]. List SC (SCL) decoder, an improved version of SC decoder, can approach the performances of ML decoder with large list size L [2-4]. However, since an SCL decoder consists of L copies of SC decoders, the hardware increase is a nonnegligible problem. In this paper, we propose a low area SCL decoder design method by reducing the number of merged processing elements (PEs). II.
1st SC decoder Stage 1
2nd SC decoder
Keywords-polar codes; list SC decoder; pre-computation; low area
I.
Stage 2 … Stage log2N Feedback part
Figure 1. Block diagram of a conventional SCL decoder.
,
,
,
, , ,
PROPOSED LIST SC DECODER
Fig. 1 shows the block diagram of a conventional SCL decoder with list size L. In general, a size-L (n, k) SCL decoder consists of Metric & Sorting part and Decoding part. Decoding part consists of the combination of L copies of (n, k) SC decoders as can be seen in Fig. 1. Fig. 2 shows an SC decoder architecture [5]. Fig. 3 shows the block diagram of the merged PE in Fig. 2. As can be seen in Fig. 2, the number of merged PEs in each stage is decreased as the stage number s is increased. More specifically, for code length N, the required number of merged PEs in stage s is N/2s, s = 1, 2, ···, log . It can be seen that stages 1 and 2 require about 75% of the total number of the merged PEs used in the SC decoder. Thus, we try to reduce the number of the merged PEs in stages 1 and 2.
,
,
As can be seen in Fig. 1, stage 1 of each SC decoder in Decoding part receives the same input signals. Thus, the output signals from one stage 1 block can be shared with other SC decoders if the connection of the stage 1 output signals is well-
-page number-
,
, ,
, ,
,
Figure 2. Architecture of 8-bit SC decoder (M: memory).
y1
Merged PE F
y2
out_F out_G0
out_F = y1 x y2+1/y1+y2
out_G1
out_G1 = y2 / y1
G
out_G0 = y1 x y2
Figure 3. Block diagram of merged PE.
ISOCC 2015
Figure 4. Two merged PE connection types between neighboring stages in SC decoder.
,
,
,
, ,
,
,
Figure 6. Architecture of the proposed 8-bit SCL decoder with L=4. Table I. Comparison of SCL decoders Complexity # of merged PEs
cannot occur simultaneously. As opposed to type 1, type 2 can have four different cases depending upon signals us(1) and us(2). Thus, instead of L stage 2 blocks, only four stage 2 blocks are sufficient to compute all the necessary stage 2 output signals as shown in Fig. 5. When type 1 is selected, only one stage 2 block is used. Otherwise, four stage 2 blocks are used to pre-compute four different cases corresponding to the signals us(1) and us(2). In each stage 3, proper input signals are selected from the lookup table in stage 2 depending on the selection signals from the feedback part. Therefore, in the proposed design, as shown in Fig. 5, only one stage 1 block and four stage 2 blocks are needed. The rest of the stages require L blocks as in the conventional SCL decoders. Fig. 6 shows the architecture of proposed SCL decoder with L=4. Table I compares the architecture in [4] and the proposed architecture for N=1024 SCL decoder. The two designs in Table I have the same computation latency. When the list size L is larger than 32, the proposed design can reduce about 70% merged PEs compared with the design in [4]. III.
CONCLUSIONS
N=1024
Figure 5. Block diagram of proposed decoding part in SCL decoder.
Proposed Design
3 4
∙
4
1
2
4
4
4
L=8
8,184
3,576(43.7%)
L=16
16,368
5,616(34.3%)
L=32
32,736
9,696(29.6%)
L=128
130,944
34,176(26.3%)
1
ACKNOWLEDGMENT This work was partly supported by the IT R&D program of MOTIE/KEIT. [10044092, Development of Core IPs of OFDM PHY and FR Transceiver for 60GHz Wireless LAN/PAN in application of 7Gbps Wireless Multimedia Services] and the Brain Korea 21 PLUS Project, National Research Foundation of Korea. REFERENCES [1]
[2] [3]
In this paper, we presented a low area SCL decoder architecture. By the proposed design, the number of merged PEs in stages 1 and 2 can be significantly reduced compared with conventional SCL decoders. The proposed architecture can be efficiently used for SCL decoders with large list size L.
[4]
1
[4]
[5]
E. Arikan, “Channel polarization: a method for constructing capacityachieving codes for symmetric binary-input memoryless channels,” IEEE Trans. On Inf. Theory, vol. 55, no. 7, pp. 3051-3073, July 2009. I. Tal and A. Vardy, “List decoding of polar codes,” in Proc. IEEE Inter. Symp. On Info. Theory(ISIT), pp. 1-5, 2011. K. Chen, K. Niu, and J. Lin, “List successive cancellation decoding of polar codes,” Electronics Letters, vol. 48, pp. 500-501, 2012. Chuan Zhang, Zhongfeng Wang, Xiaohu You, Bo Yuan, “Efficient adaptive list successive cancellation decoder for polar codes,” Signals, Systems and Computers, pp. 126-130, 2014 C. Zhang and K. K. Parhi, “Low-latency sequential and overlapped architectures for successive cancellation polar decoders,” IEEE Trans. on Signal Proc., vol. 61, pp. 2429-2441, 2013.
1
-page number-
ISOCC 2015
Jin-Gyun Chung
Div. of Electronic Engr. Chonbuk National University Jeonju, South Korea [email protected]
Div. of Electronic Engr. Chonbuk National University Jeonju, South Korea [email protected]
Abstract— Polar codes are the first constructive and provable capacity-achieving codes. Compared to conventional successive cancellation (SC) decoders, SCL (list SC) decoders have performances very close to those of the maximum-likelihood (ML) decoders. In SCL decoders with large list size, however, the hardware increase is a severe problem since an SCL decoder with list size L consists of L copies of SC decoders. In this paper, a low area SCL decoder architecture is proposed. It is shown that the proposed SCL decoder can reduce about 70% merged processing elements compared with conventional SCL decoders when the list size is larger than 32.
controlled. By the analysis of SC decoding algorithm, it can be shown that the connections between the merged PEs in stage 1 and the merged PEs in stage 2 can be either type 1 or type 2 in Fig. 4. In addition, it should be noted that type 1 and type 2 Decoding part Stage 1
Input signal from channel
Stage 1
Stage 2 … Stage log2N Feedback part
decoded
Metric codeword & Sorting
Stage 2 … Stage log2N Feedback part
Lth SC decoder
INTRODUCTION
L candidate codewords
Polar codes, proposed by Arikan [1], are the first constructive and provable capacity-achieving error-correcting codes. Polar codes can be decoded using successive cancellation (SC) decoders [1]. List SC (SCL) decoder, an improved version of SC decoder, can approach the performances of ML decoder with large list size L [2-4]. However, since an SCL decoder consists of L copies of SC decoders, the hardware increase is a nonnegligible problem. In this paper, we propose a low area SCL decoder design method by reducing the number of merged processing elements (PEs). II.
1st SC decoder Stage 1
2nd SC decoder
Keywords-polar codes; list SC decoder; pre-computation; low area
I.
Stage 2 … Stage log2N Feedback part
Figure 1. Block diagram of a conventional SCL decoder.
,
,
,
, , ,
PROPOSED LIST SC DECODER
Fig. 1 shows the block diagram of a conventional SCL decoder with list size L. In general, a size-L (n, k) SCL decoder consists of Metric & Sorting part and Decoding part. Decoding part consists of the combination of L copies of (n, k) SC decoders as can be seen in Fig. 1. Fig. 2 shows an SC decoder architecture [5]. Fig. 3 shows the block diagram of the merged PE in Fig. 2. As can be seen in Fig. 2, the number of merged PEs in each stage is decreased as the stage number s is increased. More specifically, for code length N, the required number of merged PEs in stage s is N/2s, s = 1, 2, ···, log . It can be seen that stages 1 and 2 require about 75% of the total number of the merged PEs used in the SC decoder. Thus, we try to reduce the number of the merged PEs in stages 1 and 2.
,
,
As can be seen in Fig. 1, stage 1 of each SC decoder in Decoding part receives the same input signals. Thus, the output signals from one stage 1 block can be shared with other SC decoders if the connection of the stage 1 output signals is well-
-page number-
,
, ,
, ,
,
Figure 2. Architecture of 8-bit SC decoder (M: memory).
y1
Merged PE F
y2
out_F out_G0
out_F = y1 x y2+1/y1+y2
out_G1
out_G1 = y2 / y1
G
out_G0 = y1 x y2
Figure 3. Block diagram of merged PE.
ISOCC 2015
Figure 4. Two merged PE connection types between neighboring stages in SC decoder.
,
,
,
, ,
,
,
Figure 6. Architecture of the proposed 8-bit SCL decoder with L=4. Table I. Comparison of SCL decoders Complexity # of merged PEs
cannot occur simultaneously. As opposed to type 1, type 2 can have four different cases depending upon signals us(1) and us(2). Thus, instead of L stage 2 blocks, only four stage 2 blocks are sufficient to compute all the necessary stage 2 output signals as shown in Fig. 5. When type 1 is selected, only one stage 2 block is used. Otherwise, four stage 2 blocks are used to pre-compute four different cases corresponding to the signals us(1) and us(2). In each stage 3, proper input signals are selected from the lookup table in stage 2 depending on the selection signals from the feedback part. Therefore, in the proposed design, as shown in Fig. 5, only one stage 1 block and four stage 2 blocks are needed. The rest of the stages require L blocks as in the conventional SCL decoders. Fig. 6 shows the architecture of proposed SCL decoder with L=4. Table I compares the architecture in [4] and the proposed architecture for N=1024 SCL decoder. The two designs in Table I have the same computation latency. When the list size L is larger than 32, the proposed design can reduce about 70% merged PEs compared with the design in [4]. III.
CONCLUSIONS
N=1024
Figure 5. Block diagram of proposed decoding part in SCL decoder.
Proposed Design
3 4
∙
4
1
2
4
4
4
L=8
8,184
3,576(43.7%)
L=16
16,368
5,616(34.3%)
L=32
32,736
9,696(29.6%)
L=128
130,944
34,176(26.3%)
1
ACKNOWLEDGMENT This work was partly supported by the IT R&D program of MOTIE/KEIT. [10044092, Development of Core IPs of OFDM PHY and FR Transceiver for 60GHz Wireless LAN/PAN in application of 7Gbps Wireless Multimedia Services] and the Brain Korea 21 PLUS Project, National Research Foundation of Korea. REFERENCES [1]
[2] [3]
In this paper, we presented a low area SCL decoder architecture. By the proposed design, the number of merged PEs in stages 1 and 2 can be significantly reduced compared with conventional SCL decoders. The proposed architecture can be efficiently used for SCL decoders with large list size L.
[4]
1
[4]
[5]
E. Arikan, “Channel polarization: a method for constructing capacityachieving codes for symmetric binary-input memoryless channels,” IEEE Trans. On Inf. Theory, vol. 55, no. 7, pp. 3051-3073, July 2009. I. Tal and A. Vardy, “List decoding of polar codes,” in Proc. IEEE Inter. Symp. On Info. Theory(ISIT), pp. 1-5, 2011. K. Chen, K. Niu, and J. Lin, “List successive cancellation decoding of polar codes,” Electronics Letters, vol. 48, pp. 500-501, 2012. Chuan Zhang, Zhongfeng Wang, Xiaohu You, Bo Yuan, “Efficient adaptive list successive cancellation decoder for polar codes,” Signals, Systems and Computers, pp. 126-130, 2014 C. Zhang and K. K. Parhi, “Low-latency sequential and overlapped architectures for successive cancellation polar decoders,” IEEE Trans. on Signal Proc., vol. 61, pp. 2429-2441, 2013.
1
-page number-
ISOCC 2015
