Design of SRAM PUF with Improved Uniformity and Reliability Utilizing ...
Design of SRAM PUF with Improved Uniformity and Reliability Utilizing Device Aging Effect Achiranshu Garg and Tony T. Kim VIRTUS, School of EEE Nanyang Technological University Singapore, 639798 [email protected]; [email protected] Abstract—SRAM Physical Unclonable Function (PUF) makes use of efficient silicon fabrication process where duplication of exact replica devices is difficult. One of the major issues with SRAM-PUF is the reliability and uniformity of the start-up pattern with environmental fluctuations. This paper presents a technique for improving uniformity (distribution of 1's & 0's) and reliability (variations in power-up patterns) of SRAM-PUF utilizing aging effects (mainly NBTI). The proposed technique maintains the uniformity of SRAM-PUF by controlling the polarity of the aging in SRAM arrays. The reliability is controlled by further injecting aging to the SRAM arrays after achieving target uniformity. Keywords— Static Random Access Memory (SRAM); Physical Unclonable Function (PUF); device aging
I. INTRODUCTION In recent years, digital systems are becoming part of everyday life - ranging from mobile phones, appliances & security systems. These devices store personalized data which should be protected from external attack. In addition, short product-cycle time forces semiconductor vendors to outsource IPs to other SoC vendors where design theft might result in tremendous loss of revenue to IP owners [1]. Therefore, digital electronics and IPs need robust security mechanisms without significant overheads in power and silicon area. Conventional security systems (e.g. RFID tags, smart cards) use non-volatile memory (NVM) based security mechanisms in which binary encrypted keys are stored and authenticated to access stored secret information [2]. However, with the development of new (invasive & non-invasive) tampering methods such as micro-probing, laser cutting, glitch attacks and power analysis, it is possible for attackers to steal the binary keys for authentication. To prevent such physical attacks, researchers have developed various tamper-sensing methods where meshed sensors are used to detect any tampering on the ICs. The limitation of the sensor-mesh is that it cannot detect intrusion when the circuit power is off and the hardwired information can be easily stolen [3]. To address the above issue, hardware-intrinsic-security (HIS) has been investigated by researchers for improving hardware security [4], [5]. Gassend et al. introduced Physical Unclonable Functions (PUFs) based on the concept of random functions in silicon [4]. To be brief, PUF is a method of producing fingerprints of physical objects based on their random variations during manufacturing. The amount of random variations increases with semiconductor technology scaling. Fig. 1 illustrates a sample security system where PUF is
978-1-4799-3432-4/14/$31.00 ©2014 IEEE
Fig. 1. Activation code and key generation using PUF.
employed for activation code generation and key generation. PUF is involved in both activation code generation and key generation. Since the outputs of the PUF are complex and untraceable, activation codes and keys cannot be traced either.
Various types of PUFs such as optical PUF, delaybased PUF, butterfly PUF and SRAM-PUF have been developed. Literature reveals that SRAM-PUF has many advantages over other PUF types in point of stability and reliability [6],[7],[8]. In addition, temperature variations in SRAM PUF have a common-mode effect, thus the impact of temperature variations on the output is insignificant [9]. Structurally, two cross-coupled inverters are symmetrical in an SRAM bit-cell and ideally the SRAM cell should be in the meta-stable state during a start-up phase. However, the devices in the cross-coupled inverters have mismatches due to the manufacturing variations. The small mismatches in the cross-coupled inverters will be amplified by the positive feedback of the cross-coupled inverters and will eventually generate either logic ‘1’ or logic ‘0’. Assuming random device variations, SRAM cells will also generate logic ‘1’ and logic ‘0’ randomly with the probability of 0.5. This make a binary output string read from an SRAM array unique, random and non-traceable. However, under large systematic process variations, the number of logic ‘1’ in an SRAM array can be much greater than that of logic ‘0’ or vice versa after power-up. In this case, the randomness in of an output string from an SRAM array is degraded. In addition, if device mismatches are insignificant, an output string can vary considerably between power-up phases. This degrades the reliability of the SRAM-PUF. In this work, we propose a methodology utilizing aging injection for addressing the above issues in the SRAM-PUF. To simulate the effect of NBTI injection on SRAM-PUF, we modified the transistor parameters considering the effects of NBTI on MOSFET from standard literature [10],[11].
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II. PROPOSED METHODOLOGY This work proposes an aging-injection-based methodology to address the uniformity and the reliability issues of SRAMPUF. The proposed methodology utilizes an aging mechanism called negative-bias-temperature-instability (NBTI) to adjust SRAM-PUF more uniform and reliable. NBTI has been considered as a primary aging mechanism degrading device and circuit performance in advanced CMOS technology. As the name suggests NBTI occurs when a PMOS device is subjected to negative bias (i.e. Vgs = -Vdd) on gate under high operating temperatures. The main impact of NBTI is the increase in the device threshold voltage. In high-k/metal-gate process technology, positive-bias-temperature-instability (PBTI) in NMOS devices also becomes prominent. However, only NBTI will be considered in this work for simplicity. The details of the proposed methodology are explained in the following sections.
Fig. 2. Cell Flip in power-up due to aging (NBTI) injection. |Vtp1| and |Vtp2 | represents the threshold voltage of P1 and P2 respectively before ageing. Also, |V'tp1| and |V'tp2 | represents threshold voltage of P1 and P2 after ageing.
A. Uniformity Improvement The uniformity of SRAM-PUF is defined as the distribution of data 1's and 0's in an SRAM array after powerup. Even distribution of data 1's and 0’s ensures a strong security key which is difficult to be replicated. Fig. 2 shows a typical SRAM cell with two cross coupled inverters connected back to back. The initial power-up value of the SRAM cell depends on the device mismatches in the cross-coupled inverters (P1 and P2, N1 and N2). In general, we expect the SRAM cells are initialized with data ‘1’ and ‘0’ evenly. However, under systematic process variations, the SRAM cells can have much more data ‘1’ than data ‘0’ or vice versa, which deteriorates the robustness of the SRAM-PUF. To address this, we propose an uniformity improvement technique utilizing aging (i.e. NBTI in this work) injection. The polarity and the amount of aging change the mismatches in the cross-coupled inverters and accordingly redistribute the number of data ‘1’s and ‘0’s. Fig. 3 shows the effect of aging injection on the power-up output of an SRAM cell. If we assume P1 is weaker than P2 (i.e. |Vtp1| > |Vtp2|), OUT will be data ‘0’ after power-up without considering other nonidealities as shown in Fig. 4(a). If the same cell is subjected to NBTI stress (high voltage and high temperature), P2 (Vgs = Vdd) will experience NBTI stress resulting in the increase in |Vtp2|. In subsequent power-up sequences after the aging, P2 will become weaker than P1 and hence the cell will power up with data ‘1’ as depicted in Fig. 4(b). This indicates that we can control the power-up output of an SRAM cell through the effect of ageing (NBTI). The above result can be applied to an SRAM array to improve the uniformity. Assume that a non-uniform SRAM-
Fig. 2. SRAM cell for SRAM-PUF implementation.
(a)
(b)
Fig. 3. (a) Initial power-up behavior of SRAM cell (b) flipped cell after aging injection.
PUF array is fabricated where the number of data ‘1’s is unacceptably different from that of data ‘0’s. For example, 70% of the total cells in an SRAM array are initialized with data ‘1’ while 30% of the cells have data ‘0’ after the initial power-up. Such an output distribution is vulnerable to attack and needs to be improved. In this case, we can apply aging injection to the SRAM array, leading to data flipping in some SRAM cells after power-up. This will reduce the difference between the number of ‘1’s and that of ‘0’s. The above aging injection can be repeated until the power-up data pattern is within the desired range. B. Reliability Improvement Another critical parameter to be considered in robust SRAM_PUS is reliability. In SRAM-PUF, reliability is defined as the capability of an SRAM array for repeating same power-up patterns between repeated power-up sequences. For ideal reliability, the SRAM cells should generate same values whenever SRAM-PUF is powered up. As explained, a powerup value of an SRAM cell is decided by the mismatches between corresponding cross-coupled inverters. If the mismatch between the two inverters is minimal, the start-up value of the cell can be random. Even though minimizing the mismatch in SRAM cells is highly desired in the conventional SRAM design, it is not so critical in achieving higher SRAMPUF reliability. Therefore, the mismatch has to be revisited in the design of SRAM-PUF.
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Fig. 5. Reliability enhancement using aging injection after data flipping.
Fig. 6. Proposed methodology for robust SRAM-PUF implementation.
In this work, we propose a methodology for improving SRAM-PUF reliability by injecting additional aging after achieving target uniformity. The proposed reliability improvement methodology aims to increase the threshold mismatch by applying NBTI aging to one inverter in each SRAM cell. Fig. 5 illustrates the effect of the proposed method on SRAM-PUF reliability. Since |Vtp1| is equal or slightly larger than |Vtp2|, the power-up data will be almost random. Although SRAM-PUF requires randomness in the power-up pattern of an SRAM array, it doesn’t require randomness in the powerup data of each SRAM cell. In this case, we can enhance the mismatch between the two inverters by applying NBTI to one inverter. In Fig. 5, the power-up data is data ‘1’, which is easy to be flipped. To increase the small mismatch, the power-up data needs to be flipped and NBTI stress is imposed to generate |V”tp1 | >> |Vtp2|. After this, the strength difference between two PMOS devices will be large enough to produce the power-up data of the SRAM cell dominantly ‘1’.
uniformity improvement technique with the proposed reliability improvement technique for SRAM-PUF. First, the proposed uniformity technique is employed to achieve the required uniformity. This is conducted by counting the number of data ‘1’s and that of ‘0’s. If the counting result shows that data ‘1’ and data ‘0’ are evenly distributed within the target uniformity range, the NBTI injection step is skipped. If not, we have to inject NBTI to the SRAM array until the required uniformity is obtained. Once the target uniformity is accomplished, the proposed reliability improvement technique starts by checking the variations in the uniformity using multiple power-ups. If the variation is larger than the target, the mismatch in SRAM cells needs to be enhanced. This is executed by flipping the data in the SRAM array and injecting NBTI. After the NBTI injection, if the mismatches between two inverters in SRAM cells are large enough to repeat the power-up pattern within the allowable variations, we can stop the reliability improvement process. Finally, the power-up pattern of the SRAM-PUF array is not affected by environmental fluctuations. Fig. 6 summarizes the flow explained above. Fig. 7 depicts the effect of the proposed methodology on
C. SRAM-PUF with Improved Uniformity and Reliability In this section, we explain how to merge the proposed
Fig. 7. Uniformity and Reliability improvement methodology on SRAM-PUF
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power-up data ‘1’ also increases. When the mismatch is relatively small, the probability shows a higher sensitivity to the aging. Note that it slows down when the difference between the probabilities of data ‘1’ and data ‘0’ is large. IV. Conclusion For a truly random SRAM-PUF, high degrees of uniformity and reliability are required. SRAM-PUF power-up patterns are expected to be random and uniform between SRAM-PUF ICs and consistent in a specific SRAM-PUF at every power-up so as to remove any variations in the security key. In this work, we proposed a post-fabrication methodology for improving the uniformity and the reliability of SRAM-PUFs. Device aging is utilized to reduce or increase the mismatch of SRAM-PUF cells. The proposed methodology improves the uniformity by applying NBTI stress to an SRAM-PUF array until the desired uniformity is obtained. This is followed by the reliability improvement sequence where aging is applied to the SRAMPUF array after data flipping to increase the mismatch. The proposed will be more useful in advanced CMOS technology where aging effects are more prominent.
Fig. 8. Uniformity improvement due to NBTI.
REFERENCES [1]
Fig. 9. Reliability improvement due to NBTI.
an SRAM-PUF array. The initial power-up data pattern shown in Fig. 7(i) has much more data ‘1’s (dark color) than data ‘0’s (light color). The updated data pattern after injecting aging is shown in Fig. 7(ii). Note that the number of data ‘1’s is still larger than that of data ‘0’s. Additional aging forms the data pattern in Fig.7(iii) where the number of ‘1’s is similar to that of ‘0’s. After achieving uniformity in the SRAM-PUF array, we enhance the mismatch for reliability improvement, which is described by the augmented contrast in Fig.7(iv). III.
SIMULATION RESULTS
Fig. 8 shows the effect of NBTI aging on the power-up pattern of an SRAM-PUF array. Monte-Carlo simulation with 10k points was conducted for checking power-up patterns. A skewed SRAM-PUF array was assumed to validate the proposed methodology. Note that NBTI aging improves the uniformity. After iterative aging injection, the number of ‘1’s and that of ‘0’s become almost equal. The amount of aging should be controlled until the difference between the number of ‘1’s and that of ‘0’s lies within the acceptable range. Fig. 9 shows the effect of the proposed reliability enhancement technique on the power-up data of an SRAM cell. A small mismatch in the SRAM cell was assumed to generate a cell with weak data ‘1’. When the mismatch between two crosscoupled PMOS devices is small (i.e. ΔVTH = a), the probability of power-up data ‘1’ is 0.538. As the mismatch increases with cell aging after flipping, the probability of
J. Guajardo et al. "Brand and IP protection with physical unclonable functions." IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008. [2] P. Schaumont et al. "Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits." IEEE International Symposium on Circuits and Systems (ISCAS), 2008. [3] D. Lim, J. W. Lee, B. Gassend, G. E. Suh, M. Van Dijk, and S. Devadas, "Extracting secret keys from integrated circuits," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 13, pp. 12001205, 2005. [4] S. Devadas and B. Gassend. "Integrated circuit that uses a dynamic characteristic of the circuit." U.S. Patent No. 7,757,083. 13 Jul. 2010. [5] R. S. Pappu, "Physical one-way functions," Ph.D. thesis, Massachusetts Institute of Technology, 2001. [6] R. Maes, P. Tuyls, and I. Verbauwhede, "A soft decision helper data algorithm for SRAM PUFs," in IEEE International Symposium on Information Theory, 2009. ISIT 2009., 2009, pp. 2101-2105. [7] M. Hofer and C. Boehm, "An alternative to error correction for sramlike pufs," in Cryptographic Hardware and Embedded Systems, CHES 2010, ed: Springer, 2010, pp. 335-350. [8] G. Selimis et al. "Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes." IEEE International Symposium on Circuits and Systems (ISCAS), 2011. [9] D. E. Holcomb, W. P. Burleson, and K. Fu. "Power-up SRAM state as an identifying fingerprint and source of true random numbers." IEEE Transactions on Computers, 58.9 (2009): 1198-1210. [10] L. Wang, Q. Ye, R. Wong, and M. Liehr, "Product Burn-in Stress Impacts on SRAM Array Performance," 45th annual. ieee international Reliability physics symposium, 2007. proceedings. , vol., no., pp.666,667, 15-19 April 2007. [11] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "An Analytical Model for Negative Bias Temperature Instability,". ICCAD '06. IEEE/ACM International Conference on Computer-Aided Design, 2006 , vol., no., pp.493,496, 5-9 Nov. 2006
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I. INTRODUCTION In recent years, digital systems are becoming part of everyday life - ranging from mobile phones, appliances & security systems. These devices store personalized data which should be protected from external attack. In addition, short product-cycle time forces semiconductor vendors to outsource IPs to other SoC vendors where design theft might result in tremendous loss of revenue to IP owners [1]. Therefore, digital electronics and IPs need robust security mechanisms without significant overheads in power and silicon area. Conventional security systems (e.g. RFID tags, smart cards) use non-volatile memory (NVM) based security mechanisms in which binary encrypted keys are stored and authenticated to access stored secret information [2]. However, with the development of new (invasive & non-invasive) tampering methods such as micro-probing, laser cutting, glitch attacks and power analysis, it is possible for attackers to steal the binary keys for authentication. To prevent such physical attacks, researchers have developed various tamper-sensing methods where meshed sensors are used to detect any tampering on the ICs. The limitation of the sensor-mesh is that it cannot detect intrusion when the circuit power is off and the hardwired information can be easily stolen [3]. To address the above issue, hardware-intrinsic-security (HIS) has been investigated by researchers for improving hardware security [4], [5]. Gassend et al. introduced Physical Unclonable Functions (PUFs) based on the concept of random functions in silicon [4]. To be brief, PUF is a method of producing fingerprints of physical objects based on their random variations during manufacturing. The amount of random variations increases with semiconductor technology scaling. Fig. 1 illustrates a sample security system where PUF is
978-1-4799-3432-4/14/$31.00 ©2014 IEEE
Fig. 1. Activation code and key generation using PUF.
employed for activation code generation and key generation. PUF is involved in both activation code generation and key generation. Since the outputs of the PUF are complex and untraceable, activation codes and keys cannot be traced either.
Various types of PUFs such as optical PUF, delaybased PUF, butterfly PUF and SRAM-PUF have been developed. Literature reveals that SRAM-PUF has many advantages over other PUF types in point of stability and reliability [6],[7],[8]. In addition, temperature variations in SRAM PUF have a common-mode effect, thus the impact of temperature variations on the output is insignificant [9]. Structurally, two cross-coupled inverters are symmetrical in an SRAM bit-cell and ideally the SRAM cell should be in the meta-stable state during a start-up phase. However, the devices in the cross-coupled inverters have mismatches due to the manufacturing variations. The small mismatches in the cross-coupled inverters will be amplified by the positive feedback of the cross-coupled inverters and will eventually generate either logic ‘1’ or logic ‘0’. Assuming random device variations, SRAM cells will also generate logic ‘1’ and logic ‘0’ randomly with the probability of 0.5. This make a binary output string read from an SRAM array unique, random and non-traceable. However, under large systematic process variations, the number of logic ‘1’ in an SRAM array can be much greater than that of logic ‘0’ or vice versa after power-up. In this case, the randomness in of an output string from an SRAM array is degraded. In addition, if device mismatches are insignificant, an output string can vary considerably between power-up phases. This degrades the reliability of the SRAM-PUF. In this work, we propose a methodology utilizing aging injection for addressing the above issues in the SRAM-PUF. To simulate the effect of NBTI injection on SRAM-PUF, we modified the transistor parameters considering the effects of NBTI on MOSFET from standard literature [10],[11].
1941
II. PROPOSED METHODOLOGY This work proposes an aging-injection-based methodology to address the uniformity and the reliability issues of SRAMPUF. The proposed methodology utilizes an aging mechanism called negative-bias-temperature-instability (NBTI) to adjust SRAM-PUF more uniform and reliable. NBTI has been considered as a primary aging mechanism degrading device and circuit performance in advanced CMOS technology. As the name suggests NBTI occurs when a PMOS device is subjected to negative bias (i.e. Vgs = -Vdd) on gate under high operating temperatures. The main impact of NBTI is the increase in the device threshold voltage. In high-k/metal-gate process technology, positive-bias-temperature-instability (PBTI) in NMOS devices also becomes prominent. However, only NBTI will be considered in this work for simplicity. The details of the proposed methodology are explained in the following sections.
Fig. 2. Cell Flip in power-up due to aging (NBTI) injection. |Vtp1| and |Vtp2 | represents the threshold voltage of P1 and P2 respectively before ageing. Also, |V'tp1| and |V'tp2 | represents threshold voltage of P1 and P2 after ageing.
A. Uniformity Improvement The uniformity of SRAM-PUF is defined as the distribution of data 1's and 0's in an SRAM array after powerup. Even distribution of data 1's and 0’s ensures a strong security key which is difficult to be replicated. Fig. 2 shows a typical SRAM cell with two cross coupled inverters connected back to back. The initial power-up value of the SRAM cell depends on the device mismatches in the cross-coupled inverters (P1 and P2, N1 and N2). In general, we expect the SRAM cells are initialized with data ‘1’ and ‘0’ evenly. However, under systematic process variations, the SRAM cells can have much more data ‘1’ than data ‘0’ or vice versa, which deteriorates the robustness of the SRAM-PUF. To address this, we propose an uniformity improvement technique utilizing aging (i.e. NBTI in this work) injection. The polarity and the amount of aging change the mismatches in the cross-coupled inverters and accordingly redistribute the number of data ‘1’s and ‘0’s. Fig. 3 shows the effect of aging injection on the power-up output of an SRAM cell. If we assume P1 is weaker than P2 (i.e. |Vtp1| > |Vtp2|), OUT will be data ‘0’ after power-up without considering other nonidealities as shown in Fig. 4(a). If the same cell is subjected to NBTI stress (high voltage and high temperature), P2 (Vgs = Vdd) will experience NBTI stress resulting in the increase in |Vtp2|. In subsequent power-up sequences after the aging, P2 will become weaker than P1 and hence the cell will power up with data ‘1’ as depicted in Fig. 4(b). This indicates that we can control the power-up output of an SRAM cell through the effect of ageing (NBTI). The above result can be applied to an SRAM array to improve the uniformity. Assume that a non-uniform SRAM-
Fig. 2. SRAM cell for SRAM-PUF implementation.
(a)
(b)
Fig. 3. (a) Initial power-up behavior of SRAM cell (b) flipped cell after aging injection.
PUF array is fabricated where the number of data ‘1’s is unacceptably different from that of data ‘0’s. For example, 70% of the total cells in an SRAM array are initialized with data ‘1’ while 30% of the cells have data ‘0’ after the initial power-up. Such an output distribution is vulnerable to attack and needs to be improved. In this case, we can apply aging injection to the SRAM array, leading to data flipping in some SRAM cells after power-up. This will reduce the difference between the number of ‘1’s and that of ‘0’s. The above aging injection can be repeated until the power-up data pattern is within the desired range. B. Reliability Improvement Another critical parameter to be considered in robust SRAM_PUS is reliability. In SRAM-PUF, reliability is defined as the capability of an SRAM array for repeating same power-up patterns between repeated power-up sequences. For ideal reliability, the SRAM cells should generate same values whenever SRAM-PUF is powered up. As explained, a powerup value of an SRAM cell is decided by the mismatches between corresponding cross-coupled inverters. If the mismatch between the two inverters is minimal, the start-up value of the cell can be random. Even though minimizing the mismatch in SRAM cells is highly desired in the conventional SRAM design, it is not so critical in achieving higher SRAMPUF reliability. Therefore, the mismatch has to be revisited in the design of SRAM-PUF.
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Fig. 5. Reliability enhancement using aging injection after data flipping.
Fig. 6. Proposed methodology for robust SRAM-PUF implementation.
In this work, we propose a methodology for improving SRAM-PUF reliability by injecting additional aging after achieving target uniformity. The proposed reliability improvement methodology aims to increase the threshold mismatch by applying NBTI aging to one inverter in each SRAM cell. Fig. 5 illustrates the effect of the proposed method on SRAM-PUF reliability. Since |Vtp1| is equal or slightly larger than |Vtp2|, the power-up data will be almost random. Although SRAM-PUF requires randomness in the power-up pattern of an SRAM array, it doesn’t require randomness in the powerup data of each SRAM cell. In this case, we can enhance the mismatch between the two inverters by applying NBTI to one inverter. In Fig. 5, the power-up data is data ‘1’, which is easy to be flipped. To increase the small mismatch, the power-up data needs to be flipped and NBTI stress is imposed to generate |V”tp1 | >> |Vtp2|. After this, the strength difference between two PMOS devices will be large enough to produce the power-up data of the SRAM cell dominantly ‘1’.
uniformity improvement technique with the proposed reliability improvement technique for SRAM-PUF. First, the proposed uniformity technique is employed to achieve the required uniformity. This is conducted by counting the number of data ‘1’s and that of ‘0’s. If the counting result shows that data ‘1’ and data ‘0’ are evenly distributed within the target uniformity range, the NBTI injection step is skipped. If not, we have to inject NBTI to the SRAM array until the required uniformity is obtained. Once the target uniformity is accomplished, the proposed reliability improvement technique starts by checking the variations in the uniformity using multiple power-ups. If the variation is larger than the target, the mismatch in SRAM cells needs to be enhanced. This is executed by flipping the data in the SRAM array and injecting NBTI. After the NBTI injection, if the mismatches between two inverters in SRAM cells are large enough to repeat the power-up pattern within the allowable variations, we can stop the reliability improvement process. Finally, the power-up pattern of the SRAM-PUF array is not affected by environmental fluctuations. Fig. 6 summarizes the flow explained above. Fig. 7 depicts the effect of the proposed methodology on
C. SRAM-PUF with Improved Uniformity and Reliability In this section, we explain how to merge the proposed
Fig. 7. Uniformity and Reliability improvement methodology on SRAM-PUF
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power-up data ‘1’ also increases. When the mismatch is relatively small, the probability shows a higher sensitivity to the aging. Note that it slows down when the difference between the probabilities of data ‘1’ and data ‘0’ is large. IV. Conclusion For a truly random SRAM-PUF, high degrees of uniformity and reliability are required. SRAM-PUF power-up patterns are expected to be random and uniform between SRAM-PUF ICs and consistent in a specific SRAM-PUF at every power-up so as to remove any variations in the security key. In this work, we proposed a post-fabrication methodology for improving the uniformity and the reliability of SRAM-PUFs. Device aging is utilized to reduce or increase the mismatch of SRAM-PUF cells. The proposed methodology improves the uniformity by applying NBTI stress to an SRAM-PUF array until the desired uniformity is obtained. This is followed by the reliability improvement sequence where aging is applied to the SRAMPUF array after data flipping to increase the mismatch. The proposed will be more useful in advanced CMOS technology where aging effects are more prominent.
Fig. 8. Uniformity improvement due to NBTI.
REFERENCES [1]
Fig. 9. Reliability improvement due to NBTI.
an SRAM-PUF array. The initial power-up data pattern shown in Fig. 7(i) has much more data ‘1’s (dark color) than data ‘0’s (light color). The updated data pattern after injecting aging is shown in Fig. 7(ii). Note that the number of data ‘1’s is still larger than that of data ‘0’s. Additional aging forms the data pattern in Fig.7(iii) where the number of ‘1’s is similar to that of ‘0’s. After achieving uniformity in the SRAM-PUF array, we enhance the mismatch for reliability improvement, which is described by the augmented contrast in Fig.7(iv). III.
SIMULATION RESULTS
Fig. 8 shows the effect of NBTI aging on the power-up pattern of an SRAM-PUF array. Monte-Carlo simulation with 10k points was conducted for checking power-up patterns. A skewed SRAM-PUF array was assumed to validate the proposed methodology. Note that NBTI aging improves the uniformity. After iterative aging injection, the number of ‘1’s and that of ‘0’s become almost equal. The amount of aging should be controlled until the difference between the number of ‘1’s and that of ‘0’s lies within the acceptable range. Fig. 9 shows the effect of the proposed reliability enhancement technique on the power-up data of an SRAM cell. A small mismatch in the SRAM cell was assumed to generate a cell with weak data ‘1’. When the mismatch between two crosscoupled PMOS devices is small (i.e. ΔVTH = a), the probability of power-up data ‘1’ is 0.538. As the mismatch increases with cell aging after flipping, the probability of
J. Guajardo et al. "Brand and IP protection with physical unclonable functions." IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008. [2] P. Schaumont et al. "Turning liabilities into assets: Exploiting deep submicron CMOS technology to design secure embedded circuits." IEEE International Symposium on Circuits and Systems (ISCAS), 2008. [3] D. Lim, J. W. Lee, B. Gassend, G. E. Suh, M. Van Dijk, and S. Devadas, "Extracting secret keys from integrated circuits," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 13, pp. 12001205, 2005. [4] S. Devadas and B. Gassend. "Integrated circuit that uses a dynamic characteristic of the circuit." U.S. Patent No. 7,757,083. 13 Jul. 2010. [5] R. S. Pappu, "Physical one-way functions," Ph.D. thesis, Massachusetts Institute of Technology, 2001. [6] R. Maes, P. Tuyls, and I. Verbauwhede, "A soft decision helper data algorithm for SRAM PUFs," in IEEE International Symposium on Information Theory, 2009. ISIT 2009., 2009, pp. 2101-2105. [7] M. Hofer and C. Boehm, "An alternative to error correction for sramlike pufs," in Cryptographic Hardware and Embedded Systems, CHES 2010, ed: Springer, 2010, pp. 335-350. [8] G. Selimis et al. "Evaluation of 90nm 6T-SRAM as Physical Unclonable Function for secure key generation in wireless sensor nodes." IEEE International Symposium on Circuits and Systems (ISCAS), 2011. [9] D. E. Holcomb, W. P. Burleson, and K. Fu. "Power-up SRAM state as an identifying fingerprint and source of true random numbers." IEEE Transactions on Computers, 58.9 (2009): 1198-1210. [10] L. Wang, Q. Ye, R. Wong, and M. Liehr, "Product Burn-in Stress Impacts on SRAM Array Performance," 45th annual. ieee international Reliability physics symposium, 2007. proceedings. , vol., no., pp.666,667, 15-19 April 2007. [11] S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "An Analytical Model for Negative Bias Temperature Instability,". ICCAD '06. IEEE/ACM International Conference on Computer-Aided Design, 2006 , vol., no., pp.493,496, 5-9 Nov. 2006
1944
