Detectable Perturbations: A Paradigm for ... - Semantic Scholar
c IEEE
-- Reprint from 13th IEEE VLSI Test Symposium, Princeton, N.J., April 30 - May 3, 1995
Detectable Perturbations: A Paradigm for Technology-Speci c Multi-Fault Test Generation Andrej Z emva1
Franc Brglez2
1 Electrical & Computer Engineering, University of Ljubljana, Ljubljana, Slovenia 2 CBL (CAD Benchmarking Laboratory), North Carolina State University, Raleigh, N.C. 27695, U.S.A.
(WWW: http://www.cbl.ncsu.edu/www/)
Abstract { This paper introduces the concept of detectable of wires. Just for a pair wires, we can consider 255 cases perturbations as a method to generate tests that can then cover any technology-speci c faults such as multiple bridging, open and stuck-at faults. Rather than devising a customized test pattern generation system for each class of technology-speci c faults, we implemented a generic system to generate tests for single and multiple perturbations. We demonstrate the versatility of this approach by generating tests for a set of large benchmark circuits that have been mapped into single- and multi-output modules. These tests cover single stuck-at, multi-output bridging, stuckat, as well as any mutation faults in the functionality of the technology-mapped cells. Experimental results provide useful insights about the quality of single stuck-at test patterns versus coverages for the additional classes of faults. I. INTRODUCTION Increasing number of technology mappers can now make use of FPGA or standard cell libraries where combinational cells have more than one output. Combining functionality of several single-output modules into a single cell typically reduces both the area occupied by active devices as well as the area taken by the interconnect between the cells. The presence of multi-output cells raises new questions about fault modeling and testing: how e ective is the traditional single stuck-at fault test when considering that module outputs may be pairwise bridging, stuck-at some constant values, may be interchanged, or are simply performing some other function not originally intended. Familiar examples of functional mutations on wires are related to manufacturing defects such as AND/OR bridging faults or pairwise stuck-at faults. Manufacturing defects may subtly change behavior of complex logical nodes in ways not detectable by single stuck-at fault tests. Alternatively, such nodes can also be incorrectly assigned functions during the speci cation phase { for example instead of OR one may well specify XOR and escape detection. In this paper, we address the problem of testing for multi-faults by considering the problem of detecting functional mutations on wires as well as on logic nodes. The space of mutation faults, even without considering mutations of logic nodes, grows exponentially with the number
Andrej Z emva was supported in part by Slovenian Ministry of Research and Technology under grant J2-6188-0781-94FER. Franc Brglez was supported by contracts from the Semiconductor Research Corporation (94-DJ-553), SEMATECH (94-DJ-800), and ARPA/ARO (P-33616-EL/DAAH04-94-G-2080). Xilinx Inc. provided the XACT toolset to generate new technology-mapped benchmark netlists.
of distinct 2-input 2-output functional mutations. Single, pairwise stuck-at and bridging faults are only special cases of such mutations. Rather than devising specialized algorithms to detect each speci c mutation of interest, we introduce a generic concept of detectable perturbations. By detecting a relatively small set of such perturbations, we will have covered completely a much larger set of all possible functional mutations. We demonstrate that detection of such perturbations is closely related to detection of a sequence of independent perturbations from a single source, and can thus use state-of-the-art single stuck-at test generation techniques to generate complete perturbation tests for a set of large benchmark circuits. We motivate the proposed approach in Section 2, then formalize the notion of detectable perturbations in Section 3. In Section 4, we introduce the covering of any mutation fault in terms of detectable perturbations and set up the benchmarking experiment. In Section 5, we report on the experimental results. A more detailed report on this research is available in [1]. II. MOTIVATION Consider a black box with k input pins from the set X and p output pins from the set Z . Nominally, this box realizes a function Z(X ): B k ! B p , representing the behavior of either a hardware module or a software module. Upon embedding into a larger hardware system or a software program, its I/O may no longer be directly accessible to control and to observe. The problem of testing is the same whether the black box contained in the larger system is faulty due to a manufacturing defect, whether its speci cation has been entered incorrectly, or whether an entirely wrong box has been embedded by mistake. The community concerned with testing hardware failures relies to a large extent on single stuck-at (0/1) fault models on the boundary of the box. The community concerned with testing computer programs and speci cations considers the single stuck-at fault models inadequate and attempts to derive alternative strategies [2]. Some of such strategies also consider notions of mutation faults. In the context of the black box with k input pins and p output pins, one may thus consider two extremes: between 2(k + p) single stuck-at faults and 2(p2 ) ? 1 mutation faults. Consider an example with k = 4; p = 2 and two expressions. For purpose of illustration, we share no logic: Z1 = (x1 OR x2 ) OR (x3 OR x4 ); Z2 = (x1 OR x2 ) NOR (x3 OR x4 ):
350
k
A test set f0000; 1000; 0100; 0010; 0001g covers all single stuck-at faults. However, the same test set also covers all single stuck-at faults in these expressions: Z1 = (x1 XOR x2 ) XOR (x3 XOR x4 ); Z2 = (x1 XOR x2 ) NOR (x3 XOR x4 ): In this example, the size of a single stuck-at fault4 set at the pins is simply 2 6 = 12 while there are 2(22 ) ? 1 = 4; 294; 967; 295 mutations that may be considered in the extreme case. Clearly, the choice for a best subset of mutations to generate a 'good test' for most 'typical mutations', given the initial black box speci cation, will continue to be subject of conjectures. What may be a reasoned conjecture for a hardware test, supported by reports of failures during device testing and returns from the eld, may not lead to a good fault model for testing the hardware speci cation in software, and vice versa. The concept of detectable perturbations as introduced in this paper induces tests that will implicitly cover the set of all 2(p2 ) ? 1 mutation faults. Given ka black box with k input and p output pins, we consider 2 minterms, inducing a k-in-p perturbation in up to (2p ? 1) ways onto the p output pins. The upper bound on the set of all perturbations that we will consider is thus 2k (2p ? 1) { a bound much lower than the size of the set of all possible mutations. For the example above, the 4; 294; 967; 295 mutations 4of a2 single module can all be covered by tests for up to 2 (2 ? 1) = 48 perturbations! A directed hypergraph in Figure 1 illustrates the approach to introducing perturbations. Several circuit representations, including one of a multi-output mapped circuit, are shown in Figure 4. Figure 5 focuses on experimental conclusions of this work: the total number of perturbations we need to consider for a set of large benchmark circuit is only 2.36-times the number of single stuckat faults in the equivalent logic representation. However, test patterns based on single stuck-at fault model clearly do not cover a large fraction of detectable perturbations. III. DETECTABLE PERTURBATIONS Traditional single and multiple stuck-at and bridging faults are special cases from the set of mutation faults. We consider a combinational or a sequential synchronous multiple-level Boolean network modeled as a directed hypergraph. In Figure 1 we show an example, including a 4-in-3 perturbation. More speci c illustrations are introduced in Figures 2 and 3. Several representations of the same example are shown in Figure 4a-c. Figure 4a is the initial circuit speci cation graph, Figure 4b is the optimized granular representation of the same circuit, and Figure 4c is the hypergraph created after the technology mapping into a speci c library set. Note that while circuits in Figures 4a-b are DAGs, the hypergraph in Figure 4c has a pseudo-cycle. Mutation faults can be associated with wires as well as logic nodes. Boolean network. We model this network as a directed hypergraph G = (V ; E ). Since we will relate nodes and wires in this graph to fault sets later on, we will refer to edges in this graph as wires and elements of the vertex set as nodes. All nodes are considered to be of one of the following types: primary and pseudo-primary inputs (PIs, PPIs), primary and pseudo-primary outputs (POs, k
PPOs), register nodes, cluster nodes, and fanout nodes. By de nition, all register nodes are implicitly synchronized with a single clock, have a single data input driven by a pseudo-primary output node and a single data output sourced by a pseudo-primary input node. A cluster node can have any number of inputs and any number of outputs, each output can describe a logic function of arbitrary complexity. Each cluster node is a DAG where, by de nition, all logic nodes have single outputs only. By replacing all cluster nodes in the hypergraph with their respective graph representation, we have a DAG between (PIs, PPIs) and (POs, PPOs). Note however, that the hypergraph itself may have pseudo-cycles when viewed in terms of cluster nodes. This is illustrated in Figure 4a-c. A fanout node in a hypergraph or a graph has a single input and any number of outputs. A fanout node may or may not drive another fanout node. In case where fanout node does not drive another fanout node, we say that the interconnect is simple, otherwise, the interconnect is non-simple. Note that when considering a technologymapped representation or any layout-speci c implementation fanout nodes are partitioned and connected with wires as illustrated in Figure 4c which shows a network mapped into a speci c technology. All wires have a unique label. For logic nodes we use the same label as for their outgoing edge. Similarly, we use the same label for a fanout node and its incoming edge. With each wire ei we associate a Boolean function fe . The complement of the function associated with wire ei is denoted as f e . We will refer to the logic node in this graph interchangeably also as a logic module, or a logic cell. For additional details on notation, see also [3, 4, 5, 6]. Detectable k-in-p perturbations. A k-in-p perturbation requires evaluation of a perturbation function of k decoding wires and injecting a perturbation signal onto a set of up to p perturbed wires. A perturbation is injected onto any of the perturbed wires if and only if the signal values on the decoding wires satisfy the on-set of the perturbation function . The example in Figure 1 illustrates the case where is represented by a single minterm or decoding gate m6 . Its output is 1 if and only if values on the decoding wires fx2 ; n2 ; n5 ; n4 g carry the signals f0110g. Each of the perturbed wires is an output of the XOR 'bridge gate' driven by the output from the perturbation function and the nominal wire. In the example shown, the nominal wires are fa; b; cg and the perturbed wires are fa; b ; c g. The perturbation as de ned here can introduce a cycle into the hypergraph and potentially cause asynchronous oscillations between each or some of the clock cycles. The key question that arises is whether such perturbations are detectable at any of the primary outputs in Z . Perturbations as de ned here generalize and unify the work in [3, 4, 5]. In this paper, we relate detectability of perturbations to detectability of bridging and multi-faults with a single test pattern rather than test pattern sequences. Hence, all subsequent formulations assume detectability of each perturbation in a single time frame. All PPIs and PPOs are thus assumed scannable. We denote all PIs and PPIs as x = (x0 ; x1 :::), and all POs and PPOs as Z = (Z0 ; Z1:::). The detectability function of any perturbation on the perturbed wires a ; b ; c ; ::: is thus de ned as a Boolean
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i
i
AA AA
Alternative Formulations. While complex, the notation presented here is designed to relate closely to the generic perturbation model as illustrated in Figure 1. Detectability of perturbations on wires a ; b ; c is subject to the signal value on the decoding gate and the propagation status of each of the induced perturbations. The de nitions of perturbation in [6, 7] di er from the ones introduced here. As illustrated for the simple circuit in Figure 2, used originally in [6, 7], each perturbation introduces an extra input with a constant signal of '1'. As a result, it computes the observability function of the perturbed wire without regard to any speci c assignment to this wire. In contrast, the 1-to-1 perturbation as de ned in (1), introduces no extra input to the perturbed circuit and computes the detectability function as expressed in (1) which directly relates to the single stuck-at fault detectability. According to the familiar de nitions, including ones in [6, 7], the perturbation in the circuit example in Figure 2 is both controllable and observable, and yet, this perturbation is not detectable! By inspection, we also nd that the single stuck-at 1 fault on the wire with perturbation is not detectable.
m6
x0 x1 x2 x3
n4
b*
n1
n7
b a*
a
n2
Z0
n8
c* c
x4
Y1
n5
y2
AA AA
Y0
n6
y1 y0
n3
Y2
= 0 1 n2 = 3 + 4 n3 = 1 0 a = 2 n2 n4 = n1 + a n5 = a n3 n1
x :x
f
f
x
f
y :y
x
f
x :f
f
f
f
= a+ 2 b = n4 + n5 c = n4 n5 n7 = b 2 n8 = c n6
f
f f
f
f
f
y
f
:f
f
f :y
f
f
f :f
f
b
Figure 1: A Boolean network with a 4-in-3 perturbation.
P
X Z (x) Z (x)j r
r
r
where r designates OR-ing the respective functions for all outputs. Speci cally, for the example in Figure 1 where k = 4 and p = 3, and assuming that primary inputs are assigned such that when the decoding wires fx2 ; n2 ; n5 ; n4 g carry the signals f0110g, the perturbed wires a ; b ; c carry the signals f001g which are complements of the nominal signal values f110g. In our notation, we will denote the complementation of the signals on the perturbed wires as f1 1 0g. The detectability function for a 4-in-3 perturbation, expanding on (1), is thus
ma6=b1 c1 0 =
X Z (x; a = f ; b = f ; c = f ) r
r
a
b
c
b1*
a
a
b2 c (b) observable perturbation on b1*
signal observabilities on the inputs of XOR are identical to signal observabilities on the XOR output.
b*
b
a
a*
b
b*
(b) Cases of 2-in-2 perturbation a
m6
(3)
For simplicity of notation, we will from now on refer to
a*
a
a
a*
b
which evaluates to
rather than to ma6=b1 c1 0 . This is permissible since mabc 6 =1 1 0
z
b1* y
a*
a*
a
b
X
1
(a) Cases of 1-in-1 perturbation
(2)
where we de ne the perturbation observability O1abc1 0 as a b c = O1abc1 0 = Oabc Zr (x; a = fa; b = fb ; c = f c ) r Zr (x; a = f a ; b = f b ; c = fc ) (4)
b1
b
y
Zr (x; a = fa fm6 ; b = fb fm6 ; c = f c fm6 ) mabc = ma6 =b1 c1 0 = fm6 O1abc1 0 6 =1 1 0
x
a z
Figure 2: An undetectable but observable perturbation.
(1)
b1
b2 c (a) undetectable perturbation on b1*
di erence of the nominal and the perturbed network:
ab c ::: =
x
a
b
b*
m6
a
a*
b
b*
m6
(c) Cases of k-in-2 perturbation
Figure 3: Modeling of various k-in-p perturbations. Special Cases. The perturbations in Figure 3a-b illustrate special cases of p-in-p perturbations, for p = 1 and p = 2. Here, the decoding wires have 1-to-1 relationship to the perturbed wires and we simplify the notation for the corresponding detectability functions. For example, we de ne the detectability of a 2-in-2 perturbation of both wires that carry the signals f11g as
352
X Z (x; a = f ; b = f )
fa11bg =
r a b r Zr (x; a = fa fafb ; b = fb fa fb )
(5)
j
which evaluates to
X Z (x; a = f ; b = f ) r a b r Zr (x; a = f a ; b = f b )
(6) (7)
Similarly, we write for the detectability of a 2-in-2 perturbation that carries the signals f11g and where only the wire a is perturbed:
X Z (x; a = f ; b = f )
fa11bg =
r a b r Zr (x; a = fa fa fb ; b = fb )
(8)
which evaluates to
fab1 1g = fa fb O1ab1
and
O1ab1 =
i
i
fab1 1g = fa fb O1ab1
O1ab1 =
Perturbation Equivalence Classes. Both 2-in-2 and k-in-2 perturbations can be classi ed into 8 equivalence classes with important properties [1]. As a consequence, we would consider computing mab=00 if and only if fab 00g 6= 0. ab ab ab Similar corollaries hold for f01g , f10g , and f11g . Oscillating perturbations. When perturbations introduce a cycle, we can observe e ects similar to the feedback bridging faults reported in [8]. Oscillating perturbations as de ned here are analyzed in more detail in [1]. We refer to a k-in-p perturbation as a cyclic perturbation if there is at least one path between p and k wires. If there is no such path, the perturbation is denoted as an acyclic perturbation or simply a perturbation. The k-in-p cyclic perturbation causes the circuit to oscillate whenever the perturbed signal on any of the p perturbed wires propagates to any of k decoding wires. Such a perturbation is denoted as oscillating perturbation. A perturbation which does not induce oscillation is a stable perturbation. All acyclic perturbations are stable. We can analyze the e ects of perturbations using the familiar D calculus. In a sequential circuit, a perturbation may be stable in one time frame while it can oscillate in another time frame. Consider the perturbation (m13 =0 0 1) in Figure 1: the decoding wires are fx2 ; n2 ; n5 ; n4 g and the perturbed wires are fa ; b ; c g. Assume that all ip- ops are reset in time frame 0. Perturbation is stable and undetected during time frame 0, since the D signal at line a can propagate only through node n6 and ip- op Y0 in time frame 1. In time frame 1, D is propagated through node n5 and the injected perturbation oscillates. Assuming that the values on all combinational modules are stable after 1/2 the clock period, then the circuit, considering no change at the PIs, returns into its nominal state just before the next clock signal. In time frame 2, the condition for the perturbation is satis ed again and the perturbation is reinjected, appearing as a stable and undetectable. Since this perturbation oscillates during every odd time frame, its period is 2. For circuit in Figure 4c, we note the following. A 2-in-2 perturbation (c4 c16 =f0 0g) is a detectable stable perturbation, while the 4-in-2 perturbation (m4 =0 1), with decoding wires fx4 ; x1 ; x3 ; c9 g and perturbed wires fc11 ; c12 g, is stable but undetectable. The perturbation (m24 =0 1), with decoding wires fx6 ; x7 ; x3 ; x8 ; c9 g and perturbed wires fc4 ; c16 g, induces an oscillation. While propagating the perturbation signal D to PO z4 , D is also propagated through node c6 onto the decoding wire c9 , canceling the perturbation. In this work we report all oscillating perturbations propagating to POs as detectable. Undetectable oscillating perturbations are shown in [1]. IV. DETECTABILITY OF MUTATION FAULTS We prepared three logically equivalent sets of large benchmark netlists on which we performed experiments reported in the last section of this paper. In this section we analyze their characteristics as they relate to mutation faults and perturbations. All benchmarks are derivatives of the ISCAS85 set [9] as follows. Set A: 100% testable netlist in [9]. Set B: an optimized representation of netlists from the Set A. We used SIS [10] with option map -m 0. In addition to the inverter, there are four types of 2-input logic gates in
X Z (x; a = f ; b = f ) r a b r Zr (x; a = f a ; b = fb )
(9) (10)
All cases of detectability functions related to the illustrations in Figure 3 thus summarize as follows: For any 1-in-1 perturbation we consider 2 (2 ? 1) = 2 detectability functions:
fa1g = fa O1a
fa0g = fa O0a ;
(11)
For any 2-in-2 perturbation we consider up to 22 (22 ? 1) = 12 detectability functions: (12) = f a f b O0ab0 ab = f a f b O0 0 (13) = f a f b O0ab0 (14) = ::: For any k-in-2 perturbation, where I00 ; I01 ; I10 ; I11 denote the sets of all indices of the minterms that decode the output to f00; 01; 10; 11g respectively, we consider up to 2k (22 ? 1) = 3 2k detectability functions:
fab0 0g fab0 0g fab0 0g :::
mab=0 0 = fm O0ab0 ; 8j 2 I00 (15) (16) mab=0 0 = fm O0ab0 ; 8j 2 I00 ab ab m =0 0 = fm O0 0 ; 8j 2 I00 (17) ::: = ::: We can show that O1a = O0a , O1ab1 = O0ab0 and O0ab1 = O1ab0 . j
j
j
j
j
j
353
i
i
this netlist representation, performing following functions on inputs a; b: ab, ab, a + b, a + b. This choice of logic primitives results in few if any inverters.
a1
x1 x2
Set C: a technology-mapped representation of the netlists from the Set B, using SIS technology mapper for benchmarks c499, c1355, c6288 and XACT technology mapper [11] for the remaining 7 benchmarks. For purposes of this experiment, we chose the mapped netlist from the mapper that generated the largest number of 2-output modules and reported lower fanout at module-level. This is now a hierarchical netlist based on large single and twooutput modules, with each module represented by a gatelevel logic primitive type described in Set B. Our choice of technology mapper such as XACT provided a large variety of cell functions with logic overlap that we wanted to consider in this study.
The representations of a simple circuit c44 in Figure 4 have all the attributes described. The node and the wiring characteristics of these three representations are summarized in Table 1. For example, jLa j, jQa j denote theanumber of logic and fanout nodes in circuits, and jW j denotes the number of 2-point wire connections in any of the netlist from the Set A. In case that the logic node drives a primary output only, we remove any output bu ers on this line. For netlists in the Set C, we report two representations: module level in terms of 1-output and 2-output modules jLc1 j, jLc2 j respectively,c and gate level in terms of single output logic gates jLe j that represent the total number of logic nodes in the interior to each module. Notably, while the interconnect at module level is simple, this is no longer the case when we expand each module to logic level. As illustrated in the example in Figure 4, fanout nodes may drive other fanout nodes. For purpose of test generation and more accurate modeling of layoutspeci c fault dependencies, such a model can be useful. Thec numbercof fanout nodes and wires, as expressed by jQe j and jWe j, fully accounts for this approach. This in uences the resulting test generation and fault coverage we report in our experiments. Our test generator extends the concepts introduced in [4] and targets k-in-p perturbations. Given the circuit parameter sizes in Table 1 and formulas introduced earlier, we report the sizes of perturbation and faults in Table 1. For example, jF a j, jF b j, jFec j are sizes of single stuck-at fault sets to be covered by tests for 1-in-1 perturbations. c j is the number of pairwise faults to be covered by jFpw c as speci ed tests for 2-in-2 perturbations in the set Ppw in Table 2. jP2b j denotes the size of perturbations for 2in-1 perturbations in netlists from the Set B; jPkcj denotes the size of perturbations associated with k-in-2 perturbations for netlists from the Set C. For netlists in cset C cwe are also reporting lower and upper bounds (jFlb j, jFub j) for pairwise bridging faults. We developed a set of simple formulas that relate to sizes of all parameters listed in Table 1. Let L1 , L2 Q, Z denote the sets of 1-output, 2-output logic nodes, fanout nodes, and PO nodes respectively, and let ki1 and ki2 be the number of inputs incident at 1-output and 2-output logic nodes. Then, for any circuit, such as shown in Figure
a5
z1
a9
a6
a10
z2
a11
z3
a2
x3 x4 x5
initial netlist representation
a7
a3 x6
a4
x7
(a)
(specification)
z4
a12 a8 a13
z5
x8
x1 x2
z1
b10
b1
b8
b5
z2
b11
(b)
b2
x3 x4 x5
z3
b12
b6 b9
granular netlist representation
b3 x6
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x7
intermediate
z4
b13 b7 b14 b16
b15
x8
(may be optimized)
z5
c10 c1
c5
z1
c8
x1
AAAA AAAA AAAA AAAA x2
x3 x4
(c)
z2
c12
z3
x5
final
technologymapped netlist
c11 c2
x6
c3
c9 c6
c4
c7
x7
c13
z4
c14
representation
c16
z5
x8
c15
Figure 4: Equivalent Boolean network representations. 4a-c, the number of wires (or edges) is simply
jWj =
jL j jL j X X k + k 2
1
i1 =1
i1
i2 =1
i2 + jQj + jZj
(18)
Consider netlists of simple gate primitives such as shown in Figure 4a-c. Let jL1 j be the number of such gates, excluding inverters and bu ers. Then, the size of the set of equivalence-collapsed set of faults is simply
jFj =
Xk jL1 j
i1 =1
i1 + 2(jQj + jZj)
(19)
Traditionally, following 6 mutation faults are considered: (a::b) AND-bridging faults on wires a; b OR-bridging faults on wires a; b (ajjb) (ab=00) stuck-at/00 fault pair on wires a; b (ab=01) stuck-at/01 fault pair on wires a; b (ab=10) stuck-at/10 fault pair on wires a; b (ab=11) stuck-at/11 fault pair on wires a; b To illustrate the generality of our approach, we postulate and report in this paper on 41 additional mutation faults.
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Table 1: Sizes of node, wire, and fault sets for the circuit representations a, b, c such as shown in Figure 4.
c44 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552
jXj jZj jLa j jQa j jW a j
8 36 41 60 41 33 233 50 178 32 207
5 7 32 26 32 25 139 22 123 32 108
jLb j jQb j jW b j jLc1 j jLc2 j jQc j jW c j jLce j jQce j jWec j
13 10 44 16 10 47 1 3 6 29 16 11 48 157 86 419 169 72 414 21 26 61 269 169 98 440 202 59 491 406 155 999 28 20 61 317 412 311 1161 357 125 854 347 115 834 40 43 82 441 340 196 888 514 259 1315 510 259 1311 24 24 55 321 448 335 1257 878 383 1896 610 187 1432 70 42 92 565 560 318 1433 1014 327 2147 797 173 1779 92 35 69 676 609 297 1606 1610 511 3309 1168 293 2643 117 140 164 1224 1150 537 2783 2288 792 5210 2059 437 4625 275 89 259 1797 1733 884 4385 2399 1438 6218 2349 1422 6151 628 165 728 4464 3760 1642 9144 3395 1197 7173 2524 678 5776 279 202 367 2236 2190 1227 5611 (a) Number of nodes and wires in equivalent circuit representations a, b, c.
jF a j jF b j
c j jFec j jFpw
jFlbc j
jFubc j
c j jP2b j jPpw
jPkc j
c44 57 62 68 141 132 464 64 36 224 c432 471 490 542 1222 1402 4104 676 312 2312 c499 542 1186 1498 940 1520 26668 1624 240 2560 c880 942 974 1096 2021 2178 10958 1386 516 3140 c1355 1566 1602 1618 1128 1664 32072 2040 288 2912 c1908 1862 1644 1746 1947 2734 22330 2440 504 3400 c2670 2086 1964 1994 1645 3034 23428 2956 420 3876 c3540 3122 2950 3266 6580 6894 38280 4672 1680 9912 c5315 5220 5132 5304 4183 8506 63542 8140 1068 9852 c6288 7638 7604 10768 7755 23074 114306 9396 1980 29976 c7552 7035 6504 6842 9494 11036 82578 9994 2424 13864 (b) Number of faults and perturbations in equivalent circuit representations a, b, c. While some of these may not be of immediate interest in testing community, these faults and several others from a total set of 255, do provide measurable opportunities to reduce logic [1, 3, 4, 5]. The mutations we consider here are a straightforward extensions of the pairwise stuck-at fault class: namely (ab= i j ). By letting i = 0 we can nd up to 10 perturbation functions j inducing mutations that can only be covered by a pairwise perturbation test. Similarly, we derive other 30 mutation faults in related classes. The last mutation fault, in its own class here only, is the pairwise interchange fault (a $ b). As per Table 1, we considered 47 pairwise mutation faults at the output of each 2-output module, for a total of c j = 47jL2 j (20) jFpw In contrast, the total size of the set of 2-in-2 perturbations jPpw j for the set of output pins in L2 is c j = 22 (22 ? 1)jL2 j = 12jL2 j jPpw (21) We considered two sets of k-in-2 perturbations: jP2 j based on Set B, and jPk j based on Set C.
jP2b j = jPkc j =
jL j X 2k
i1
= 4jL1 j
jL j X 2k
i1
+ (22 ? 1)
1
i1 =1 1
i1 =1
(22) jL j X 2k 2
i2 =1
i2
(23)
In addition, we calculate sizes of bridging fault sets which may well be typical upper and lower bounds if we consider AND and OR bridging fault pairs with respect to all pins on the boundary (Flb ) as well as the internal wires of each module wi ( Fub ) based on Set C.
jFlbc j = jFubc j =
jL j X (k 1
i1 + 1)ki1 +
i1 =1 jL1 j+jL2 j
X i=1
jL j X (k 2
i2 =1
i2 + 2)(ki2 + 1) (24)
wi (wi ? 1)
(25)
We use the concept of perturbations and the related detectability functions as introduced in the preceding section to formulate detectability functions for technologyspeci c faults in a combinational network with multioutput modules.
Theorem 1 Complete detection of 2(p2 ) ? 1 mutation faults in a k-input p-output module is guaranteed by test patterns that detect all 2k (2p ? 1) k-in-p perturbations. k
Proof of Theorem 1 is by construction [1]. Patterns that detect all perturbations clearly also cover all multiple stuck-at and bridging faults on module inputs and outputs. All fault detectability functions can be expressed in terms of the perturbation functions as de ned earlier. In Table 2 we show the covering relations for a subset
355
Table 2: A subset of 255 mutation faults covered by 12 detectable perturbations.
A B
( (
) ) 00) 01) 10) 11) ) 0 1 ) 0 2 ) 0 3 ) 0 4 ) 0 5 ) 0 6 ) 0 7 ) 0 12 ) 0 13 ) 0 14 ) 1 1 )
00
f
g
ab
00
f
g
ab
00
f
g
ab
01
f
g
a::b
( ( ( ( C ( D0 ( ( ( ( ( ( ( ( ( ( D1 (
ajjb
p
g p
ab
10
f
g
ab
10
f
g p
ab
10
f
g
ab
11
f
g
ab
11
f
g
p
p
p p
p p
ab=
ab=
p
ab=
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
ab=
ab
p
p
ab=
g
p
p
ab=
11
f
p
p
ab=
ab
p
p
p
ab=
p
p
p
p
p
p
p
p p
of mutation faults in terms of all 12 detectable perturbations. We list one detectability function for each of the fault classes shown in Table 2. Detectability of pairwise AND-bridging fault (a::b):
(a::b) = fab0 1g + fab1 0g
(26)
Detectability of pairwise stuck-at fault (ab=00):
(27) (ab=00) = fab1 1g + fab1 0g + fab0 1g Detectability of a pairwise interchange fault (a $ b): (28) (a$b) = fab0 1g + fab1 0g Detectability of conditionally stuck-at fault (ab=0 1): (ab=0 1 ) = fab1 1g + fab0 1g + fab1 0g + fab0 0g (29)
The set of all possible perturbation functions f j g that can be considered to construct this table is the following: f j g = f 0 = 0; 1 = f a f b ; 2 = f a fb ; 3 = f a ; 4 = fa f b ; 5 = f b ; 6 = fa fb ; 7 = f a + f b ; 8 = fafb ; 9 = fa fb ; 10 = fb; 11 = fa + fb ; 12 = fa ; 13 = fa + f b ; 14 = fa + fb ; 15=1g. While not shown explicitly, detectability of single stuckat faults (a=0), (a=1) relates to single perturbations as: (30) (a=0) = fa1g ; (a=1) = fa0g To detect any mutation fault of a module with k-inputs and 2-outputs, we have to consider individual minterm perturbations for the sets of all indices I00 ; I01 ; I10 ; I11 of the minterms that decode the output to f00; 01; 10; 11g respectively: i.e. up to 2k (22 ?1) = 32k detectability functions of minterm faults fmj =00; mj =01; mj =10; mj =11g.
m =00 = mab=0 0 + mab=0 0 + mab=0 0 ; 8j 2 I00 (31) ::: = ::: j
01
f
p
ab=
ab=
ab
p
a $ b
ab=
g
p
ab= ab=
01
f
p
ab= ab=
ab
j
j
j
A direct generation of tests for k-in-2 perturbations may generate shortest test sequences but does not reveal the potential and limitations of tests for 1-in-1 and 2-in-2 perturbations. In this contribution, we rst generate tests for 1-in-1 perturbations and evaluate for coverage of 2-in2 perturbations. We complete test generation for 2-in-2 perturbations and use the complete pattern set to evaluate coverage of k-in-2 perturbations. Test generation is completed by nding tests, if they exist, for all detectable k-in-2 perturbations. It may be critical that the detectability of functionality faults fmj =00; mj =01; mj =10; mj =11g are covered for all j as indicated in (31). However, in some cases, similar to ones considered for bridging faults only and for speci c technology in [12], only a speci c subset of j from (31) may be designated as essential for test purposes of speci c modules. V. EXPERIMENTAL RESULTS Our experiments address the following questions: (1) Given a single stuck-at fault model, how e ective are test patterns generated from an unmapped circuit representation such as Set A, Set B to cover single stuck-at faults based on a model of a mapped representation such as given in Set C ? (2) Given a pairwise stuck-at fault model as de ned in Table 2, all detectable pairwise faults are covered by tests for 2-in-2 perturbations. The question arises: can one effectively generate single stuck-at test patterns from any gate-level representation to detect 2-in-2 perturbations and subsequently, pairwise stuck-at faults? (3) All detectable single minterm mutation faults are covered by tests for k-in-2 perturbations. How can one effectively generate single stuck-at test patterns from any gate-level representation to detect k-in-2 perturbations and subsequently, single minterm mutation faults? Experimental results are summarized in Figure 5. All of the data in this gure refers to sum totals of faults and perturbations for the three netlist representations of
356
90000 80000 70000 60000 50000 40000 30000 20000 10000 0 6000 5000 4000 3000 2000 1000 0
1)
AA AA AA AA AA AA AAA AA AAAAAAA AA AAA AA AAA AA AA AA AAA AA AAAAAAA AAAAA AA AAAAAAA AAA AA AAA AA AAAAAAA AAA AAAAA AA AA AA AAAAAAA AA AA AAA AA AAA AAA AA AA AAAAAAAA AAAAA Set sizes of undetectable faults (F) & perturbations (P)
Set sizes of detectectable faults (F) & perturbations (P)
3
2
1
2
|Fa|
|Fb|
|Fce| |Fcpw|
|Pb2| |Pcpw| |Pck|
Set sizes of test patterns (T) for all detectectable faults (F) & perturbations (P)
|Ta|
|Tb|
|Tce|
c |Tb2| |T pw| c Fe
c e detects 99.76% of 34,674 faults in a b detect up to 99.46% of 34,674 T ;T
|Tck|
. faults in ec . c detects up to 83.74% of 9,432 perturbations 2) pw c and up to 99.26% of 36,942 faults in c . in pw pw a b detect up to 82.80% of 9,432 perturbations c and up to 99.17% of 36,942 faults in c . in pw pw c 3) k detects up to 75.82% of 81,804 perturbations in in kc ; remaining perturbations are undetectable! a b c detect up to 64.47% of 81,804 e 2 perturbations in kc. T
F
T
P
T
F
;T
P
F
T
P
T
;T
;T
P
Figure 5: Combined summary of basic experiments. the ISCAS85 circuits shown in Table 2. With each of c ; P c, the fault or perturbation sets, F a ; F b ; Fec, P2b ; Ppw k we associate corresponding sets of test patterns that will cover all detectable faults or perturbations, namely T a ; T b ; Tec ; T2b ; Tpwc ; Tkc . Only the coverage of the set of c , is measured indirectly the postulated pairwise faults, Fpw in terms of other pattern sets. All of the technologyindependent netlists have been made 100% testable by design. This may account in part for the conclusions we can draw from the current state of these experiments. Pattern sets T a ; T b , generated to cover single stuckat faults in technology-independent representation appear highly e ective to cover, on the average, more than 99% of the single-stuck-at faults in the technology-speci c gatelevel model. Additional tests generated in Tec cover additional module-interior gate-level faults, including the additional wiring between the fanout stems. A total of 0.24% of all modeled, module-interior faults were undetectable; tests were found for 99.76% of all modeled faults. While tests for single stuck-at faults T a ; T b cover only 82.80% of 2-in-2 perturbations, they seem to consistently detect over 99% of all detectable perturbations as well as
over c99% of traditional and non-traditional pairwise faults in Fpw as de ned in Table 2. Tests from Pkc cover 75.82% of all k-in-2 detectable perturbations for this set of benchmark circuits. All other perturbations have been proven as undetectable. However, tests from T a ; T2b ; Tec cover only up to 64.47% of k-in-2 perturbations, falling more than 10% short of the range of all detectable k-in-2 perturbations. Tests based on single stuck-at faults are clearly not adequate when considering coverage of non-traditional technology-speci c faults that may be hard to model explicitly. In contrast, tests that cover all possible perturbations will also cover all possible mutations of each multioutput module, including module functionality as well as wiring faults on module boundary. The number of all perturbations in Pkc is 81; 804=34; 674 = 2:36-times the size of the set of all single stuck-at faults currently considered in the technology-mapped model Fec. Test generation based on the detectable perturbation paradigm is comprehensive and less expensive than alternative and incomplete strategies, such as extensions to much larger sets of layout-speci c pairwise bridging faults.
References
[1] A. Z emva and F. Brglez. Detectable Perturbations: A Paradigm for Complete Coverage of Mutation Faults. CBL/NCSU Technical Report 95-CBL-TR04-1. Available, including new benchmark directory, under Publications at http://www.cbl.ncsu.edu/www/, April 1995. [2] M. Roper. Software Testing. McGraw Hill, UK, 1994. [3] A. Z emva, F. Brglez, and K. Kozminski. Functionality Test and Don't Care Synthesis in FPGA ICs. TR93-04, MCNC, Research Triangle Park, N.C., March 1993. [4] A. Z emva, F. Brglez, K. Kozminski, and B. Zajc. A Functionality Fault Model: Feasibility and Applications. In European D & T Conf., pages 152{158, February 1994. [5] B. Roh eisch and F. Brglez. Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. In European D & T Conf., pages 87{93, February 1994. [6] M. Damiani and G. De Micheli. Don't Care Set Speci cations in Combinational and Synchronous Logic Circuits. IEEE Trans. on Computer-Aided Design, CAD12(3):365{388, March 1993. [7] G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw Hill, New York, 1994. [8] M. Abramovici and P. R. Menon. A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. IEEE Trans. on Comp., C-34(7):658{663, July 1985. [9] G.-J. Tromp. Addendum to the ISCAS85 Benchmark Directory. In DAC'93 Edition: ACM/SIGDA Benchmark Newsletter (F. Brglez, Ed.), page 19, June 1993. Available under Publications at http://www.cbl.ncsu.edu/www/. For autoreply about benchmarks, send e-mail to [email protected]. [10] SIS { Release 1.1. UC Berkeley Soft. Distr., Sept. 1992. [11] Xilinx. User Guide and Tutorials. Xilinx Incorporation, 2100 Logic Drive, San Jose, California, 1991. [12] B. Chess and T. Larrabee. Generated Test Patterns for Bridge Faults in CMOS ICs. In European D & T Conf., pages 165{170, February 1994.
357
-- Reprint from 13th IEEE VLSI Test Symposium, Princeton, N.J., April 30 - May 3, 1995
Detectable Perturbations: A Paradigm for Technology-Speci c Multi-Fault Test Generation Andrej Z emva1
Franc Brglez2
1 Electrical & Computer Engineering, University of Ljubljana, Ljubljana, Slovenia 2 CBL (CAD Benchmarking Laboratory), North Carolina State University, Raleigh, N.C. 27695, U.S.A.
(WWW: http://www.cbl.ncsu.edu/www/)
Abstract { This paper introduces the concept of detectable of wires. Just for a pair wires, we can consider 255 cases perturbations as a method to generate tests that can then cover any technology-speci c faults such as multiple bridging, open and stuck-at faults. Rather than devising a customized test pattern generation system for each class of technology-speci c faults, we implemented a generic system to generate tests for single and multiple perturbations. We demonstrate the versatility of this approach by generating tests for a set of large benchmark circuits that have been mapped into single- and multi-output modules. These tests cover single stuck-at, multi-output bridging, stuckat, as well as any mutation faults in the functionality of the technology-mapped cells. Experimental results provide useful insights about the quality of single stuck-at test patterns versus coverages for the additional classes of faults. I. INTRODUCTION Increasing number of technology mappers can now make use of FPGA or standard cell libraries where combinational cells have more than one output. Combining functionality of several single-output modules into a single cell typically reduces both the area occupied by active devices as well as the area taken by the interconnect between the cells. The presence of multi-output cells raises new questions about fault modeling and testing: how e ective is the traditional single stuck-at fault test when considering that module outputs may be pairwise bridging, stuck-at some constant values, may be interchanged, or are simply performing some other function not originally intended. Familiar examples of functional mutations on wires are related to manufacturing defects such as AND/OR bridging faults or pairwise stuck-at faults. Manufacturing defects may subtly change behavior of complex logical nodes in ways not detectable by single stuck-at fault tests. Alternatively, such nodes can also be incorrectly assigned functions during the speci cation phase { for example instead of OR one may well specify XOR and escape detection. In this paper, we address the problem of testing for multi-faults by considering the problem of detecting functional mutations on wires as well as on logic nodes. The space of mutation faults, even without considering mutations of logic nodes, grows exponentially with the number
Andrej Z emva was supported in part by Slovenian Ministry of Research and Technology under grant J2-6188-0781-94FER. Franc Brglez was supported by contracts from the Semiconductor Research Corporation (94-DJ-553), SEMATECH (94-DJ-800), and ARPA/ARO (P-33616-EL/DAAH04-94-G-2080). Xilinx Inc. provided the XACT toolset to generate new technology-mapped benchmark netlists.
of distinct 2-input 2-output functional mutations. Single, pairwise stuck-at and bridging faults are only special cases of such mutations. Rather than devising specialized algorithms to detect each speci c mutation of interest, we introduce a generic concept of detectable perturbations. By detecting a relatively small set of such perturbations, we will have covered completely a much larger set of all possible functional mutations. We demonstrate that detection of such perturbations is closely related to detection of a sequence of independent perturbations from a single source, and can thus use state-of-the-art single stuck-at test generation techniques to generate complete perturbation tests for a set of large benchmark circuits. We motivate the proposed approach in Section 2, then formalize the notion of detectable perturbations in Section 3. In Section 4, we introduce the covering of any mutation fault in terms of detectable perturbations and set up the benchmarking experiment. In Section 5, we report on the experimental results. A more detailed report on this research is available in [1]. II. MOTIVATION Consider a black box with k input pins from the set X and p output pins from the set Z . Nominally, this box realizes a function Z(X ): B k ! B p , representing the behavior of either a hardware module or a software module. Upon embedding into a larger hardware system or a software program, its I/O may no longer be directly accessible to control and to observe. The problem of testing is the same whether the black box contained in the larger system is faulty due to a manufacturing defect, whether its speci cation has been entered incorrectly, or whether an entirely wrong box has been embedded by mistake. The community concerned with testing hardware failures relies to a large extent on single stuck-at (0/1) fault models on the boundary of the box. The community concerned with testing computer programs and speci cations considers the single stuck-at fault models inadequate and attempts to derive alternative strategies [2]. Some of such strategies also consider notions of mutation faults. In the context of the black box with k input pins and p output pins, one may thus consider two extremes: between 2(k + p) single stuck-at faults and 2(p2 ) ? 1 mutation faults. Consider an example with k = 4; p = 2 and two expressions. For purpose of illustration, we share no logic: Z1 = (x1 OR x2 ) OR (x3 OR x4 ); Z2 = (x1 OR x2 ) NOR (x3 OR x4 ):
350
k
A test set f0000; 1000; 0100; 0010; 0001g covers all single stuck-at faults. However, the same test set also covers all single stuck-at faults in these expressions: Z1 = (x1 XOR x2 ) XOR (x3 XOR x4 ); Z2 = (x1 XOR x2 ) NOR (x3 XOR x4 ): In this example, the size of a single stuck-at fault4 set at the pins is simply 2 6 = 12 while there are 2(22 ) ? 1 = 4; 294; 967; 295 mutations that may be considered in the extreme case. Clearly, the choice for a best subset of mutations to generate a 'good test' for most 'typical mutations', given the initial black box speci cation, will continue to be subject of conjectures. What may be a reasoned conjecture for a hardware test, supported by reports of failures during device testing and returns from the eld, may not lead to a good fault model for testing the hardware speci cation in software, and vice versa. The concept of detectable perturbations as introduced in this paper induces tests that will implicitly cover the set of all 2(p2 ) ? 1 mutation faults. Given ka black box with k input and p output pins, we consider 2 minterms, inducing a k-in-p perturbation in up to (2p ? 1) ways onto the p output pins. The upper bound on the set of all perturbations that we will consider is thus 2k (2p ? 1) { a bound much lower than the size of the set of all possible mutations. For the example above, the 4; 294; 967; 295 mutations 4of a2 single module can all be covered by tests for up to 2 (2 ? 1) = 48 perturbations! A directed hypergraph in Figure 1 illustrates the approach to introducing perturbations. Several circuit representations, including one of a multi-output mapped circuit, are shown in Figure 4. Figure 5 focuses on experimental conclusions of this work: the total number of perturbations we need to consider for a set of large benchmark circuit is only 2.36-times the number of single stuckat faults in the equivalent logic representation. However, test patterns based on single stuck-at fault model clearly do not cover a large fraction of detectable perturbations. III. DETECTABLE PERTURBATIONS Traditional single and multiple stuck-at and bridging faults are special cases from the set of mutation faults. We consider a combinational or a sequential synchronous multiple-level Boolean network modeled as a directed hypergraph. In Figure 1 we show an example, including a 4-in-3 perturbation. More speci c illustrations are introduced in Figures 2 and 3. Several representations of the same example are shown in Figure 4a-c. Figure 4a is the initial circuit speci cation graph, Figure 4b is the optimized granular representation of the same circuit, and Figure 4c is the hypergraph created after the technology mapping into a speci c library set. Note that while circuits in Figures 4a-b are DAGs, the hypergraph in Figure 4c has a pseudo-cycle. Mutation faults can be associated with wires as well as logic nodes. Boolean network. We model this network as a directed hypergraph G = (V ; E ). Since we will relate nodes and wires in this graph to fault sets later on, we will refer to edges in this graph as wires and elements of the vertex set as nodes. All nodes are considered to be of one of the following types: primary and pseudo-primary inputs (PIs, PPIs), primary and pseudo-primary outputs (POs, k
PPOs), register nodes, cluster nodes, and fanout nodes. By de nition, all register nodes are implicitly synchronized with a single clock, have a single data input driven by a pseudo-primary output node and a single data output sourced by a pseudo-primary input node. A cluster node can have any number of inputs and any number of outputs, each output can describe a logic function of arbitrary complexity. Each cluster node is a DAG where, by de nition, all logic nodes have single outputs only. By replacing all cluster nodes in the hypergraph with their respective graph representation, we have a DAG between (PIs, PPIs) and (POs, PPOs). Note however, that the hypergraph itself may have pseudo-cycles when viewed in terms of cluster nodes. This is illustrated in Figure 4a-c. A fanout node in a hypergraph or a graph has a single input and any number of outputs. A fanout node may or may not drive another fanout node. In case where fanout node does not drive another fanout node, we say that the interconnect is simple, otherwise, the interconnect is non-simple. Note that when considering a technologymapped representation or any layout-speci c implementation fanout nodes are partitioned and connected with wires as illustrated in Figure 4c which shows a network mapped into a speci c technology. All wires have a unique label. For logic nodes we use the same label as for their outgoing edge. Similarly, we use the same label for a fanout node and its incoming edge. With each wire ei we associate a Boolean function fe . The complement of the function associated with wire ei is denoted as f e . We will refer to the logic node in this graph interchangeably also as a logic module, or a logic cell. For additional details on notation, see also [3, 4, 5, 6]. Detectable k-in-p perturbations. A k-in-p perturbation requires evaluation of a perturbation function of k decoding wires and injecting a perturbation signal onto a set of up to p perturbed wires. A perturbation is injected onto any of the perturbed wires if and only if the signal values on the decoding wires satisfy the on-set of the perturbation function . The example in Figure 1 illustrates the case where is represented by a single minterm or decoding gate m6 . Its output is 1 if and only if values on the decoding wires fx2 ; n2 ; n5 ; n4 g carry the signals f0110g. Each of the perturbed wires is an output of the XOR 'bridge gate' driven by the output from the perturbation function and the nominal wire. In the example shown, the nominal wires are fa; b; cg and the perturbed wires are fa; b ; c g. The perturbation as de ned here can introduce a cycle into the hypergraph and potentially cause asynchronous oscillations between each or some of the clock cycles. The key question that arises is whether such perturbations are detectable at any of the primary outputs in Z . Perturbations as de ned here generalize and unify the work in [3, 4, 5]. In this paper, we relate detectability of perturbations to detectability of bridging and multi-faults with a single test pattern rather than test pattern sequences. Hence, all subsequent formulations assume detectability of each perturbation in a single time frame. All PPIs and PPOs are thus assumed scannable. We denote all PIs and PPIs as x = (x0 ; x1 :::), and all POs and PPOs as Z = (Z0 ; Z1:::). The detectability function of any perturbation on the perturbed wires a ; b ; c ; ::: is thus de ned as a Boolean
351
i
i
AA AA
Alternative Formulations. While complex, the notation presented here is designed to relate closely to the generic perturbation model as illustrated in Figure 1. Detectability of perturbations on wires a ; b ; c is subject to the signal value on the decoding gate and the propagation status of each of the induced perturbations. The de nitions of perturbation in [6, 7] di er from the ones introduced here. As illustrated for the simple circuit in Figure 2, used originally in [6, 7], each perturbation introduces an extra input with a constant signal of '1'. As a result, it computes the observability function of the perturbed wire without regard to any speci c assignment to this wire. In contrast, the 1-to-1 perturbation as de ned in (1), introduces no extra input to the perturbed circuit and computes the detectability function as expressed in (1) which directly relates to the single stuck-at fault detectability. According to the familiar de nitions, including ones in [6, 7], the perturbation in the circuit example in Figure 2 is both controllable and observable, and yet, this perturbation is not detectable! By inspection, we also nd that the single stuck-at 1 fault on the wire with perturbation is not detectable.
m6
x0 x1 x2 x3
n4
b*
n1
n7
b a*
a
n2
Z0
n8
c* c
x4
Y1
n5
y2
AA AA
Y0
n6
y1 y0
n3
Y2
= 0 1 n2 = 3 + 4 n3 = 1 0 a = 2 n2 n4 = n1 + a n5 = a n3 n1
x :x
f
f
x
f
y :y
x
f
x :f
f
f
f
= a+ 2 b = n4 + n5 c = n4 n5 n7 = b 2 n8 = c n6
f
f f
f
f
f
y
f
:f
f
f :y
f
f
f :f
f
b
Figure 1: A Boolean network with a 4-in-3 perturbation.
P
X Z (x) Z (x)j r
r
r
where r designates OR-ing the respective functions for all outputs. Speci cally, for the example in Figure 1 where k = 4 and p = 3, and assuming that primary inputs are assigned such that when the decoding wires fx2 ; n2 ; n5 ; n4 g carry the signals f0110g, the perturbed wires a ; b ; c carry the signals f001g which are complements of the nominal signal values f110g. In our notation, we will denote the complementation of the signals on the perturbed wires as f1 1 0g. The detectability function for a 4-in-3 perturbation, expanding on (1), is thus
ma6=b1 c1 0 =
X Z (x; a = f ; b = f ; c = f ) r
r
a
b
c
b1*
a
a
b2 c (b) observable perturbation on b1*
signal observabilities on the inputs of XOR are identical to signal observabilities on the XOR output.
b*
b
a
a*
b
b*
(b) Cases of 2-in-2 perturbation a
m6
(3)
For simplicity of notation, we will from now on refer to
a*
a
a
a*
b
which evaluates to
rather than to ma6=b1 c1 0 . This is permissible since mabc 6 =1 1 0
z
b1* y
a*
a*
a
b
X
1
(a) Cases of 1-in-1 perturbation
(2)
where we de ne the perturbation observability O1abc1 0 as a b c = O1abc1 0 = Oabc Zr (x; a = fa; b = fb ; c = f c ) r Zr (x; a = f a ; b = f b ; c = fc ) (4)
b1
b
y
Zr (x; a = fa fm6 ; b = fb fm6 ; c = f c fm6 ) mabc = ma6 =b1 c1 0 = fm6 O1abc1 0 6 =1 1 0
x
a z
Figure 2: An undetectable but observable perturbation.
(1)
b1
b2 c (a) undetectable perturbation on b1*
di erence of the nominal and the perturbed network:
ab c ::: =
x
a
b
b*
m6
a
a*
b
b*
m6
(c) Cases of k-in-2 perturbation
Figure 3: Modeling of various k-in-p perturbations. Special Cases. The perturbations in Figure 3a-b illustrate special cases of p-in-p perturbations, for p = 1 and p = 2. Here, the decoding wires have 1-to-1 relationship to the perturbed wires and we simplify the notation for the corresponding detectability functions. For example, we de ne the detectability of a 2-in-2 perturbation of both wires that carry the signals f11g as
352
X Z (x; a = f ; b = f )
fa11bg =
r a b r Zr (x; a = fa fafb ; b = fb fa fb )
(5)
j
which evaluates to
X Z (x; a = f ; b = f ) r a b r Zr (x; a = f a ; b = f b )
(6) (7)
Similarly, we write for the detectability of a 2-in-2 perturbation that carries the signals f11g and where only the wire a is perturbed:
X Z (x; a = f ; b = f )
fa11bg =
r a b r Zr (x; a = fa fa fb ; b = fb )
(8)
which evaluates to
fab1 1g = fa fb O1ab1
and
O1ab1 =
i
i
fab1 1g = fa fb O1ab1
O1ab1 =
Perturbation Equivalence Classes. Both 2-in-2 and k-in-2 perturbations can be classi ed into 8 equivalence classes with important properties [1]. As a consequence, we would consider computing mab=00 if and only if fab 00g 6= 0. ab ab ab Similar corollaries hold for f01g , f10g , and f11g . Oscillating perturbations. When perturbations introduce a cycle, we can observe e ects similar to the feedback bridging faults reported in [8]. Oscillating perturbations as de ned here are analyzed in more detail in [1]. We refer to a k-in-p perturbation as a cyclic perturbation if there is at least one path between p and k wires. If there is no such path, the perturbation is denoted as an acyclic perturbation or simply a perturbation. The k-in-p cyclic perturbation causes the circuit to oscillate whenever the perturbed signal on any of the p perturbed wires propagates to any of k decoding wires. Such a perturbation is denoted as oscillating perturbation. A perturbation which does not induce oscillation is a stable perturbation. All acyclic perturbations are stable. We can analyze the e ects of perturbations using the familiar D calculus. In a sequential circuit, a perturbation may be stable in one time frame while it can oscillate in another time frame. Consider the perturbation (m13 =0 0 1) in Figure 1: the decoding wires are fx2 ; n2 ; n5 ; n4 g and the perturbed wires are fa ; b ; c g. Assume that all ip- ops are reset in time frame 0. Perturbation is stable and undetected during time frame 0, since the D signal at line a can propagate only through node n6 and ip- op Y0 in time frame 1. In time frame 1, D is propagated through node n5 and the injected perturbation oscillates. Assuming that the values on all combinational modules are stable after 1/2 the clock period, then the circuit, considering no change at the PIs, returns into its nominal state just before the next clock signal. In time frame 2, the condition for the perturbation is satis ed again and the perturbation is reinjected, appearing as a stable and undetectable. Since this perturbation oscillates during every odd time frame, its period is 2. For circuit in Figure 4c, we note the following. A 2-in-2 perturbation (c4 c16 =f0 0g) is a detectable stable perturbation, while the 4-in-2 perturbation (m4 =0 1), with decoding wires fx4 ; x1 ; x3 ; c9 g and perturbed wires fc11 ; c12 g, is stable but undetectable. The perturbation (m24 =0 1), with decoding wires fx6 ; x7 ; x3 ; x8 ; c9 g and perturbed wires fc4 ; c16 g, induces an oscillation. While propagating the perturbation signal D to PO z4 , D is also propagated through node c6 onto the decoding wire c9 , canceling the perturbation. In this work we report all oscillating perturbations propagating to POs as detectable. Undetectable oscillating perturbations are shown in [1]. IV. DETECTABILITY OF MUTATION FAULTS We prepared three logically equivalent sets of large benchmark netlists on which we performed experiments reported in the last section of this paper. In this section we analyze their characteristics as they relate to mutation faults and perturbations. All benchmarks are derivatives of the ISCAS85 set [9] as follows. Set A: 100% testable netlist in [9]. Set B: an optimized representation of netlists from the Set A. We used SIS [10] with option map -m 0. In addition to the inverter, there are four types of 2-input logic gates in
X Z (x; a = f ; b = f ) r a b r Zr (x; a = f a ; b = fb )
(9) (10)
All cases of detectability functions related to the illustrations in Figure 3 thus summarize as follows: For any 1-in-1 perturbation we consider 2 (2 ? 1) = 2 detectability functions:
fa1g = fa O1a
fa0g = fa O0a ;
(11)
For any 2-in-2 perturbation we consider up to 22 (22 ? 1) = 12 detectability functions: (12) = f a f b O0ab0 ab = f a f b O0 0 (13) = f a f b O0ab0 (14) = ::: For any k-in-2 perturbation, where I00 ; I01 ; I10 ; I11 denote the sets of all indices of the minterms that decode the output to f00; 01; 10; 11g respectively, we consider up to 2k (22 ? 1) = 3 2k detectability functions:
fab0 0g fab0 0g fab0 0g :::
mab=0 0 = fm O0ab0 ; 8j 2 I00 (15) (16) mab=0 0 = fm O0ab0 ; 8j 2 I00 ab ab m =0 0 = fm O0 0 ; 8j 2 I00 (17) ::: = ::: We can show that O1a = O0a , O1ab1 = O0ab0 and O0ab1 = O1ab0 . j
j
j
j
j
j
353
i
i
this netlist representation, performing following functions on inputs a; b: ab, ab, a + b, a + b. This choice of logic primitives results in few if any inverters.
a1
x1 x2
Set C: a technology-mapped representation of the netlists from the Set B, using SIS technology mapper for benchmarks c499, c1355, c6288 and XACT technology mapper [11] for the remaining 7 benchmarks. For purposes of this experiment, we chose the mapped netlist from the mapper that generated the largest number of 2-output modules and reported lower fanout at module-level. This is now a hierarchical netlist based on large single and twooutput modules, with each module represented by a gatelevel logic primitive type described in Set B. Our choice of technology mapper such as XACT provided a large variety of cell functions with logic overlap that we wanted to consider in this study.
The representations of a simple circuit c44 in Figure 4 have all the attributes described. The node and the wiring characteristics of these three representations are summarized in Table 1. For example, jLa j, jQa j denote theanumber of logic and fanout nodes in circuits, and jW j denotes the number of 2-point wire connections in any of the netlist from the Set A. In case that the logic node drives a primary output only, we remove any output bu ers on this line. For netlists in the Set C, we report two representations: module level in terms of 1-output and 2-output modules jLc1 j, jLc2 j respectively,c and gate level in terms of single output logic gates jLe j that represent the total number of logic nodes in the interior to each module. Notably, while the interconnect at module level is simple, this is no longer the case when we expand each module to logic level. As illustrated in the example in Figure 4, fanout nodes may drive other fanout nodes. For purpose of test generation and more accurate modeling of layoutspeci c fault dependencies, such a model can be useful. Thec numbercof fanout nodes and wires, as expressed by jQe j and jWe j, fully accounts for this approach. This in uences the resulting test generation and fault coverage we report in our experiments. Our test generator extends the concepts introduced in [4] and targets k-in-p perturbations. Given the circuit parameter sizes in Table 1 and formulas introduced earlier, we report the sizes of perturbation and faults in Table 1. For example, jF a j, jF b j, jFec j are sizes of single stuck-at fault sets to be covered by tests for 1-in-1 perturbations. c j is the number of pairwise faults to be covered by jFpw c as speci ed tests for 2-in-2 perturbations in the set Ppw in Table 2. jP2b j denotes the size of perturbations for 2in-1 perturbations in netlists from the Set B; jPkcj denotes the size of perturbations associated with k-in-2 perturbations for netlists from the Set C. For netlists in cset C cwe are also reporting lower and upper bounds (jFlb j, jFub j) for pairwise bridging faults. We developed a set of simple formulas that relate to sizes of all parameters listed in Table 1. Let L1 , L2 Q, Z denote the sets of 1-output, 2-output logic nodes, fanout nodes, and PO nodes respectively, and let ki1 and ki2 be the number of inputs incident at 1-output and 2-output logic nodes. Then, for any circuit, such as shown in Figure
a5
z1
a9
a6
a10
z2
a11
z3
a2
x3 x4 x5
initial netlist representation
a7
a3 x6
a4
x7
(a)
(specification)
z4
a12 a8 a13
z5
x8
x1 x2
z1
b10
b1
b8
b5
z2
b11
(b)
b2
x3 x4 x5
z3
b12
b6 b9
granular netlist representation
b3 x6
b4
x7
intermediate
z4
b13 b7 b14 b16
b15
x8
(may be optimized)
z5
c10 c1
c5
z1
c8
x1
AAAA AAAA AAAA AAAA x2
x3 x4
(c)
z2
c12
z3
x5
final
technologymapped netlist
c11 c2
x6
c3
c9 c6
c4
c7
x7
c13
z4
c14
representation
c16
z5
x8
c15
Figure 4: Equivalent Boolean network representations. 4a-c, the number of wires (or edges) is simply
jWj =
jL j jL j X X k + k 2
1
i1 =1
i1
i2 =1
i2 + jQj + jZj
(18)
Consider netlists of simple gate primitives such as shown in Figure 4a-c. Let jL1 j be the number of such gates, excluding inverters and bu ers. Then, the size of the set of equivalence-collapsed set of faults is simply
jFj =
Xk jL1 j
i1 =1
i1 + 2(jQj + jZj)
(19)
Traditionally, following 6 mutation faults are considered: (a::b) AND-bridging faults on wires a; b OR-bridging faults on wires a; b (ajjb) (ab=00) stuck-at/00 fault pair on wires a; b (ab=01) stuck-at/01 fault pair on wires a; b (ab=10) stuck-at/10 fault pair on wires a; b (ab=11) stuck-at/11 fault pair on wires a; b To illustrate the generality of our approach, we postulate and report in this paper on 41 additional mutation faults.
354
Table 1: Sizes of node, wire, and fault sets for the circuit representations a, b, c such as shown in Figure 4.
c44 c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552
jXj jZj jLa j jQa j jW a j
8 36 41 60 41 33 233 50 178 32 207
5 7 32 26 32 25 139 22 123 32 108
jLb j jQb j jW b j jLc1 j jLc2 j jQc j jW c j jLce j jQce j jWec j
13 10 44 16 10 47 1 3 6 29 16 11 48 157 86 419 169 72 414 21 26 61 269 169 98 440 202 59 491 406 155 999 28 20 61 317 412 311 1161 357 125 854 347 115 834 40 43 82 441 340 196 888 514 259 1315 510 259 1311 24 24 55 321 448 335 1257 878 383 1896 610 187 1432 70 42 92 565 560 318 1433 1014 327 2147 797 173 1779 92 35 69 676 609 297 1606 1610 511 3309 1168 293 2643 117 140 164 1224 1150 537 2783 2288 792 5210 2059 437 4625 275 89 259 1797 1733 884 4385 2399 1438 6218 2349 1422 6151 628 165 728 4464 3760 1642 9144 3395 1197 7173 2524 678 5776 279 202 367 2236 2190 1227 5611 (a) Number of nodes and wires in equivalent circuit representations a, b, c.
jF a j jF b j
c j jFec j jFpw
jFlbc j
jFubc j
c j jP2b j jPpw
jPkc j
c44 57 62 68 141 132 464 64 36 224 c432 471 490 542 1222 1402 4104 676 312 2312 c499 542 1186 1498 940 1520 26668 1624 240 2560 c880 942 974 1096 2021 2178 10958 1386 516 3140 c1355 1566 1602 1618 1128 1664 32072 2040 288 2912 c1908 1862 1644 1746 1947 2734 22330 2440 504 3400 c2670 2086 1964 1994 1645 3034 23428 2956 420 3876 c3540 3122 2950 3266 6580 6894 38280 4672 1680 9912 c5315 5220 5132 5304 4183 8506 63542 8140 1068 9852 c6288 7638 7604 10768 7755 23074 114306 9396 1980 29976 c7552 7035 6504 6842 9494 11036 82578 9994 2424 13864 (b) Number of faults and perturbations in equivalent circuit representations a, b, c. While some of these may not be of immediate interest in testing community, these faults and several others from a total set of 255, do provide measurable opportunities to reduce logic [1, 3, 4, 5]. The mutations we consider here are a straightforward extensions of the pairwise stuck-at fault class: namely (ab= i j ). By letting i = 0 we can nd up to 10 perturbation functions j inducing mutations that can only be covered by a pairwise perturbation test. Similarly, we derive other 30 mutation faults in related classes. The last mutation fault, in its own class here only, is the pairwise interchange fault (a $ b). As per Table 1, we considered 47 pairwise mutation faults at the output of each 2-output module, for a total of c j = 47jL2 j (20) jFpw In contrast, the total size of the set of 2-in-2 perturbations jPpw j for the set of output pins in L2 is c j = 22 (22 ? 1)jL2 j = 12jL2 j jPpw (21) We considered two sets of k-in-2 perturbations: jP2 j based on Set B, and jPk j based on Set C.
jP2b j = jPkc j =
jL j X 2k
i1
= 4jL1 j
jL j X 2k
i1
+ (22 ? 1)
1
i1 =1 1
i1 =1
(22) jL j X 2k 2
i2 =1
i2
(23)
In addition, we calculate sizes of bridging fault sets which may well be typical upper and lower bounds if we consider AND and OR bridging fault pairs with respect to all pins on the boundary (Flb ) as well as the internal wires of each module wi ( Fub ) based on Set C.
jFlbc j = jFubc j =
jL j X (k 1
i1 + 1)ki1 +
i1 =1 jL1 j+jL2 j
X i=1
jL j X (k 2
i2 =1
i2 + 2)(ki2 + 1) (24)
wi (wi ? 1)
(25)
We use the concept of perturbations and the related detectability functions as introduced in the preceding section to formulate detectability functions for technologyspeci c faults in a combinational network with multioutput modules.
Theorem 1 Complete detection of 2(p2 ) ? 1 mutation faults in a k-input p-output module is guaranteed by test patterns that detect all 2k (2p ? 1) k-in-p perturbations. k
Proof of Theorem 1 is by construction [1]. Patterns that detect all perturbations clearly also cover all multiple stuck-at and bridging faults on module inputs and outputs. All fault detectability functions can be expressed in terms of the perturbation functions as de ned earlier. In Table 2 we show the covering relations for a subset
355
Table 2: A subset of 255 mutation faults covered by 12 detectable perturbations.
A B
( (
) ) 00) 01) 10) 11) ) 0 1 ) 0 2 ) 0 3 ) 0 4 ) 0 5 ) 0 6 ) 0 7 ) 0 12 ) 0 13 ) 0 14 ) 1 1 )
00
f
g
ab
00
f
g
ab
00
f
g
ab
01
f
g
a::b
( ( ( ( C ( D0 ( ( ( ( ( ( ( ( ( ( D1 (
ajjb
p
g p
ab
10
f
g
ab
10
f
g p
ab
10
f
g
ab
11
f
g
ab
11
f
g
p
p
p p
p p
ab=
ab=
p
ab=
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
p
ab=
ab
p
p
ab=
g
p
p
ab=
11
f
p
p
ab=
ab
p
p
p
ab=
p
p
p
p
p
p
p
p p
of mutation faults in terms of all 12 detectable perturbations. We list one detectability function for each of the fault classes shown in Table 2. Detectability of pairwise AND-bridging fault (a::b):
(a::b) = fab0 1g + fab1 0g
(26)
Detectability of pairwise stuck-at fault (ab=00):
(27) (ab=00) = fab1 1g + fab1 0g + fab0 1g Detectability of a pairwise interchange fault (a $ b): (28) (a$b) = fab0 1g + fab1 0g Detectability of conditionally stuck-at fault (ab=0 1): (ab=0 1 ) = fab1 1g + fab0 1g + fab1 0g + fab0 0g (29)
The set of all possible perturbation functions f j g that can be considered to construct this table is the following: f j g = f 0 = 0; 1 = f a f b ; 2 = f a fb ; 3 = f a ; 4 = fa f b ; 5 = f b ; 6 = fa fb ; 7 = f a + f b ; 8 = fafb ; 9 = fa fb ; 10 = fb; 11 = fa + fb ; 12 = fa ; 13 = fa + f b ; 14 = fa + fb ; 15=1g. While not shown explicitly, detectability of single stuckat faults (a=0), (a=1) relates to single perturbations as: (30) (a=0) = fa1g ; (a=1) = fa0g To detect any mutation fault of a module with k-inputs and 2-outputs, we have to consider individual minterm perturbations for the sets of all indices I00 ; I01 ; I10 ; I11 of the minterms that decode the output to f00; 01; 10; 11g respectively: i.e. up to 2k (22 ?1) = 32k detectability functions of minterm faults fmj =00; mj =01; mj =10; mj =11g.
m =00 = mab=0 0 + mab=0 0 + mab=0 0 ; 8j 2 I00 (31) ::: = ::: j
01
f
p
ab=
ab=
ab
p
a $ b
ab=
g
p
ab= ab=
01
f
p
ab= ab=
ab
j
j
j
A direct generation of tests for k-in-2 perturbations may generate shortest test sequences but does not reveal the potential and limitations of tests for 1-in-1 and 2-in-2 perturbations. In this contribution, we rst generate tests for 1-in-1 perturbations and evaluate for coverage of 2-in2 perturbations. We complete test generation for 2-in-2 perturbations and use the complete pattern set to evaluate coverage of k-in-2 perturbations. Test generation is completed by nding tests, if they exist, for all detectable k-in-2 perturbations. It may be critical that the detectability of functionality faults fmj =00; mj =01; mj =10; mj =11g are covered for all j as indicated in (31). However, in some cases, similar to ones considered for bridging faults only and for speci c technology in [12], only a speci c subset of j from (31) may be designated as essential for test purposes of speci c modules. V. EXPERIMENTAL RESULTS Our experiments address the following questions: (1) Given a single stuck-at fault model, how e ective are test patterns generated from an unmapped circuit representation such as Set A, Set B to cover single stuck-at faults based on a model of a mapped representation such as given in Set C ? (2) Given a pairwise stuck-at fault model as de ned in Table 2, all detectable pairwise faults are covered by tests for 2-in-2 perturbations. The question arises: can one effectively generate single stuck-at test patterns from any gate-level representation to detect 2-in-2 perturbations and subsequently, pairwise stuck-at faults? (3) All detectable single minterm mutation faults are covered by tests for k-in-2 perturbations. How can one effectively generate single stuck-at test patterns from any gate-level representation to detect k-in-2 perturbations and subsequently, single minterm mutation faults? Experimental results are summarized in Figure 5. All of the data in this gure refers to sum totals of faults and perturbations for the three netlist representations of
356
90000 80000 70000 60000 50000 40000 30000 20000 10000 0 6000 5000 4000 3000 2000 1000 0
1)
AA AA AA AA AA AA AAA AA AAAAAAA AA AAA AA AAA AA AA AA AAA AA AAAAAAA AAAAA AA AAAAAAA AAA AA AAA AA AAAAAAA AAA AAAAA AA AA AA AAAAAAA AA AA AAA AA AAA AAA AA AA AAAAAAAA AAAAA Set sizes of undetectable faults (F) & perturbations (P)
Set sizes of detectectable faults (F) & perturbations (P)
3
2
1
2
|Fa|
|Fb|
|Fce| |Fcpw|
|Pb2| |Pcpw| |Pck|
Set sizes of test patterns (T) for all detectectable faults (F) & perturbations (P)
|Ta|
|Tb|
|Tce|
c |Tb2| |T pw| c Fe
c e detects 99.76% of 34,674 faults in a b detect up to 99.46% of 34,674 T ;T
|Tck|
. faults in ec . c detects up to 83.74% of 9,432 perturbations 2) pw c and up to 99.26% of 36,942 faults in c . in pw pw a b detect up to 82.80% of 9,432 perturbations c and up to 99.17% of 36,942 faults in c . in pw pw c 3) k detects up to 75.82% of 81,804 perturbations in in kc ; remaining perturbations are undetectable! a b c detect up to 64.47% of 81,804 e 2 perturbations in kc. T
F
T
P
T
F
;T
P
F
T
P
T
;T
;T
P
Figure 5: Combined summary of basic experiments. the ISCAS85 circuits shown in Table 2. With each of c ; P c, the fault or perturbation sets, F a ; F b ; Fec, P2b ; Ppw k we associate corresponding sets of test patterns that will cover all detectable faults or perturbations, namely T a ; T b ; Tec ; T2b ; Tpwc ; Tkc . Only the coverage of the set of c , is measured indirectly the postulated pairwise faults, Fpw in terms of other pattern sets. All of the technologyindependent netlists have been made 100% testable by design. This may account in part for the conclusions we can draw from the current state of these experiments. Pattern sets T a ; T b , generated to cover single stuckat faults in technology-independent representation appear highly e ective to cover, on the average, more than 99% of the single-stuck-at faults in the technology-speci c gatelevel model. Additional tests generated in Tec cover additional module-interior gate-level faults, including the additional wiring between the fanout stems. A total of 0.24% of all modeled, module-interior faults were undetectable; tests were found for 99.76% of all modeled faults. While tests for single stuck-at faults T a ; T b cover only 82.80% of 2-in-2 perturbations, they seem to consistently detect over 99% of all detectable perturbations as well as
over c99% of traditional and non-traditional pairwise faults in Fpw as de ned in Table 2. Tests from Pkc cover 75.82% of all k-in-2 detectable perturbations for this set of benchmark circuits. All other perturbations have been proven as undetectable. However, tests from T a ; T2b ; Tec cover only up to 64.47% of k-in-2 perturbations, falling more than 10% short of the range of all detectable k-in-2 perturbations. Tests based on single stuck-at faults are clearly not adequate when considering coverage of non-traditional technology-speci c faults that may be hard to model explicitly. In contrast, tests that cover all possible perturbations will also cover all possible mutations of each multioutput module, including module functionality as well as wiring faults on module boundary. The number of all perturbations in Pkc is 81; 804=34; 674 = 2:36-times the size of the set of all single stuck-at faults currently considered in the technology-mapped model Fec. Test generation based on the detectable perturbation paradigm is comprehensive and less expensive than alternative and incomplete strategies, such as extensions to much larger sets of layout-speci c pairwise bridging faults.
References
[1] A. Z emva and F. Brglez. Detectable Perturbations: A Paradigm for Complete Coverage of Mutation Faults. CBL/NCSU Technical Report 95-CBL-TR04-1. Available, including new benchmark directory, under Publications at http://www.cbl.ncsu.edu/www/, April 1995. [2] M. Roper. Software Testing. McGraw Hill, UK, 1994. [3] A. Z emva, F. Brglez, and K. Kozminski. Functionality Test and Don't Care Synthesis in FPGA ICs. TR93-04, MCNC, Research Triangle Park, N.C., March 1993. [4] A. Z emva, F. Brglez, K. Kozminski, and B. Zajc. A Functionality Fault Model: Feasibility and Applications. In European D & T Conf., pages 152{158, February 1994. [5] B. Roh eisch and F. Brglez. Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping. In European D & T Conf., pages 87{93, February 1994. [6] M. Damiani and G. De Micheli. Don't Care Set Speci cations in Combinational and Synchronous Logic Circuits. IEEE Trans. on Computer-Aided Design, CAD12(3):365{388, March 1993. [7] G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw Hill, New York, 1994. [8] M. Abramovici and P. R. Menon. A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. IEEE Trans. on Comp., C-34(7):658{663, July 1985. [9] G.-J. Tromp. Addendum to the ISCAS85 Benchmark Directory. In DAC'93 Edition: ACM/SIGDA Benchmark Newsletter (F. Brglez, Ed.), page 19, June 1993. Available under Publications at http://www.cbl.ncsu.edu/www/. For autoreply about benchmarks, send e-mail to [email protected]. [10] SIS { Release 1.1. UC Berkeley Soft. Distr., Sept. 1992. [11] Xilinx. User Guide and Tutorials. Xilinx Incorporation, 2100 Logic Drive, San Jose, California, 1991. [12] B. Chess and T. Larrabee. Generated Test Patterns for Bridge Faults in CMOS ICs. In European D & T Conf., pages 165{170, February 1994.
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