Deterministic Flow Lines With Applications - Semantic Scholar
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Deterministic Flow Lines With Applications James R. Morrison, Member, IEEE
Abstract—We demonstrate that flow line models with deterministic service times and an arbitrary arrival process may be exactly decomposed into segments that each exhibit similar behavior. We call the segments channels and demonstrate that this decomposition leads to a recursion for the delay experienced by customers within the system. The consequence, in addition to clearly elucidating the manner in which customers advance, is that the state of a flow line at any time can be completely characterized by a handful of parameters per channel. The recursions and channel decomposition allow us to model a class of state dependent failures that are common in certain cluster tools in semiconductor wafer manufacturing. Using the fact that wafers are typically grouped into batches, we are able to reduce the computation required to simulate the wafer advancement by about 50 times. The models have been tested with data from a clustered photolithography tool in production and provide throughput and process time predictions within 0.5% and 3% of the actual performance, respectively. Note to Practitioners—Flow line models can be used to model assembly lines, tandem manufacturing systems, and robotic work cells such as cluster tools. In semiconductor wafer fabrication, generic cluster tools have become increasingly important and the class of clustered photolithography tools are essential to production. We develop deterministic flow line models allowing for setups that depend on the location of wafers within a tool. A reduction in computational complexity is achieved by noting that wafers are often grouped into wafer lots. Tests of the models against actual production data for clustered photolithography tools have shown that the reduction in computation required to simulate production with setups is on the order of 50 times, while still achieving a throughput and cycle time accuracy of 0.5% and 3%, respectively. Thus, for important classes of tools, the models are good candidates for use in simulation and to determine a tool’s intrinsic equipment loss (that is, the throughput loss caused by setups, tool structure, and tool failures). Index Terms—Discrete-event simulation, flow line, photolithography cluster tools, semiconductor manufacturing automation.
I. INTRODUCTION ITH an eye toward application to the performance analysis of cluster tools in semiconductor wafer fabrication, we study flow lines with deterministic service times. Flow lines are also called assembly lines or tandem queues and have been studied for many years. There exists a rich and diverse body of work addressing their performance and design. For general
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Manuscript received December 18, 2008; revised April 29, 2009. First published October 13, 2009; current version published April 07, 2010. This paper was recommended for publication by Associate Editor Q. Zhao and Editor M. Zhou upon evaluation of the reviewers’ comments. The author is with the Department of Industrial and Systems Engineering and the KAIST Institute for the Design of Complex Systems, KAIST, Daejeon 305-701, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TASE.2009.2027222
overviews of flow line models, one may consider survey papers such as [1] and [2] or texts such as [3] and [4]. Early key results on flow lines with deterministic service times and reliable servers date back to 1965 [5], [6]. In [5], it is shown that the total queue time of a customer is independent of the order of servers, a buffer can be modeled as a server with zero process time and the mean queue time is the same as in a G/D/1 queue. Extensions for batch arrivals and practical complications are discussed in [7]–[10]. Further investigations on maximum throughput with probabilistic service times, different kinds of blocking for server attention, server ordering and buffer levels have been conducted in [11]–[15], to mention a few of the most closely related studies. Since the key results of [5] and [6] in 1965, there has been little additional insight into the behavior of deterministic flow lines with reliable servers, a single class of customer and an arbitrary arrival process. It is known that the maximum throughput of such flow lines is equal to the bottleneck server rate. The work of [5] provides a recursion for customer exit times from the system. However, it is not known whether there is additional structure to the advancement of customers within the system. To wit, as stated in the well-known text by Altiok ([4, pp. 158]) “[T]here are no known techniques to obtain measures specific to particular buffers, such as the probability distribution of the buffer contents.” In this paper, we prove the following results. • Within subsets of the servers that we call channels, the customer delay is well structured (Theorem 4). • A recursion for the channel delays exists and requires only a handful of parameters; the delay at each server is implied by the channel delay (Theorem 5). • A flow line is characterized by its constituent channels. That is, the channels serve as an exact structural decomposition (Theorem 6). The channel decomposition is characterized by dominating stations [6], [16], [17], which are defined as those servers whose process times are strictly greater than all preceding servers. To determine the state of a customer within the flow line at a given time without using these structural observations, one must resort to the elementary evolution equations and calculate the entry times, service completion times, and queueing at each server. Our application area of interest is semiconductor wafer manufacturing and we will show that, in addition to elucidating the manner in which customers traverse the system, there is utility to the insight gleaned. It is common for semiconductor wafer fabricators, referred to as fabs hereafter, to employ fab-wide simulation models of production to predict system throughput and cycle time. These models simulate the progress of wafer lots through hundreds of tool groups and are used to assess the consequence of changes to production control policies, product mix, tool capacity, etc. Invariably, each of the many tool group
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models specifies parameters such as throughput rate, first wafer delay, setup time, maximum batch size, uptime duration and downtime duration, among others. For many tools, these parameters are sufficient for reliable cycle time and throughput predictions. This is particularly true when there are few interruptions to production and few product changeovers. However, as discussed in [18] and later [8] and [9], disturbances to production can be quite common and have dramatic consequences. Further, with the impending proliferation of small lot sizes and diversity of product mix brought about by the anticipated development of 450 mm wafer fabs, setups and internal buffers will have a greater role to play in system behavior [19]. Loosely speaking, the tools will most often be operating in a transient mode. For cluster tools, in particular clustered photolithography tools, the typical simulation parameters do not account for internal wafer buffers and internal state-dependent setups. These features play key roles in transient behavior. Hence, it is necessary to efficiently expose the inner workings of these tools. In this paper, we show the following. • A class of state dependent failures caused by setups can be readily incorporated into the flow line model (Corollary 2). • The computation required to simulate a flow line with such setups and batch arrivals can be significantly reduced (Corollaries 3, 4 and Theorem 7). For parameters typical of a real clustered photolithography tool, our approach requires about 50 times fewer computations than otherwise possible. Further, in a comparison between a flow line model and data from a clustered photolithography tool in production, the throughput and cycle time predictions were accurate to within 0.5% and 3%, respectively. The models are thus promising candidates to improve the fidelity of key tool groups in fab-wide simulation models without too much additional computational complexity. A flow line model has strengths and limitations. A few caveats are mentioned next. They do not include a customer transport resource such as the wafer transport robot in cluster tools. Note that modeling this resource is essential when one’s purpose is to control the robot movement, as in [20]. However, as the application of interest to us is fab-level simulation, such details are far beyond the scope of the model and would impose intractable computational demands. Another limitation of the flow line model we consider is that it does not allow for server breakdown. In fact, including server breakdowns, except as described in the sequel, prevents the neat decomposition of the flow line into channels. Much work has been done to study this case, however the results are almost always directed to mean throughput or performance bounds (cf. [4]). Detailed wafer advancement must be described by the elementary evolution equations. Also, as in [5], we will assume the system initially empty. This is a common practice in the simulation of large systems. As each tool in such simulations repeatedly and with frequency returns to an empty state, this assumption is not too restrictive. However, the model is a poor candidate for use in developing controls for wafer transport robots; such controls must be robust to variation in initial conditions. Control is not our objective.
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Fig. 1. A flow line with
M servers and intermediate buffers.
Ultimately, since the model has demonstrated a fidelity of 0.5% error in practical throughput prediction, we consider it sufficient. In fact, 5% accuracy often suffices for practical simulation studies. A practical limitation is that we do not allow the service times to depend upon the customer; this is addressed in subsequent work, see [21]. Note that some of the results of this paper first appeared in [22] in abbreviated form and without proof. This paper is organized as follows. Section II provides the system description and existing results. The decomposition of a flow line into channels and the channel properties are considered in Section III. Section IV develops features required for the application to semiconductor manufacturing. A realistic and practical example of the results is discussed Section V. Concluding remarks are presented in Section VI. Throughout, we relegate all proofs to the Appendix . II. DETERMINISTIC FLOW LINES We next describe the flow line model of interest and review relevant results from the literature. No new results are developed in this section. A flow line, as in [1]–[5], consists of a series of servers, , at which customers receive service. Each server may be preceded by a buffer of capacity at which cusif there is no such buffer. Let tomers await service. Set denote the internal buffer capacity. We assume . The that there is a buffer of infinite capacity prior to server is deterministic. Cusservice time of a customer at server tomers require service from each server in order. Let denote the index of the bottleneck server, that is, the server for which and for all other servers with . The servers are reliable and do not fail. Fig. 1 depicts such a system. customer, . Let denote the arrival time of the The interarrival times have arbitrary distributions. We allow , . Without batch arrivals. Assume that loss of generality, customers are served in the order in which they arrive. Arrivals queue in the infinite capacity buffer until . At that time, all preceding customers have vacated server . Once the customer immediately begins service with server , it begins service customer receives service from server either immediately or when customer with server exits server , whichever time is greater. If the next server is ’s buffer if not available, customer will proceed to server space is available. Otherwise, the customer languishes inside . When server subsequently exits a customer, server all customers that next require server ’s attention advance one position in the buffer, or if there is no buffer, immediately enter the server. Using the terminology of [1], the system is an
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asynchronous flow line with deterministic service times, reliable servers, discrete customers and manufacturing blocking. We call it a deterministic flow line. The customer exit time depends only on the total service time and the exit time of the previous customer [5]. From this perspective, it is equivalent to consider the buffers as servers with zero process times. What about from the perspective of the internal advancement of customers? Here too, if we consider a buffer as a zero process time server, the internal behavior is preserved. If no queueing is required in a buffer slot, the customer will pass immediately through that slot and spend exactly zero time there. Queueing will only occur in a buffer slot when there is no room to advance further. For a deterministic flow line, there is no need to distinguish between buffers and servers. denote the total number of locations for Let customers inside the system including both buffers and servers. Hereafter, we consider each such location as a server. Let denote these servers. Use as before for a true for the buffers. server and set To be definite, assume that all processes are right-continuous denote the start time of customer in with left-limits. Let . The progression of customers through the flow line server is dictated by the elementary evolution equations
(1) , , and initial conditions , for for . Let denote the completion time of . Time spent customer from server , that is, is not included in . queueing for the subsequent server These equations enforce the asynchronous nature of the line. Customers advance as soon as they are able to the next server. In the sequel, we refer to the servers as modules. This is the common terminology for processing chambers within clustered photolithography tools. The following lemma is proved or assumed in [5] and [6]. Lemma 1: No contention after the bottleneck. After the bottleneck
and . Lemma 1 is used for the proof of Theorem 1, which is a key result of [5]. It states that either an arriving customer faces no time units after the precontention for any server or it exits ceding customer. Theorem 1: A recursion for completion times. Let denote . For an the sum of the service times, that is, initially empty system
for and initial condition . The completion time is independent of the order of the modules or their individual service times. These results are extended to batch arrivals and for the requirement that all pre-bottleneck
modules be empty before the next customer begins service in [8] and [9]. Since there is no contention after the bottleneck, from Theorem 1. Theorem 2 is one can immediately infer also a key result of [5] and extends to batch arrivals [8], [9]. Theorem 2: Total delay in a flow line. The total time a cus, in a tomer spends queueing, deterministic flow line is identical to the queue time they would experience in a single-server queue with deterministic process time . To our knowledge, this is the extent of exact analytical results for such deterministic flow lines (cf., [4, pp. 158]). III. THE EVOLUTION OF DELAY We are poised to begin our study of the delay in each module. This information is critical when the system behavior depends upon the internal state of the flow line. We start with the following definition. Definition 1: Consider a deterministic flow line with the exis a function of the customer . We call such ception that a system a channel if , and 1) 2) . as the bottleneck and also In this case, we refer to module . denote it as A channel is thus a series of modules in which the first is slower than all others except the last. The service time of the last module may vary but is always strictly greater than . If we allow modules after the channel bottleneck, Lemma 1 holds replaced by , so long as their process times do with . The next result corresponds to Theorem not exceed 1 for a channel. Theorem 3: A recursion for channel completion times. Let denote the sum of the service times for customer , that is, . For an initially empty system
for and initial condition . Like all results in this paper, we relegate the proof to the Appendix . If we allow modules after the channel bottleneck , an analowith process times less than or equal to gous version of Theorem 3 holds. The following corollary is easy to prove and provides a recursion for the total delay each customer faces in a channel. It includes both queueing to enter and queueing for all subsequent servers. Corollary 1: Total delay in a channel. Let . For an initially empty system
for , with and . We now state our first main results. They reveal the evolution of delay in a channel. There are two key points. First, if a customer experiences delay inside the channel, the delay in all modules subsequent to the module of initial delay is determined . Second, there is a recursion by the process times of module to calculate the total delay that a customer will face internal to the channel. The total channel delay also characterizes the delays at individual modules.
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Fig. 2. Customer progression through the channel of Example 1. The shaded bars indicate delay for the next server.
A few definitions are of help. Let
TABLE I TOTAL IN-CHANNEL DELAY FOR THE SYSTEM OF EXAMPLE 1
denote the customer delay to enter module and the delay in each module, respectively. The next result is a consequence of the well structured service times in a channel. In general, module failures or customer dependent service times will disrupt this behavior. Theorem 4: Delay structure. Consider an initially empty channel and a customer . If there is a , let denote obey the first module in which delay occurs. The
for and . denote the total delay waiting for For customer , let . service at modules not including queueing to enter module That is, . Let denote the maximum possible delay customer can experience while in modules , . If the channel is completely filled with customers, all customers advance simultaneously every exits a wafer. The maximum possible time the last module is delay that can be experienced by a customer in module . We thus define
We do not include in the sum since no delay is ever incurred in the bottleneck module or thereafter. Finally, let denote . Theorem 5: A recursion for the delay in a channel. For obeys the an initially empty channel, the in-channel delay following recursion for :
(2) (3) The entry and server delays may be obtained as
(4)
for
. The initial conditions are , , , and . One utility of Theorem 5 is that it enables us to recursively without resorting to a full channel simulation. determine Thus, we can determine the total in-channel delay with reduced complexity. An upper bound for the complexity required to simulate a flow line will be discussed in the sequel. The next example highlights the application of Theorem 5. 1) Example 1: Delay evolution in a channel. Consider a channel consisting of four modules with service times
and for . The bottleneck service times change from 20 to 25 to 30 and then repeat this pat, , , tern. Consider customer arrival times , , . Fig. 2 depicts the module occupation on the axis as a function of time on the axis. An empty box with a number inside indicates that customer is residing in the corresponding module for a duration of time equal to the width of the box. Gray boxes indicate that a customer has completed service and is waiting to advance to the . During next module. For example, consider the row labeled module is vacant, during the time interval wafer 1 is receiving processing from module , during the module is vacant, during wafer 2 is receiving prowafer 2 is waiting for module to be cessing, during gives the total deavailable, and so on. The recursion for can then be lays each customer faces in the channel and deduced. and . The delay customer faces Table I provides , and in each module can be obtained using only . We now turn to the decomposition of deterministic flow lines. in a determinDefinition 2: If the service time of module istic flow line is such that , we call a domis the first dominating module and inating module. Module is the last. Let be the set of module indices of dominating modules.
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Index the dominating modules in order from the start of the line. Let denote the number of dominating modules and use as their index. Let denote the module index of dominating module . 2) Example 2: Dominating modules in a flow line. Consider ) a deterministic flow line consisting of nine modules ( with . The dominating modules are and . Module is the bottleneck. In this case, . Since there are three dominating modules . From the beginning of the flow line, so that , the the first dominating module is module so that and the third is module second is module so that . Hereafter, we consider only flow lines with three or more dominating modules. If there are fewer, the previous discussion is sufficient to characterize delay. That is, if there is only one is the bottleneck and there is no dominating module then delay inside the line. If there are two dominating modules, the system is fully described by the channel theorems since customers never experience delay in modules past the bottleneck. between and inConsider the modules , cluding two neighboring dominating modules and . As is shown in the Appendix , this collection of sequent modules is a channel; call it channel- . The following Corollary of Theorem 3 deals with the start time of wafers in each . such channel. Let Corollary 2: Entry times at dominating modules. For an initially empty system, start times in channel- satisfy
TABLE II DELAY EVOLUTION FOR THE SYSTEM OF EXAMPLE 3
The start times at channel- are given as
for server is
. For
, the delay at a
and for , and . Since each channel behaves as in Theorem 5, concatenating the equations for a flow line’s constituent channels yields Theorem 6. It is stated after a few definitions. Define
for all . represents the maximum total delay that customer can experience in channel- . This defifor a channel nition agrees with the previous definition of when . Let denote the actual delay incurred while in channel- , not accounting for delay in the final module of the channel. That is
Since there is no delay after the bottleneck by Lemma 1, we need only consider the delays incurred in channel- , . Theorem 6: Delays in a deterministic flow line. In an initially empty deterministic flow line, the delays , obey the following recursions for :
The initial conditions are , and , for , for and , and . While the elementary evolution equations require a module by module calculation, the recursion requires only the customer data and the state of each channel. An example follows. 3) Example 3: Delay evolution in a deterministic flow line. Consider the initially empty system of Example 2. We can easily determine the maximum delays possible and , for all . For 12 customers with arrival , , , , , times , , , , , and , Table II depicts the maximum , the experienced channel delays channel delay and and . We do not include , since it is constant for all customers . Fig. 3 depicts the customer residence times in each module for all . The clear portion of the bar is the service time; the shaded portion of the bar is delay. For example, consider the subgraph labeled “Cust 3.” In the first to , the graph shows that customer channel from modules , 35 s in , 60 s in , 60 s in , etc. 3 spends 30 s in . There is no delay in module . From Table II, is the maximum possible value of 36 s The delay in module and 24 s are spent processing. The delay in module is 24 s . and 12 s are spent processing. There is no delay in module
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through Suppose that all wafers must vacate modules prior to the commencement of a setup. Let denote the wafer dependent setup duration. For wafers requiring and . Further, let no setup, we set denote the time instant at which wafer vacates module . We consider two policies controlling the start time of a setup. If the setup for wafer must wait for both wafer to vacate and for wafer to arrive, define the adjusted entry module On the time of wafer as other hand, if the setup need not await the arrival of customer , then define . Let denote the index of the successive bottleneck prior to , that . With these definitions, is, the next result follows immediately. Corollary 3: Delay with state dependent setups. Theorem replaced by and 5 holds with
Fig. 3. Residency times of customers in the system of Example 3.
The total delays in this channel from modules to sum to . For the first five customers, the residency times are increasing to 90 starting from the end of the line. Similarly, the residency times in channel-1 are increasing to 60 starting from the end of the channel, until channel-2 fills (at which point residency times in channel-1 begin to increase toward 90 from the end of the channel). Similar behavior is exhibited for customers 6 through 12. IV. PRACTICAL FEATURES In addition to elucidating the evolution of delay, the results can be extended for practical purposes. Three topics are discussed in this section: state dependent setups, batch arrivals and computational complexity. As is common in semiconductor fabs, we hereafter refer to customers as wafers.
We next seek to reduce computation. Since is typically in the last channel prior to the bottleneck, we can narrow our focus. Corollary 4 summarizes the result. We suppress dependence upon wafer in because there is no delay incurred . in the bottleneck module. Recall that Corollary 4: Delay in the last channel. The total delay in is given as channel-
for , where we use individual module delays obey
. The
Here A. A Class of State Dependent Failures: Setups Cluster tools may require a setup when changing from one class of wafer to another. A setup prepares the process modules for the new wafers by adjusting the module temperature or chemical characteristics. For process integrity, the tool cannot be occupied during a setup. Thus, setup initiation must wait until all wafers have vacated the tool. Interconnected cluster tools (cf., [23]) consist of several distinct tools which pass wafers to each other. A setup in one cluster of the interconnection may not begin until that cluster is vacant. In clustered photolithography tools, all modules from the first to the last of the pre-scan track must be vacated prior to setup initiation. Once the setup has been conducted, wafers may once again . We will incorporate this behavior into our enter module model. Since the setup cannot begin until the flow line reaches a certain state, we are modeling a state dependent failure mode.
The vacation times from server
may be obtained as
The initial conditions for the recursion are , , and . . This is acceptThe caveat is that we lose visibility to able if there is only a single tool. When simulating a system consisting of two or more clustered photolithography tools, the
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start time of service is useful information. Without it we sacrifice visibility to the wafers in queue. Setups can be modeled as in Corollary 3.
TABLE III NUMBER OF OPERATIONS REQUIRED FOR THE INITIALIZATION
B. Batch Arrivals: Wafer Lots In semiconductor fabs, identical wafers are grouped into batches termed lots. Lots consist of up to 25 wafers. Since wafers within a lot do not prompt a setup, we can develop a delay recursion for lots instead of wafers. We focus on the last channel as our goal is to further reduce the computational complexity. Since wafers in a lot arrive simultaneously, we slightly abuse be the arrival time of lot . Let denotation and let note the index of the th wafer of lot . For example, if lots 1 and 2 each consist of 25 wafers, the seventh wafer of lot 3 is . The start and the 57th wafer to arrive and thus completion times at module for wafer are denoted, and , as before. Similarly, respectively, as . Finally, let denote the number of wafers in lot . As before, is not a function of the wafer. Corollary 5: Delay recursion in the last channel for lots. The aggregate delay obeys the following relations :
for . The module delays for obey the same behavior as in Corollary 4. Above, , so that
The function denotes the sum of the delays experienced by . It has the value wafers of lot in module
where is the index of the first wafer in lot to experience delay , or otherwise. It has the value shown in module in the equation at the bottom of the page. The initial conditions , for the recursion are , and . As in the previous subsection, each arriving lot may require a setup. These can be analogously incorporated as in Corollary 3 by replacing with and calculating . C. Computational Complexity Aside from harvesting additional insight into the dynamics of a deterministic flow line, the approach allows for significant computational reduction. For simplicity, we suppose that the number of wafers per lot is constant . Recall that denotes the bottleneck module and there are modules and successive bottlenecks with . Here, we quantify the improvement in computation from the channel decomposition under the following assumption. Assumption A1: Our simulation goal is to characterize the dynamics in the modules between the penultimate dominating and the bottleneck . If we use the approach module of , . • Equation (1), we must calculate . • Theorem 6 or its corollaries, we must calculate Assumption A1 allows us to clearly demonstrate the computational complexity differences in the alternate approaches and in the last ensure that setups could be incorporated for channel. We do not, however, address the additional calculations entry times from to . required to shift the module There are a few more computations than reported next for the approach of Theorem 6 and its corollaries since we must then determine the vacation times. Theorem 7: Computational complexity. Under Assumption A1, and with the computation given in Table III for initialization, the number of calculations required in our implementation to simulate the completion of wafers from the bottleneck is given in Table IV. We consider a multiple of . Table IV provides the number of maximum/minimum, addition, and multiplication operations required for the recursions of (1), Theorem 6, Corollary 4 and Corollary 5. There may be a more efficient approach.
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Fig. 4. System of Example 4.
TABLE IV NUMBER OF OPERATIONS REQUIRED FOR THE RECURSIONS
TABLE V OPERATIONS REQUIRED TO INITIALIZE A FLOW LINE MODEL FOR EXAMPLE 4
V. APPLICATION TO SEMICONDUCTOR MANUFACTURING
a post-scan buffer. The process times including robot transfer , are given in the vector time, denoted ,
We consider a flow line model for a clustered photolithography tool. The system is intended to be representative of actual tools. Our goal is to demonstrate the application of the model and the resulting reduction in computational complexity. A clustered photolithography tool consists of pre-scan modules, a photolithography scanner and a collection of post-scan modules. They act as a single tool. The pre-scan operations include the deposition of photosensitive chemicals and anti-reflective coatings, baking and cooling processes. The scanner typically houses a magazine of either 12 or 24 buffer spaces, one alignment module, the scanner module itself where wafers are illuminated with nonvisible light and possibly a post-scan buffer magazine. The post-scan modules develop the image on the wafer via baking, cooling, and related operations. Wafers are moved from one module to the next via wafer transport robots. Note our two key caveats. First, we willfully neglect wafer transport robot issues, assume the system is not robot limited and incorporate the presence of robots only via a lengthening of the process times by travel time. Second, though we allow for setups between lots, all module process times are independent . of the wafer, that is Acknowledging our caveats, a flow line model may serve to model this system. Each pre-scan, scan and post-scan operation may be modeled by a single module with appropriate process time. To incorporate the wafer transport, any time required to transfer the wafer from one module to the next is included in the process time. In real systems, there are generally multiple modules devoted to a single process so that a wafer has multiple paths it may follow. As discussed in [22], if there are say redundant modules devoted to a process which requires units of time, we can readily model this by including modules in . This is not the flow line model each with process time exactly equivalent, however. 4) Example 4: Clustered photolithography scanners. Con, a 12 sider a system with five pre-scan processes wafer pre-scan buffer , one align process , one scan process , and four post-scan processes . We do not include
The scanner process time is . The number of redundant , ensures modules allocated to each process , denoted that the highly expensive scanner is the system bottleneck. The scanner modules cannot be made redundant, so we thus . The set system is depicted in Fig. 4. There are no buffers between processes except just prior to the scanner modules but there is an infinite queue available prior to entering the tool. The pre-scan buffer is not labeled in the diagram, it is the rectangle with 12 sections indicating buffer space for 12 wafers. modThe flow line model for the system consists of , , ules. The process times are , , , for the buffer, , , , , and . The botwith . The three dominating tleneck is module , and . Module is the bottleneck. modules are We ignore the post bottleneck modules as they do not influence the system dynamics. Their sole contribution is to add a fixed constant amount of time for a wafer to exit the system once it clears the bottleneck. We suppose that a setup, when required, may only begin once are vacant. Thus, all modules up to and including module . With these assumptions, Tables V and VI provide the computations required to simulate lots each consisting of 25 wafers, so that there are wafers. Including a small number of initialization calculations, the batch evolution requires dramatically fewer computations than the elementary evolution (1). Though Corollary 5 requires 5 multiplications per lot, there are 37.5 times more additions and 54.5 times more max/min operations in (1). In addition to enabling an orders of magnitude reduction in the computation required for simulation, the model is also very accurate. The flow line model has been tested on a clustered
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TABLE VI NUMBER OF OPERATIONS REQUIRED FOR THE RECURSIONS
photolithography tool in production with similar wafers and was found to provide throughput and cycle time estimates within 0.5% and 3% of actual, respectively. VI. CONCLUDING REMARKS
or , then all terms in the If an equation contains an -alequation should be interpreted in the sense of the gebra. Otherwise, the standard interpretation applies. Often, and understand that whenever we work we suppress the -algebra notation, with an equation containing “multiplication” is interpreted as . Matrix multiplication in -algebra is interpreted analogously to normal the matrix multiplication in that the elements of the matrix are . Let product be the column vector of start times for customer , that is . As is demonstrated in [24, pp. 19], a deterministic flow line can be written as a matrix -algebra as follows: difference equation in the (6)
For deterministic flow line models, we have developed results in two directions. First, we showed that there is an exact decomposition into channels characterized by dominating modules. The decomposition allows us to develop a recursion for the dynamics of customer delay under an arbitrary customer arrival process. The results thus provide insight into the manner in which the line behaves. Second, and of particular relevance to applications, we have employed the decomposition to simulate state dependent setups with almost two orders of magnitude less computation. We demonstrated, via a representative clustered photolithography example, how the wafer flow in such cluster tools may be simulated using a flow line model. In addition, it was mentioned that the models have been tested on a clustered photolithography tool processing similar wafers and provided estimates of throughput and cycle time within 0.5% and 3% accuracy, respectively. There were two caveats: the process times must be constant for all wafers and we suppose that the system is not robot limited. Further work to extend the results is mentioned next and some questions are posed. To serve as an adequate model for cluster tools, the restriction to a single class of wafers with identical process times must be removed. In addition, can we use the recursions as a starting point for the development of closed form analytic expressions for throughput with state dependent setups? Does any of the structure exposed remain in the presence of transport robots? Finally, can the insight into the system behavior be employed to help us obtain, in the words of Altiok ([4, pp. 158]) “the probability distribution of the buffer contents”?
Here, we have suppressed the and understand that multiplication takes precedence over addition. Let and be the identity and elements for and , respectively. That is, . Hence, in normal notation, and . Then, the matrices in (6) are given as follows:
Note that, for example, is to be interpreted as . Proof of Theorem 3: A recursion for channel completion so that it times. By definition, will suffice to show that . We first demonstrate that . From the elementary evolution (1), we , for all and see that . Hence customers
APPENDIX Here, we prove the results stated in the paper. In the proof of -algebra notation Theorem 3, it is helpful to use the [24]. The other proofs use standard notation. -algebra, we use and to denote and In the , respectively. The elementary evolution (1) then becomes
(5) for
and with the same initial conditions.
where the last inequality follows since . This is the first term of the maximization. The second term also follows . by the evolution equations, since To complete the proof, we must show that . Let be the column vector of start times for customer , that is . The system can be written
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as a matrix difference equation in the follows:
237
-algebra as
(7) Unlike in (6), the matrix is a function of customer since is dependent upon . That is
Since we are interested in the completion times from module , we define the row vector and consider . Conducting the matrix multiplication, we obtain
Now, since
, for
, we obtain
This was what it remained to show. Proof of Corollary 1: Total delay in a channel. From Theorem 3, we have that
By adding and subtracting from the right-hand term in the maximization, we obtain the result. Proof of Theorem 4 and 5: Delay in a channel. We prove these results jointly. Note that (4) is equivalent to Theorem 4. follows directly from the definiThe recursion (3) for tion, since . We prove (2) and (4) jointly by induction on the customer index . First, partition the possible cases as follows. Let denote the condition • and ; • denote the condition and ; denote the condition . • so that (2) is equivalent to the Note that following three equations: (8) (9) (10)
The first step of our induction is to demonstrate that (2) and under the initially empty system as(4) hold for customer sumption. This is easy to do since we can use (1) to immediately , for all , so that , calculate . Since , for all , (2) yields , for all and we are done with the initialization step. (4) yields Our induction hypothesis is that (2) and (4) hold for customer . If (and thus ), it is easy to iterate the basic evolution (1) forward to show (2) and (4) for customer (there are two cases that must be considered and ). We thus assume that . In particular, this means that there is a module such that ; • ; • . • From this we have that . We can easily calculate the start times for customer to obtain the following. : ; • For • For : ; • For : . We must now demonstrate that (2) and (4) hold for customer when . We proceed by cases. First, consider case , so that . For customer the module start times may be obtained from (1). : ; • For • For : ; , we • Using the fact that have that for : . ’s. The delays can then be calculated from the ; • • ; • ; . • There are two possibilities, , or not. If , then and . In this case
as we wanted to show. In the case, we have that
, , and again . Equation (4) for
then follows immediately. customer is similar. We omit the details. The argument for case Case is slightly more involved. There are two cases. Either in which customer encounters there is a first module delay or there is none. Note that by this we mean the delay occurs while in a module after the process time has elapsed; this does not necessarily rule out nor imply delay to enter the flow
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line. If there is no such first module, then so that , and . implies that Now, (the last by the basic evolution (1)). This last inequality may be written as , which is equivalent to . This then gives us and and so (2) and (4) hold. when there is a first module in which Now, for the case is delayed. Using the definition of , (1) customer and the condition , we obtain the module start times. : . • For : • For
• Using the fact that have that for
, we : .
We can thus determine the delays. • •
.
• Summing the delays gives . Combining this with the case where there is no yields (10). This concludes the proof. Proof of Corollary 2: Entry times at dominating modules. First note that Theorem 3 holds for a larger class of systems than a channel. In fact, the proof only requires that . Thus, any deterministic flow line that allows its bottleneck process times to vary as a function of and satisfies this condition will obey Theorem 3. In a deter), consider the portion ministic flow line (without variable and of a flow line consisting of the modules let . These modules possess the necessary structure required for Theorem 3 to hold. Recalling , we have the result. that Proof of Theorem 6: A recursion for the delay in a deterministic flow line. Let the arrival time of a customer k to , which each such channel be the entry time to module . Let the channel bottleneck serwe have denoted as plus vice time be given as the service time of module any delay incurred by customer k suffering contention for the , if any. With these definitions downstream module for the channel arrival and bottleneck service times, the mod, , act as a channel; call it ules channel- . This is sufficient to prove Theorem 6. Corollary 3 and 4 are immediate. Proof of Corollary 5: Delay recursion in the last channel follows immediately for lots. The result for
; we will do this moif we can evaluate , mentarily. To show the recursion for note that since the arrival times are identical within a lot the maximization term in the recursion of Corollary 4 for will always yield . Since there are remaining wafers after the first one, we are done. result follows by Corollary 2. The forms for The and are just the definitions. , consider the first wafer of the lot to experience To obtain , call this wafer . If there is no such delay in module . Before wafer there are no dewafer we let for lot , and after wafer lays experienced in module the maximum delay is faced by wafers of lot in module . That is, , and , . This ac. The remaining term counts for the first of the two terms in is the delay experienced by wafer ; this delay readily follows is from the delay evolution of Corollary 4. The wafer index that value satisfying and . The result follows, where we use to ensure the equation for is correct in within the case when delay does not propagate back to lot . Proof of Theorem 7: Computational Complexity. We consider subtraction and addition to be the same in terms of computation. Similarly, multiplication and division. Maximizaare also considered the same. tion, minimization and For (1), to determine the wafer evolution in the last channel, one must evolve the wafers through every preceding module. , one max and For each wafer, there is one max for module , and one max and two adds one add for modules . In total, there are max and adds per wafer. for module No initial calculations are of help. Consider the initialization for Theorem 5. For each , channel- , to facilitate the determination of we first calculate
. From this we can
calculate
with two more adds. In total, this requires additions. We also store the terms. Calculate for all in additions. The adds. initialization requires We turn to the recursion for Theorem 5. and , we can calculate • By storing
This requires 2 adds per for a total of adds. • Assuming that we know the value of all input variables for , calculating for all requires adds max. The input variables needed to calculate and are and . • Since , nothing is required for once we obtain . To obtain requires two adds . Assuming , and one max if we have takes more adds.
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• Given the require • Finally, calculate
terms, the delays and adds and max.
for all in adds. Since the recursion is repeated for each of the wafers, we obtain the values given in Table IV. The computations required for Corollaries 4 and 5 can be determined similarly. ACKNOWLEDGMENT The author is grateful to the anonymous referees for their insightful comments. This paper is much improved for their suggestions. REFERENCES [1] Y. Dallery and S. B. Gershwin, “Manufacturing flow line systems: A review of models and analytical results,” Queueing Syst., vol. 12, pp. 3–94, 1992. [2] H. T. Papadopoulos and C. Heavey, “Queueing theory in manufacturing systems analysis and design: A classification of models for production and transfer lines,” Eur. J. Oper. Res., vol. 92, pp. 1–27, 1996. [3] J. A. Buzacott and J. G. Shanthikumar, Stochastic Models of Manufacturing Systems. Englewood Cliffs, NJ: Prentice-Hall, 1993. [4] T. Altiok, Performance Evaluation of Manufacturing Systems. New York: Springer-Verlag, 1996. [5] B. Avi-Itzhak, “A sequence of service stations with arbitrary input and regular service times,” Manage. Sci., vol. 11, no. 5, pp. 565–571, 1965. [6] H. D. Friedman, “Reduction methods for tandem queuing systems,” Oper. Res., vol. 13, no. 1, pp. 121–131, 1965. [7] J. R. Morrison and M. K. Mutnuri, “On the throughput of clustered photolithography tools: Wafer advancement and intrinsic equipment loss,” in Proc. 3rd Annu. IEEE Conf. Autom. Sci. Eng., Sep. 2007, pp. 88–93. [8] J. R. Morrison, B. S. Bortnick, and D. P. Martin, “Performance evaluation of serial photolithography clusters: Queueing models, throughput and workload sequencing,” in Proc. 2006 IEEE/SEMI Adv. Semicond. Manuf. Conf., Boston, MA, May 2006, pp. 44–49. [9] J. R. Morrison and D. P. Martin, “Performance evaluation of photolithography cluster tools: Queueing and throughput models,” OR Spectrum, vol. 11, no. 4, pp. 375–389, 2007. [10] J. R. Morrison and D. P. Martin, “Practical extensions to approximations for the G/G/m queue with applications,” IEEE Trans. Autom. Sci. Eng., vol. 4, pp. 523–532, 2007.
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[11] F. P. Kelly, “The throughput of a series of buffers,” Adv. Appl. Probability, vol. 14, no. 3, pp. 633–653, 1982. [12] B. Avi-Itzhak and S. Halfin, “Servers in tandem with communication and manufacturing blocking,” J. Appl. Probability, vol. 30, pp. 429–437, 1993. [13] B. Avi-Itzhak, “Servers in tandem with k-stage blocking and communications-type flow,” J. Appl. Probability, vol. 31, pp. 1061–1069, 1994. [14] B. Avi-Itzhak and M. Yadin, “A sequence of servers with arbitrary input and regular service times revisited,” Manage. Sci., vol. 41, no. 6, pp. 1039–1047, 1995. [15] B. Avi-Itzhak and H. Levy, “Buffer requirements and server ordering in a tandem queue with correlated service times,” Math. Oper. Res., vol. 26, no. 2, pp. 358–374, 2001. [16] J. M. Kim and B. Avi-Itzhak, “Ordering of tandem constant-service stations to minimize in-process stock cost,” Rutcor Research Rep., RRR32-93, 1993. [17] J. R. Perkins and P. R. Kumar, “Optimal control of pull manufacturing systems,” IEEE Trans. Autom. Control, vol. 40, pp. 2040–2051, 1995. [18] D. P. Martin, “Capacity and cycle time-throughput understanding system (CAC-TUS): An analysis tool to determine the components of capacity and cycle time in a semiconductor manufacturing line,” in Proc. 1999 IEEE/SEMI Adv. Semicond. Manuf. Conf. Workshop, Sep. 1999, pp. 127–131. [19] D. Pillai, “The future of semiconductor manufacturing: Factory integration breakthrough opportunities,” IEEE Robot. Autom. Mag., vol. 13, no. 4, pp. 16–24, Dec. 2008. [20] M. W. Dawande, H. N. Geismar, S. P. Sethi, and C. Sriskandarajah, Throughput Optimization in Robotic Cells, ser. Springer International Series in Operations Research and Management Science. New York: Springer, 2007. [21] J. R. Morrison, “Regular flow line models for semiconductor cluster tools: A case of lot dependent process times,” in Proc. 5th IEEE Conf. Autom. Sci. Eng., Aug. 2009, pp. 561–566. [22] J. R. Morrison, “Flow lines with regular service times: Evolution of delay, state dependent failures and semiconductor wafer fabrication,” in Proc. 4th IEEE Conf. Autom. Sci. Eng., Aug. 2008, pp. 247–252. [23] S. Ding, J. Yi, and M. T. Zhang, “Multicluster tools scheduling: An integrated event graph and network model approach,” IEEE Trans. Semicond. Manuf., vol. 19, pp. 339–351, 2006. [24] F. Baccelli, G. Cohen, G. J. Olsder, and J. P. Quadrat, Synchronization and Linearity. New York: Wiley, 1992. James R. Morrison (S’97–M’00) received B.S. degrees in electrical engineering and in mathematics from the University of Maryland, College Park, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Illinois at Urbana–Champaign, Urbana, in 1997 and 2000, respectively. He was with the Fab Operations Engineering Department at the IBM Corporation from 2000 to 2005. He is currently an Assistant Professor in the Department of Industrial and Systems Engineering, KAIST, South Korea. In September 2008, he became a Co-Chair of the IEEE Robotics and Automation Society Technical Committee on Semiconductor Manufacturing Automation. His research interests include semiconductor wafer fabrication, system design, queueing networks, and stochastic control.
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Deterministic Flow Lines With Applications James R. Morrison, Member, IEEE
Abstract—We demonstrate that flow line models with deterministic service times and an arbitrary arrival process may be exactly decomposed into segments that each exhibit similar behavior. We call the segments channels and demonstrate that this decomposition leads to a recursion for the delay experienced by customers within the system. The consequence, in addition to clearly elucidating the manner in which customers advance, is that the state of a flow line at any time can be completely characterized by a handful of parameters per channel. The recursions and channel decomposition allow us to model a class of state dependent failures that are common in certain cluster tools in semiconductor wafer manufacturing. Using the fact that wafers are typically grouped into batches, we are able to reduce the computation required to simulate the wafer advancement by about 50 times. The models have been tested with data from a clustered photolithography tool in production and provide throughput and process time predictions within 0.5% and 3% of the actual performance, respectively. Note to Practitioners—Flow line models can be used to model assembly lines, tandem manufacturing systems, and robotic work cells such as cluster tools. In semiconductor wafer fabrication, generic cluster tools have become increasingly important and the class of clustered photolithography tools are essential to production. We develop deterministic flow line models allowing for setups that depend on the location of wafers within a tool. A reduction in computational complexity is achieved by noting that wafers are often grouped into wafer lots. Tests of the models against actual production data for clustered photolithography tools have shown that the reduction in computation required to simulate production with setups is on the order of 50 times, while still achieving a throughput and cycle time accuracy of 0.5% and 3%, respectively. Thus, for important classes of tools, the models are good candidates for use in simulation and to determine a tool’s intrinsic equipment loss (that is, the throughput loss caused by setups, tool structure, and tool failures). Index Terms—Discrete-event simulation, flow line, photolithography cluster tools, semiconductor manufacturing automation.
I. INTRODUCTION ITH an eye toward application to the performance analysis of cluster tools in semiconductor wafer fabrication, we study flow lines with deterministic service times. Flow lines are also called assembly lines or tandem queues and have been studied for many years. There exists a rich and diverse body of work addressing their performance and design. For general
W
Manuscript received December 18, 2008; revised April 29, 2009. First published October 13, 2009; current version published April 07, 2010. This paper was recommended for publication by Associate Editor Q. Zhao and Editor M. Zhou upon evaluation of the reviewers’ comments. The author is with the Department of Industrial and Systems Engineering and the KAIST Institute for the Design of Complex Systems, KAIST, Daejeon 305-701, Korea (e-mail: [email protected]). Digital Object Identifier 10.1109/TASE.2009.2027222
overviews of flow line models, one may consider survey papers such as [1] and [2] or texts such as [3] and [4]. Early key results on flow lines with deterministic service times and reliable servers date back to 1965 [5], [6]. In [5], it is shown that the total queue time of a customer is independent of the order of servers, a buffer can be modeled as a server with zero process time and the mean queue time is the same as in a G/D/1 queue. Extensions for batch arrivals and practical complications are discussed in [7]–[10]. Further investigations on maximum throughput with probabilistic service times, different kinds of blocking for server attention, server ordering and buffer levels have been conducted in [11]–[15], to mention a few of the most closely related studies. Since the key results of [5] and [6] in 1965, there has been little additional insight into the behavior of deterministic flow lines with reliable servers, a single class of customer and an arbitrary arrival process. It is known that the maximum throughput of such flow lines is equal to the bottleneck server rate. The work of [5] provides a recursion for customer exit times from the system. However, it is not known whether there is additional structure to the advancement of customers within the system. To wit, as stated in the well-known text by Altiok ([4, pp. 158]) “[T]here are no known techniques to obtain measures specific to particular buffers, such as the probability distribution of the buffer contents.” In this paper, we prove the following results. • Within subsets of the servers that we call channels, the customer delay is well structured (Theorem 4). • A recursion for the channel delays exists and requires only a handful of parameters; the delay at each server is implied by the channel delay (Theorem 5). • A flow line is characterized by its constituent channels. That is, the channels serve as an exact structural decomposition (Theorem 6). The channel decomposition is characterized by dominating stations [6], [16], [17], which are defined as those servers whose process times are strictly greater than all preceding servers. To determine the state of a customer within the flow line at a given time without using these structural observations, one must resort to the elementary evolution equations and calculate the entry times, service completion times, and queueing at each server. Our application area of interest is semiconductor wafer manufacturing and we will show that, in addition to elucidating the manner in which customers traverse the system, there is utility to the insight gleaned. It is common for semiconductor wafer fabricators, referred to as fabs hereafter, to employ fab-wide simulation models of production to predict system throughput and cycle time. These models simulate the progress of wafer lots through hundreds of tool groups and are used to assess the consequence of changes to production control policies, product mix, tool capacity, etc. Invariably, each of the many tool group
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models specifies parameters such as throughput rate, first wafer delay, setup time, maximum batch size, uptime duration and downtime duration, among others. For many tools, these parameters are sufficient for reliable cycle time and throughput predictions. This is particularly true when there are few interruptions to production and few product changeovers. However, as discussed in [18] and later [8] and [9], disturbances to production can be quite common and have dramatic consequences. Further, with the impending proliferation of small lot sizes and diversity of product mix brought about by the anticipated development of 450 mm wafer fabs, setups and internal buffers will have a greater role to play in system behavior [19]. Loosely speaking, the tools will most often be operating in a transient mode. For cluster tools, in particular clustered photolithography tools, the typical simulation parameters do not account for internal wafer buffers and internal state-dependent setups. These features play key roles in transient behavior. Hence, it is necessary to efficiently expose the inner workings of these tools. In this paper, we show the following. • A class of state dependent failures caused by setups can be readily incorporated into the flow line model (Corollary 2). • The computation required to simulate a flow line with such setups and batch arrivals can be significantly reduced (Corollaries 3, 4 and Theorem 7). For parameters typical of a real clustered photolithography tool, our approach requires about 50 times fewer computations than otherwise possible. Further, in a comparison between a flow line model and data from a clustered photolithography tool in production, the throughput and cycle time predictions were accurate to within 0.5% and 3%, respectively. The models are thus promising candidates to improve the fidelity of key tool groups in fab-wide simulation models without too much additional computational complexity. A flow line model has strengths and limitations. A few caveats are mentioned next. They do not include a customer transport resource such as the wafer transport robot in cluster tools. Note that modeling this resource is essential when one’s purpose is to control the robot movement, as in [20]. However, as the application of interest to us is fab-level simulation, such details are far beyond the scope of the model and would impose intractable computational demands. Another limitation of the flow line model we consider is that it does not allow for server breakdown. In fact, including server breakdowns, except as described in the sequel, prevents the neat decomposition of the flow line into channels. Much work has been done to study this case, however the results are almost always directed to mean throughput or performance bounds (cf. [4]). Detailed wafer advancement must be described by the elementary evolution equations. Also, as in [5], we will assume the system initially empty. This is a common practice in the simulation of large systems. As each tool in such simulations repeatedly and with frequency returns to an empty state, this assumption is not too restrictive. However, the model is a poor candidate for use in developing controls for wafer transport robots; such controls must be robust to variation in initial conditions. Control is not our objective.
229
Fig. 1. A flow line with
M servers and intermediate buffers.
Ultimately, since the model has demonstrated a fidelity of 0.5% error in practical throughput prediction, we consider it sufficient. In fact, 5% accuracy often suffices for practical simulation studies. A practical limitation is that we do not allow the service times to depend upon the customer; this is addressed in subsequent work, see [21]. Note that some of the results of this paper first appeared in [22] in abbreviated form and without proof. This paper is organized as follows. Section II provides the system description and existing results. The decomposition of a flow line into channels and the channel properties are considered in Section III. Section IV develops features required for the application to semiconductor manufacturing. A realistic and practical example of the results is discussed Section V. Concluding remarks are presented in Section VI. Throughout, we relegate all proofs to the Appendix . II. DETERMINISTIC FLOW LINES We next describe the flow line model of interest and review relevant results from the literature. No new results are developed in this section. A flow line, as in [1]–[5], consists of a series of servers, , at which customers receive service. Each server may be preceded by a buffer of capacity at which cusif there is no such buffer. Let tomers await service. Set denote the internal buffer capacity. We assume . The that there is a buffer of infinite capacity prior to server is deterministic. Cusservice time of a customer at server tomers require service from each server in order. Let denote the index of the bottleneck server, that is, the server for which and for all other servers with . The servers are reliable and do not fail. Fig. 1 depicts such a system. customer, . Let denote the arrival time of the The interarrival times have arbitrary distributions. We allow , . Without batch arrivals. Assume that loss of generality, customers are served in the order in which they arrive. Arrivals queue in the infinite capacity buffer until . At that time, all preceding customers have vacated server . Once the customer immediately begins service with server , it begins service customer receives service from server either immediately or when customer with server exits server , whichever time is greater. If the next server is ’s buffer if not available, customer will proceed to server space is available. Otherwise, the customer languishes inside . When server subsequently exits a customer, server all customers that next require server ’s attention advance one position in the buffer, or if there is no buffer, immediately enter the server. Using the terminology of [1], the system is an
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asynchronous flow line with deterministic service times, reliable servers, discrete customers and manufacturing blocking. We call it a deterministic flow line. The customer exit time depends only on the total service time and the exit time of the previous customer [5]. From this perspective, it is equivalent to consider the buffers as servers with zero process times. What about from the perspective of the internal advancement of customers? Here too, if we consider a buffer as a zero process time server, the internal behavior is preserved. If no queueing is required in a buffer slot, the customer will pass immediately through that slot and spend exactly zero time there. Queueing will only occur in a buffer slot when there is no room to advance further. For a deterministic flow line, there is no need to distinguish between buffers and servers. denote the total number of locations for Let customers inside the system including both buffers and servers. Hereafter, we consider each such location as a server. Let denote these servers. Use as before for a true for the buffers. server and set To be definite, assume that all processes are right-continuous denote the start time of customer in with left-limits. Let . The progression of customers through the flow line server is dictated by the elementary evolution equations
(1) , , and initial conditions , for for . Let denote the completion time of . Time spent customer from server , that is, is not included in . queueing for the subsequent server These equations enforce the asynchronous nature of the line. Customers advance as soon as they are able to the next server. In the sequel, we refer to the servers as modules. This is the common terminology for processing chambers within clustered photolithography tools. The following lemma is proved or assumed in [5] and [6]. Lemma 1: No contention after the bottleneck. After the bottleneck
and . Lemma 1 is used for the proof of Theorem 1, which is a key result of [5]. It states that either an arriving customer faces no time units after the precontention for any server or it exits ceding customer. Theorem 1: A recursion for completion times. Let denote . For an the sum of the service times, that is, initially empty system
for and initial condition . The completion time is independent of the order of the modules or their individual service times. These results are extended to batch arrivals and for the requirement that all pre-bottleneck
modules be empty before the next customer begins service in [8] and [9]. Since there is no contention after the bottleneck, from Theorem 1. Theorem 2 is one can immediately infer also a key result of [5] and extends to batch arrivals [8], [9]. Theorem 2: Total delay in a flow line. The total time a cus, in a tomer spends queueing, deterministic flow line is identical to the queue time they would experience in a single-server queue with deterministic process time . To our knowledge, this is the extent of exact analytical results for such deterministic flow lines (cf., [4, pp. 158]). III. THE EVOLUTION OF DELAY We are poised to begin our study of the delay in each module. This information is critical when the system behavior depends upon the internal state of the flow line. We start with the following definition. Definition 1: Consider a deterministic flow line with the exis a function of the customer . We call such ception that a system a channel if , and 1) 2) . as the bottleneck and also In this case, we refer to module . denote it as A channel is thus a series of modules in which the first is slower than all others except the last. The service time of the last module may vary but is always strictly greater than . If we allow modules after the channel bottleneck, Lemma 1 holds replaced by , so long as their process times do with . The next result corresponds to Theorem not exceed 1 for a channel. Theorem 3: A recursion for channel completion times. Let denote the sum of the service times for customer , that is, . For an initially empty system
for and initial condition . Like all results in this paper, we relegate the proof to the Appendix . If we allow modules after the channel bottleneck , an analowith process times less than or equal to gous version of Theorem 3 holds. The following corollary is easy to prove and provides a recursion for the total delay each customer faces in a channel. It includes both queueing to enter and queueing for all subsequent servers. Corollary 1: Total delay in a channel. Let . For an initially empty system
for , with and . We now state our first main results. They reveal the evolution of delay in a channel. There are two key points. First, if a customer experiences delay inside the channel, the delay in all modules subsequent to the module of initial delay is determined . Second, there is a recursion by the process times of module to calculate the total delay that a customer will face internal to the channel. The total channel delay also characterizes the delays at individual modules.
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231
Fig. 2. Customer progression through the channel of Example 1. The shaded bars indicate delay for the next server.
A few definitions are of help. Let
TABLE I TOTAL IN-CHANNEL DELAY FOR THE SYSTEM OF EXAMPLE 1
denote the customer delay to enter module and the delay in each module, respectively. The next result is a consequence of the well structured service times in a channel. In general, module failures or customer dependent service times will disrupt this behavior. Theorem 4: Delay structure. Consider an initially empty channel and a customer . If there is a , let denote obey the first module in which delay occurs. The
for and . denote the total delay waiting for For customer , let . service at modules not including queueing to enter module That is, . Let denote the maximum possible delay customer can experience while in modules , . If the channel is completely filled with customers, all customers advance simultaneously every exits a wafer. The maximum possible time the last module is delay that can be experienced by a customer in module . We thus define
We do not include in the sum since no delay is ever incurred in the bottleneck module or thereafter. Finally, let denote . Theorem 5: A recursion for the delay in a channel. For obeys the an initially empty channel, the in-channel delay following recursion for :
(2) (3) The entry and server delays may be obtained as
(4)
for
. The initial conditions are , , , and . One utility of Theorem 5 is that it enables us to recursively without resorting to a full channel simulation. determine Thus, we can determine the total in-channel delay with reduced complexity. An upper bound for the complexity required to simulate a flow line will be discussed in the sequel. The next example highlights the application of Theorem 5. 1) Example 1: Delay evolution in a channel. Consider a channel consisting of four modules with service times
and for . The bottleneck service times change from 20 to 25 to 30 and then repeat this pat, , , tern. Consider customer arrival times , , . Fig. 2 depicts the module occupation on the axis as a function of time on the axis. An empty box with a number inside indicates that customer is residing in the corresponding module for a duration of time equal to the width of the box. Gray boxes indicate that a customer has completed service and is waiting to advance to the . During next module. For example, consider the row labeled module is vacant, during the time interval wafer 1 is receiving processing from module , during the module is vacant, during wafer 2 is receiving prowafer 2 is waiting for module to be cessing, during gives the total deavailable, and so on. The recursion for can then be lays each customer faces in the channel and deduced. and . The delay customer faces Table I provides , and in each module can be obtained using only . We now turn to the decomposition of deterministic flow lines. in a determinDefinition 2: If the service time of module istic flow line is such that , we call a domis the first dominating module and inating module. Module is the last. Let be the set of module indices of dominating modules.
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Index the dominating modules in order from the start of the line. Let denote the number of dominating modules and use as their index. Let denote the module index of dominating module . 2) Example 2: Dominating modules in a flow line. Consider ) a deterministic flow line consisting of nine modules ( with . The dominating modules are and . Module is the bottleneck. In this case, . Since there are three dominating modules . From the beginning of the flow line, so that , the the first dominating module is module so that and the third is module second is module so that . Hereafter, we consider only flow lines with three or more dominating modules. If there are fewer, the previous discussion is sufficient to characterize delay. That is, if there is only one is the bottleneck and there is no dominating module then delay inside the line. If there are two dominating modules, the system is fully described by the channel theorems since customers never experience delay in modules past the bottleneck. between and inConsider the modules , cluding two neighboring dominating modules and . As is shown in the Appendix , this collection of sequent modules is a channel; call it channel- . The following Corollary of Theorem 3 deals with the start time of wafers in each . such channel. Let Corollary 2: Entry times at dominating modules. For an initially empty system, start times in channel- satisfy
TABLE II DELAY EVOLUTION FOR THE SYSTEM OF EXAMPLE 3
The start times at channel- are given as
for server is
. For
, the delay at a
and for , and . Since each channel behaves as in Theorem 5, concatenating the equations for a flow line’s constituent channels yields Theorem 6. It is stated after a few definitions. Define
for all . represents the maximum total delay that customer can experience in channel- . This defifor a channel nition agrees with the previous definition of when . Let denote the actual delay incurred while in channel- , not accounting for delay in the final module of the channel. That is
Since there is no delay after the bottleneck by Lemma 1, we need only consider the delays incurred in channel- , . Theorem 6: Delays in a deterministic flow line. In an initially empty deterministic flow line, the delays , obey the following recursions for :
The initial conditions are , and , for , for and , and . While the elementary evolution equations require a module by module calculation, the recursion requires only the customer data and the state of each channel. An example follows. 3) Example 3: Delay evolution in a deterministic flow line. Consider the initially empty system of Example 2. We can easily determine the maximum delays possible and , for all . For 12 customers with arrival , , , , , times , , , , , and , Table II depicts the maximum , the experienced channel delays channel delay and and . We do not include , since it is constant for all customers . Fig. 3 depicts the customer residence times in each module for all . The clear portion of the bar is the service time; the shaded portion of the bar is delay. For example, consider the subgraph labeled “Cust 3.” In the first to , the graph shows that customer channel from modules , 35 s in , 60 s in , 60 s in , etc. 3 spends 30 s in . There is no delay in module . From Table II, is the maximum possible value of 36 s The delay in module and 24 s are spent processing. The delay in module is 24 s . and 12 s are spent processing. There is no delay in module
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through Suppose that all wafers must vacate modules prior to the commencement of a setup. Let denote the wafer dependent setup duration. For wafers requiring and . Further, let no setup, we set denote the time instant at which wafer vacates module . We consider two policies controlling the start time of a setup. If the setup for wafer must wait for both wafer to vacate and for wafer to arrive, define the adjusted entry module On the time of wafer as other hand, if the setup need not await the arrival of customer , then define . Let denote the index of the successive bottleneck prior to , that . With these definitions, is, the next result follows immediately. Corollary 3: Delay with state dependent setups. Theorem replaced by and 5 holds with
Fig. 3. Residency times of customers in the system of Example 3.
The total delays in this channel from modules to sum to . For the first five customers, the residency times are increasing to 90 starting from the end of the line. Similarly, the residency times in channel-1 are increasing to 60 starting from the end of the channel, until channel-2 fills (at which point residency times in channel-1 begin to increase toward 90 from the end of the channel). Similar behavior is exhibited for customers 6 through 12. IV. PRACTICAL FEATURES In addition to elucidating the evolution of delay, the results can be extended for practical purposes. Three topics are discussed in this section: state dependent setups, batch arrivals and computational complexity. As is common in semiconductor fabs, we hereafter refer to customers as wafers.
We next seek to reduce computation. Since is typically in the last channel prior to the bottleneck, we can narrow our focus. Corollary 4 summarizes the result. We suppress dependence upon wafer in because there is no delay incurred . in the bottleneck module. Recall that Corollary 4: Delay in the last channel. The total delay in is given as channel-
for , where we use individual module delays obey
. The
Here A. A Class of State Dependent Failures: Setups Cluster tools may require a setup when changing from one class of wafer to another. A setup prepares the process modules for the new wafers by adjusting the module temperature or chemical characteristics. For process integrity, the tool cannot be occupied during a setup. Thus, setup initiation must wait until all wafers have vacated the tool. Interconnected cluster tools (cf., [23]) consist of several distinct tools which pass wafers to each other. A setup in one cluster of the interconnection may not begin until that cluster is vacant. In clustered photolithography tools, all modules from the first to the last of the pre-scan track must be vacated prior to setup initiation. Once the setup has been conducted, wafers may once again . We will incorporate this behavior into our enter module model. Since the setup cannot begin until the flow line reaches a certain state, we are modeling a state dependent failure mode.
The vacation times from server
may be obtained as
The initial conditions for the recursion are , , and . . This is acceptThe caveat is that we lose visibility to able if there is only a single tool. When simulating a system consisting of two or more clustered photolithography tools, the
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start time of service is useful information. Without it we sacrifice visibility to the wafers in queue. Setups can be modeled as in Corollary 3.
TABLE III NUMBER OF OPERATIONS REQUIRED FOR THE INITIALIZATION
B. Batch Arrivals: Wafer Lots In semiconductor fabs, identical wafers are grouped into batches termed lots. Lots consist of up to 25 wafers. Since wafers within a lot do not prompt a setup, we can develop a delay recursion for lots instead of wafers. We focus on the last channel as our goal is to further reduce the computational complexity. Since wafers in a lot arrive simultaneously, we slightly abuse be the arrival time of lot . Let denotation and let note the index of the th wafer of lot . For example, if lots 1 and 2 each consist of 25 wafers, the seventh wafer of lot 3 is . The start and the 57th wafer to arrive and thus completion times at module for wafer are denoted, and , as before. Similarly, respectively, as . Finally, let denote the number of wafers in lot . As before, is not a function of the wafer. Corollary 5: Delay recursion in the last channel for lots. The aggregate delay obeys the following relations :
for . The module delays for obey the same behavior as in Corollary 4. Above, , so that
The function denotes the sum of the delays experienced by . It has the value wafers of lot in module
where is the index of the first wafer in lot to experience delay , or otherwise. It has the value shown in module in the equation at the bottom of the page. The initial conditions , for the recursion are , and . As in the previous subsection, each arriving lot may require a setup. These can be analogously incorporated as in Corollary 3 by replacing with and calculating . C. Computational Complexity Aside from harvesting additional insight into the dynamics of a deterministic flow line, the approach allows for significant computational reduction. For simplicity, we suppose that the number of wafers per lot is constant . Recall that denotes the bottleneck module and there are modules and successive bottlenecks with . Here, we quantify the improvement in computation from the channel decomposition under the following assumption. Assumption A1: Our simulation goal is to characterize the dynamics in the modules between the penultimate dominating and the bottleneck . If we use the approach module of , . • Equation (1), we must calculate . • Theorem 6 or its corollaries, we must calculate Assumption A1 allows us to clearly demonstrate the computational complexity differences in the alternate approaches and in the last ensure that setups could be incorporated for channel. We do not, however, address the additional calculations entry times from to . required to shift the module There are a few more computations than reported next for the approach of Theorem 6 and its corollaries since we must then determine the vacation times. Theorem 7: Computational complexity. Under Assumption A1, and with the computation given in Table III for initialization, the number of calculations required in our implementation to simulate the completion of wafers from the bottleneck is given in Table IV. We consider a multiple of . Table IV provides the number of maximum/minimum, addition, and multiplication operations required for the recursions of (1), Theorem 6, Corollary 4 and Corollary 5. There may be a more efficient approach.
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Fig. 4. System of Example 4.
TABLE IV NUMBER OF OPERATIONS REQUIRED FOR THE RECURSIONS
TABLE V OPERATIONS REQUIRED TO INITIALIZE A FLOW LINE MODEL FOR EXAMPLE 4
V. APPLICATION TO SEMICONDUCTOR MANUFACTURING
a post-scan buffer. The process times including robot transfer , are given in the vector time, denoted ,
We consider a flow line model for a clustered photolithography tool. The system is intended to be representative of actual tools. Our goal is to demonstrate the application of the model and the resulting reduction in computational complexity. A clustered photolithography tool consists of pre-scan modules, a photolithography scanner and a collection of post-scan modules. They act as a single tool. The pre-scan operations include the deposition of photosensitive chemicals and anti-reflective coatings, baking and cooling processes. The scanner typically houses a magazine of either 12 or 24 buffer spaces, one alignment module, the scanner module itself where wafers are illuminated with nonvisible light and possibly a post-scan buffer magazine. The post-scan modules develop the image on the wafer via baking, cooling, and related operations. Wafers are moved from one module to the next via wafer transport robots. Note our two key caveats. First, we willfully neglect wafer transport robot issues, assume the system is not robot limited and incorporate the presence of robots only via a lengthening of the process times by travel time. Second, though we allow for setups between lots, all module process times are independent . of the wafer, that is Acknowledging our caveats, a flow line model may serve to model this system. Each pre-scan, scan and post-scan operation may be modeled by a single module with appropriate process time. To incorporate the wafer transport, any time required to transfer the wafer from one module to the next is included in the process time. In real systems, there are generally multiple modules devoted to a single process so that a wafer has multiple paths it may follow. As discussed in [22], if there are say redundant modules devoted to a process which requires units of time, we can readily model this by including modules in . This is not the flow line model each with process time exactly equivalent, however. 4) Example 4: Clustered photolithography scanners. Con, a 12 sider a system with five pre-scan processes wafer pre-scan buffer , one align process , one scan process , and four post-scan processes . We do not include
The scanner process time is . The number of redundant , ensures modules allocated to each process , denoted that the highly expensive scanner is the system bottleneck. The scanner modules cannot be made redundant, so we thus . The set system is depicted in Fig. 4. There are no buffers between processes except just prior to the scanner modules but there is an infinite queue available prior to entering the tool. The pre-scan buffer is not labeled in the diagram, it is the rectangle with 12 sections indicating buffer space for 12 wafers. modThe flow line model for the system consists of , , ules. The process times are , , , for the buffer, , , , , and . The botwith . The three dominating tleneck is module , and . Module is the bottleneck. modules are We ignore the post bottleneck modules as they do not influence the system dynamics. Their sole contribution is to add a fixed constant amount of time for a wafer to exit the system once it clears the bottleneck. We suppose that a setup, when required, may only begin once are vacant. Thus, all modules up to and including module . With these assumptions, Tables V and VI provide the computations required to simulate lots each consisting of 25 wafers, so that there are wafers. Including a small number of initialization calculations, the batch evolution requires dramatically fewer computations than the elementary evolution (1). Though Corollary 5 requires 5 multiplications per lot, there are 37.5 times more additions and 54.5 times more max/min operations in (1). In addition to enabling an orders of magnitude reduction in the computation required for simulation, the model is also very accurate. The flow line model has been tested on a clustered
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TABLE VI NUMBER OF OPERATIONS REQUIRED FOR THE RECURSIONS
photolithography tool in production with similar wafers and was found to provide throughput and cycle time estimates within 0.5% and 3% of actual, respectively. VI. CONCLUDING REMARKS
or , then all terms in the If an equation contains an -alequation should be interpreted in the sense of the gebra. Otherwise, the standard interpretation applies. Often, and understand that whenever we work we suppress the -algebra notation, with an equation containing “multiplication” is interpreted as . Matrix multiplication in -algebra is interpreted analogously to normal the matrix multiplication in that the elements of the matrix are . Let product be the column vector of start times for customer , that is . As is demonstrated in [24, pp. 19], a deterministic flow line can be written as a matrix -algebra as follows: difference equation in the (6)
For deterministic flow line models, we have developed results in two directions. First, we showed that there is an exact decomposition into channels characterized by dominating modules. The decomposition allows us to develop a recursion for the dynamics of customer delay under an arbitrary customer arrival process. The results thus provide insight into the manner in which the line behaves. Second, and of particular relevance to applications, we have employed the decomposition to simulate state dependent setups with almost two orders of magnitude less computation. We demonstrated, via a representative clustered photolithography example, how the wafer flow in such cluster tools may be simulated using a flow line model. In addition, it was mentioned that the models have been tested on a clustered photolithography tool processing similar wafers and provided estimates of throughput and cycle time within 0.5% and 3% accuracy, respectively. There were two caveats: the process times must be constant for all wafers and we suppose that the system is not robot limited. Further work to extend the results is mentioned next and some questions are posed. To serve as an adequate model for cluster tools, the restriction to a single class of wafers with identical process times must be removed. In addition, can we use the recursions as a starting point for the development of closed form analytic expressions for throughput with state dependent setups? Does any of the structure exposed remain in the presence of transport robots? Finally, can the insight into the system behavior be employed to help us obtain, in the words of Altiok ([4, pp. 158]) “the probability distribution of the buffer contents”?
Here, we have suppressed the and understand that multiplication takes precedence over addition. Let and be the identity and elements for and , respectively. That is, . Hence, in normal notation, and . Then, the matrices in (6) are given as follows:
Note that, for example, is to be interpreted as . Proof of Theorem 3: A recursion for channel completion so that it times. By definition, will suffice to show that . We first demonstrate that . From the elementary evolution (1), we , for all and see that . Hence customers
APPENDIX Here, we prove the results stated in the paper. In the proof of -algebra notation Theorem 3, it is helpful to use the [24]. The other proofs use standard notation. -algebra, we use and to denote and In the , respectively. The elementary evolution (1) then becomes
(5) for
and with the same initial conditions.
where the last inequality follows since . This is the first term of the maximization. The second term also follows . by the evolution equations, since To complete the proof, we must show that . Let be the column vector of start times for customer , that is . The system can be written
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as a matrix difference equation in the follows:
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-algebra as
(7) Unlike in (6), the matrix is a function of customer since is dependent upon . That is
Since we are interested in the completion times from module , we define the row vector and consider . Conducting the matrix multiplication, we obtain
Now, since
, for
, we obtain
This was what it remained to show. Proof of Corollary 1: Total delay in a channel. From Theorem 3, we have that
By adding and subtracting from the right-hand term in the maximization, we obtain the result. Proof of Theorem 4 and 5: Delay in a channel. We prove these results jointly. Note that (4) is equivalent to Theorem 4. follows directly from the definiThe recursion (3) for tion, since . We prove (2) and (4) jointly by induction on the customer index . First, partition the possible cases as follows. Let denote the condition • and ; • denote the condition and ; denote the condition . • so that (2) is equivalent to the Note that following three equations: (8) (9) (10)
The first step of our induction is to demonstrate that (2) and under the initially empty system as(4) hold for customer sumption. This is easy to do since we can use (1) to immediately , for all , so that , calculate . Since , for all , (2) yields , for all and we are done with the initialization step. (4) yields Our induction hypothesis is that (2) and (4) hold for customer . If (and thus ), it is easy to iterate the basic evolution (1) forward to show (2) and (4) for customer (there are two cases that must be considered and ). We thus assume that . In particular, this means that there is a module such that ; • ; • . • From this we have that . We can easily calculate the start times for customer to obtain the following. : ; • For • For : ; • For : . We must now demonstrate that (2) and (4) hold for customer when . We proceed by cases. First, consider case , so that . For customer the module start times may be obtained from (1). : ; • For • For : ; , we • Using the fact that have that for : . ’s. The delays can then be calculated from the ; • • ; • ; . • There are two possibilities, , or not. If , then and . In this case
as we wanted to show. In the case, we have that
, , and again . Equation (4) for
then follows immediately. customer is similar. We omit the details. The argument for case Case is slightly more involved. There are two cases. Either in which customer encounters there is a first module delay or there is none. Note that by this we mean the delay occurs while in a module after the process time has elapsed; this does not necessarily rule out nor imply delay to enter the flow
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line. If there is no such first module, then so that , and . implies that Now, (the last by the basic evolution (1)). This last inequality may be written as , which is equivalent to . This then gives us and and so (2) and (4) hold. when there is a first module in which Now, for the case is delayed. Using the definition of , (1) customer and the condition , we obtain the module start times. : . • For : • For
• Using the fact that have that for
, we : .
We can thus determine the delays. • •
.
• Summing the delays gives . Combining this with the case where there is no yields (10). This concludes the proof. Proof of Corollary 2: Entry times at dominating modules. First note that Theorem 3 holds for a larger class of systems than a channel. In fact, the proof only requires that . Thus, any deterministic flow line that allows its bottleneck process times to vary as a function of and satisfies this condition will obey Theorem 3. In a deter), consider the portion ministic flow line (without variable and of a flow line consisting of the modules let . These modules possess the necessary structure required for Theorem 3 to hold. Recalling , we have the result. that Proof of Theorem 6: A recursion for the delay in a deterministic flow line. Let the arrival time of a customer k to , which each such channel be the entry time to module . Let the channel bottleneck serwe have denoted as plus vice time be given as the service time of module any delay incurred by customer k suffering contention for the , if any. With these definitions downstream module for the channel arrival and bottleneck service times, the mod, , act as a channel; call it ules channel- . This is sufficient to prove Theorem 6. Corollary 3 and 4 are immediate. Proof of Corollary 5: Delay recursion in the last channel follows immediately for lots. The result for
; we will do this moif we can evaluate , mentarily. To show the recursion for note that since the arrival times are identical within a lot the maximization term in the recursion of Corollary 4 for will always yield . Since there are remaining wafers after the first one, we are done. result follows by Corollary 2. The forms for The and are just the definitions. , consider the first wafer of the lot to experience To obtain , call this wafer . If there is no such delay in module . Before wafer there are no dewafer we let for lot , and after wafer lays experienced in module the maximum delay is faced by wafers of lot in module . That is, , and , . This ac. The remaining term counts for the first of the two terms in is the delay experienced by wafer ; this delay readily follows is from the delay evolution of Corollary 4. The wafer index that value satisfying and . The result follows, where we use to ensure the equation for is correct in within the case when delay does not propagate back to lot . Proof of Theorem 7: Computational Complexity. We consider subtraction and addition to be the same in terms of computation. Similarly, multiplication and division. Maximizaare also considered the same. tion, minimization and For (1), to determine the wafer evolution in the last channel, one must evolve the wafers through every preceding module. , one max and For each wafer, there is one max for module , and one max and two adds one add for modules . In total, there are max and adds per wafer. for module No initial calculations are of help. Consider the initialization for Theorem 5. For each , channel- , to facilitate the determination of we first calculate
. From this we can
calculate
with two more adds. In total, this requires additions. We also store the terms. Calculate for all in additions. The adds. initialization requires We turn to the recursion for Theorem 5. and , we can calculate • By storing
This requires 2 adds per for a total of adds. • Assuming that we know the value of all input variables for , calculating for all requires adds max. The input variables needed to calculate and are and . • Since , nothing is required for once we obtain . To obtain requires two adds . Assuming , and one max if we have takes more adds.
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• Given the require • Finally, calculate
terms, the delays and adds and max.
for all in adds. Since the recursion is repeated for each of the wafers, we obtain the values given in Table IV. The computations required for Corollaries 4 and 5 can be determined similarly. ACKNOWLEDGMENT The author is grateful to the anonymous referees for their insightful comments. This paper is much improved for their suggestions. REFERENCES [1] Y. Dallery and S. B. Gershwin, “Manufacturing flow line systems: A review of models and analytical results,” Queueing Syst., vol. 12, pp. 3–94, 1992. [2] H. T. Papadopoulos and C. Heavey, “Queueing theory in manufacturing systems analysis and design: A classification of models for production and transfer lines,” Eur. J. Oper. Res., vol. 92, pp. 1–27, 1996. [3] J. A. Buzacott and J. G. Shanthikumar, Stochastic Models of Manufacturing Systems. Englewood Cliffs, NJ: Prentice-Hall, 1993. [4] T. Altiok, Performance Evaluation of Manufacturing Systems. New York: Springer-Verlag, 1996. [5] B. Avi-Itzhak, “A sequence of service stations with arbitrary input and regular service times,” Manage. Sci., vol. 11, no. 5, pp. 565–571, 1965. [6] H. D. Friedman, “Reduction methods for tandem queuing systems,” Oper. Res., vol. 13, no. 1, pp. 121–131, 1965. [7] J. R. Morrison and M. K. Mutnuri, “On the throughput of clustered photolithography tools: Wafer advancement and intrinsic equipment loss,” in Proc. 3rd Annu. IEEE Conf. Autom. Sci. Eng., Sep. 2007, pp. 88–93. [8] J. R. Morrison, B. S. Bortnick, and D. P. Martin, “Performance evaluation of serial photolithography clusters: Queueing models, throughput and workload sequencing,” in Proc. 2006 IEEE/SEMI Adv. Semicond. Manuf. Conf., Boston, MA, May 2006, pp. 44–49. [9] J. R. Morrison and D. P. Martin, “Performance evaluation of photolithography cluster tools: Queueing and throughput models,” OR Spectrum, vol. 11, no. 4, pp. 375–389, 2007. [10] J. R. Morrison and D. P. Martin, “Practical extensions to approximations for the G/G/m queue with applications,” IEEE Trans. Autom. Sci. Eng., vol. 4, pp. 523–532, 2007.
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[11] F. P. Kelly, “The throughput of a series of buffers,” Adv. Appl. Probability, vol. 14, no. 3, pp. 633–653, 1982. [12] B. Avi-Itzhak and S. Halfin, “Servers in tandem with communication and manufacturing blocking,” J. Appl. Probability, vol. 30, pp. 429–437, 1993. [13] B. Avi-Itzhak, “Servers in tandem with k-stage blocking and communications-type flow,” J. Appl. Probability, vol. 31, pp. 1061–1069, 1994. [14] B. Avi-Itzhak and M. Yadin, “A sequence of servers with arbitrary input and regular service times revisited,” Manage. Sci., vol. 41, no. 6, pp. 1039–1047, 1995. [15] B. Avi-Itzhak and H. Levy, “Buffer requirements and server ordering in a tandem queue with correlated service times,” Math. Oper. Res., vol. 26, no. 2, pp. 358–374, 2001. [16] J. M. Kim and B. Avi-Itzhak, “Ordering of tandem constant-service stations to minimize in-process stock cost,” Rutcor Research Rep., RRR32-93, 1993. [17] J. R. Perkins and P. R. Kumar, “Optimal control of pull manufacturing systems,” IEEE Trans. Autom. Control, vol. 40, pp. 2040–2051, 1995. [18] D. P. Martin, “Capacity and cycle time-throughput understanding system (CAC-TUS): An analysis tool to determine the components of capacity and cycle time in a semiconductor manufacturing line,” in Proc. 1999 IEEE/SEMI Adv. Semicond. Manuf. Conf. Workshop, Sep. 1999, pp. 127–131. [19] D. Pillai, “The future of semiconductor manufacturing: Factory integration breakthrough opportunities,” IEEE Robot. Autom. Mag., vol. 13, no. 4, pp. 16–24, Dec. 2008. [20] M. W. Dawande, H. N. Geismar, S. P. Sethi, and C. Sriskandarajah, Throughput Optimization in Robotic Cells, ser. Springer International Series in Operations Research and Management Science. New York: Springer, 2007. [21] J. R. Morrison, “Regular flow line models for semiconductor cluster tools: A case of lot dependent process times,” in Proc. 5th IEEE Conf. Autom. Sci. Eng., Aug. 2009, pp. 561–566. [22] J. R. Morrison, “Flow lines with regular service times: Evolution of delay, state dependent failures and semiconductor wafer fabrication,” in Proc. 4th IEEE Conf. Autom. Sci. Eng., Aug. 2008, pp. 247–252. [23] S. Ding, J. Yi, and M. T. Zhang, “Multicluster tools scheduling: An integrated event graph and network model approach,” IEEE Trans. Semicond. Manuf., vol. 19, pp. 339–351, 2006. [24] F. Baccelli, G. Cohen, G. J. Olsder, and J. P. Quadrat, Synchronization and Linearity. New York: Wiley, 1992. James R. Morrison (S’97–M’00) received B.S. degrees in electrical engineering and in mathematics from the University of Maryland, College Park, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Illinois at Urbana–Champaign, Urbana, in 1997 and 2000, respectively. He was with the Fab Operations Engineering Department at the IBM Corporation from 2000 to 2005. He is currently an Assistant Professor in the Department of Industrial and Systems Engineering, KAIST, South Korea. In September 2008, he became a Co-Chair of the IEEE Robotics and Automation Society Technical Committee on Semiconductor Manufacturing Automation. His research interests include semiconductor wafer fabrication, system design, queueing networks, and stochastic control.
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