Differential Current-Mode Signaling for Robust and ... - IEEE Xplore
Differential Current-Mode Signaling for Robust and Power Efficient On-Chip Global Interconnects Liang Zhang, John Wilson, Rizwan Bashirullah*, and Paul Franzon
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606 * Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 3261 1 Tel: (919)513-7261, Fax: (919)515-2285 Email; {lzhang3, jmwilson, paulf}@ncsu.edu, *[email protected] ABSTRACT A global interconnect scheme with better current return path control is presented for accurate inductance analysis and robust interconnect design. High performance is obtained by using differential signaling, current-mode sensing, bridge termination, and driver pre-emphasis. INTRODUCTION On-chip global interconnects are typically routed in top-level metal layers with a large cross section to reduce resistance. With increasing signal frequency and signal edge rate, inductance is becoming an important consideration for global timing analysis and signal integrity [1]. While on-chip capacitance extraction can be restricted in a region around interested conductors without losing accuracy [2], the longrange effect of inductance makes current loops in integrated circuits unpredictable. Partial-elementequivalent-circuit (PEEC) models magnetic influence between pairs of conductor segments instead of loops [3], but it is extremely computation expensive and almost not feasible for a whole chip problem. To achieve higher modeling efficiency, loop-based inductance analysis has been proposed for clock networks with close current return paths [4]. In this work, a differential current-mode signaling scheme with drive pre-emphasis technique is proposed. It allows better return path control and loop-based inductance analysis for on-chip global buses. Diver preemphasis and current-mode sensing increase interconnect channel bandwidth. These techniques reduce the size of drivers and minimize the number of repeater required for global interconnects. Together with differential signaling, a current return path can be relatively well-defined and simultaneous switching noise (SSN) can be largely reduced. With a bridge resistor termination to cut the static current of current-mode signaling by half and low signal swing, this repeater-free scheme is more power-efficient than a conventional voltage mode bus scheme for data activity factors beyond 0.1. Besides, this differential scheme only requires 7.9% more bus routing area than single-ended designs for a 16-bit bus, and saves all of the repeater placement blockages. INDUCTANCE MODEL Magnetic interaction model as in [4, 5] is used in the inductance analysis of one pair of repeater-free differential interconnects. Fig. 1 shows current la flowing through interconnect linea. The relationship between the time-derivative of la and the induced voltage Vind on lineb is,
-L
V
dl
(1)
a
where Lba is the mutual inductance of linea upon lineb. Vind results from the integration of the induced electric field Eind and Eind is created by the time variation of magnetic flux (D,
Vinnd=|
=
dt If all the current in linea is assumed to be condensed to its axis, it generates a magnetic field B b
(2) o I 2rTPitch_
at the center of lineb. go is the permeability of free space. If the magnetic field along the cross section of lineb is approximated as Bo, we have,
(D= JB. dS =WidthLengh 2
i
where S is the surface of lineb on XY plane. By combining (1) - (3), WidthLengt h yo dI,
hitd
Pitch
2 c dt
From (1) and (4),
0-7803-9220-51051$20.00 2005 IEEE.
315
Ia
(3) (4)
L
ba=WidthLengt h
(5)
0
I
Pitch 27r As such, this simple closed-form calculation can be used for the inductance extraction of differential interconnects. ba
lina Pitch
l/-ia -t Width
B , JI'1
X
"
linebtfl
' X81-8F
Thickness
------Eind
MVin-d_ ----------------Figure 1. Magnetic field created by the time-variant current in linea induces voltage in lineb. The skin effect and proximity effect are ignored in this analysis because both the skin depth and proximity depth are larger than the line width used in our interconnect scheme. For a 5OpS rise time tr, the characteristic frequency can be defined as f - 0.35 = 7GHZ L-------------(4
tr
For an aluminum conductivity a=3.8xlO8( )n' skin depth 5 is given by [6], S=(;rfy0a)05 = 0.31 gm Line proximity effect can be modeled as [4], R PrOx (f)
(6)
- 2 Rshe Pitch
RDC[1 + ( Uojidh f)21 I
(7)
We define the proximity depth as a width where proximity effect changes the resistance by 5% of RDC. For R,she=0.076iWsquare, it is roughly 5,um. Driver pre-emphasis technique and current-mode signaling allow us to use interconnects as narrow as 0.4pm for signal transmission. It is smaller than both 28 and the proximity depth. Therefore, the skin effect and proximity effect are ignorable in this case. INTERCONNECT SCHEME As shown in Fig. 2, differential signaling and current-mode sensing are used to apply driver pre-emphasis technique to on-chip global interconnects [7]. A one-tap FIR filter is used to reduce driver power overhead. High frequency signal components are pre-emphasized at the driver side to improve interconnect channel bandwidth. A differential 200mV low signal swing is built on the bridge resistor RB. This bridge termination cuts the static current of current-mode signaling by half and provides a virtual ground of VDD/2. As a result from the driver size reduction, repeater minimization and differential signaling in this scheme, peak current is reduced by 63.8% comparing to a conventional voltage-mode bus design (Fig. 3). Driver
elay
oufL HU.
V
,.::
D2------
Digtl Figure 2. Interconnect scheme with driver pre-emphasis technique, differential signaling, current-mode sensing, and bridge termination.
316
6-3,8%-1
Figure 3. Peak current reduction. Fig. 4 shows the structure implementation of a 16Gb/s differential bus and a reference bench of a singleended full-swing bus. 10mm long metal-4 lines with 0.8gm pitch-minimum (Pmin) in TSMC 0.25gm technology are used. Every differential pair has a pitch of 3.2gm, or 2xPmin per line. The single-ended bus uses drivers with twice size of differential drivers. They still need wider wires with 3xPmin and two repeaters along each line to run signal at the same speed, plus one Vdd/Gnd shielding line for each 4-bit to provide signal return path. As such, the proposed differential bus takes only 7.9% more bus routing area than the single-ended bus and it requires none of the active area needed for repeaters. 2xPmin or lxPmin can be used to save the routing area of the reference bench, but that requires much more repeaters to meet the delay goal. This proposed bus architecture reduces power consumption by 26.0% to 51.2% for data activity factors above 0.2 comparing to the single-ended bus architecture and only consumes more power for data activity factors less than 0.1. Crosstalk from the same metal layer is examined by transitioning the two neighbor pairs in various directions. The coupling on the differential signal swing is always under 20% for any direction of transitions. Crosstalk of the full-swing signal from other metal layer is analyzed in Fig. 5. The worst case is that the signals on the 8-bit full-swing bus running orthogonally switch to the same direction. Their coupling on the low-swing differential bus is small due to the I fE coupling capacitance between the two layers. As shown in the figure, it can be rejected as common-mode noise. CONCLUSIONS Advanced signaling methods, driver pre-emphasis, differential, and current-mode sensing, were used in this proposed interconnect scheme. The improved channel bandwidth allowed a relatively well-defined signal loop and narrow lines to be used for global communication. Therefore, this scheme is suitable for loopbased inductance analysis and robust again crosstalk noise. It generates 63.8% less peak current to help reduce SSN noise and it is more power-efficient than a conventional voltage-mode bus scheme for data activity factors beyond 0.1. ACKNOWLEDGMENTS We thank Dr. Stephen Mick, Lei Luo, Jian Xu, Evan Erickson, Karthik Chandrasekar, and Dr. Steve Lipa for helpful discussions. This work is supported by NSF under CCR-9988334 and AFRL under F29601-033-0135 REFERENCES [1] A. Deutsch, et al., "On-chip wiring design challenges for gigahertz operation," proc of IEEE, vol. 89, pp. 529-555, Apr 2001. [2] V. Veremey and R. Mittra, "Efficient computation of interconnect capacitances using the domain decomposition approach," EPEP, pp. 277-280, Oct 1998.
317
[3] A. E. Ruehli, "Inductance calculation in a complex integrated circuit environment," IBM J. Res. Develop., pp. 16470-16485, 1972. [4] X. Huang, et al., "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design," IEEE J. Solid-State Circuits, vol. 38, no. 3, Mar 2003. [5] M. Beattie and L. Pileggi, "Inductance 101: modeling and extraction," DAC, pp. 323-328, Jun 2001. [6] J. Jackson, Classical Electrodynamics, 2nd Edition, J. Wiley, New York, 1984. [7] L. Zhang, et al., "Driver pre-emphasis techniques for on-chip global buses," Accepted by ISLPED, Aug 2005. Gnd
bu O]
[2
bus[12]
3
[15]
1
Gnd
K s0O] ] ]2 0-0 2 [150 1.2pm 21xm
16 bit differential bus with 2xPmin, shielded by I Gnd line at each side
2.4gm
H Rea,e ter_f_l7.I.4~.~f L [ LJ_KJ_ KJ__ KJ_ H _
Re pe ter
Gnd bus[O] [1]
[2]
Vdd bus[12] [13] [14] [15] Gnd [3] Vdd 16 bit single-ended bus with 3xPmin, shielded by I Gnd/Vdd line for every 4 bits
Figure 4. Differential and single-ended 16-bit bus structure. 1.40
F.F..
---------
---------
1.30
[ 1.20
F.
---------
-.......--....-.........-............-.-.-.-.---.. I1.On
1.10 ... --.... 1 0.On
---------
Low-swing differential bus .____ -
-
-
-
-__ -
--
I I I I
.......
time
12.0n
13.On
12.On
13.On
0.1
j1
r _iRJ1IVEFLFLJ1IFL
0.0
-0.1
8-bit full-swing bus orthogonally crossing from other metal layer
-
V''10.On
11.On
time
Figure 5. Crosstalk of full-swing signal from other metal layer.
318
Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27606 * Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 3261 1 Tel: (919)513-7261, Fax: (919)515-2285 Email; {lzhang3, jmwilson, paulf}@ncsu.edu, *[email protected] ABSTRACT A global interconnect scheme with better current return path control is presented for accurate inductance analysis and robust interconnect design. High performance is obtained by using differential signaling, current-mode sensing, bridge termination, and driver pre-emphasis. INTRODUCTION On-chip global interconnects are typically routed in top-level metal layers with a large cross section to reduce resistance. With increasing signal frequency and signal edge rate, inductance is becoming an important consideration for global timing analysis and signal integrity [1]. While on-chip capacitance extraction can be restricted in a region around interested conductors without losing accuracy [2], the longrange effect of inductance makes current loops in integrated circuits unpredictable. Partial-elementequivalent-circuit (PEEC) models magnetic influence between pairs of conductor segments instead of loops [3], but it is extremely computation expensive and almost not feasible for a whole chip problem. To achieve higher modeling efficiency, loop-based inductance analysis has been proposed for clock networks with close current return paths [4]. In this work, a differential current-mode signaling scheme with drive pre-emphasis technique is proposed. It allows better return path control and loop-based inductance analysis for on-chip global buses. Diver preemphasis and current-mode sensing increase interconnect channel bandwidth. These techniques reduce the size of drivers and minimize the number of repeater required for global interconnects. Together with differential signaling, a current return path can be relatively well-defined and simultaneous switching noise (SSN) can be largely reduced. With a bridge resistor termination to cut the static current of current-mode signaling by half and low signal swing, this repeater-free scheme is more power-efficient than a conventional voltage mode bus scheme for data activity factors beyond 0.1. Besides, this differential scheme only requires 7.9% more bus routing area than single-ended designs for a 16-bit bus, and saves all of the repeater placement blockages. INDUCTANCE MODEL Magnetic interaction model as in [4, 5] is used in the inductance analysis of one pair of repeater-free differential interconnects. Fig. 1 shows current la flowing through interconnect linea. The relationship between the time-derivative of la and the induced voltage Vind on lineb is,
-L
V
dl
(1)
a
where Lba is the mutual inductance of linea upon lineb. Vind results from the integration of the induced electric field Eind and Eind is created by the time variation of magnetic flux (D,
Vinnd=|
=
dt If all the current in linea is assumed to be condensed to its axis, it generates a magnetic field B b
(2) o I 2rTPitch_
at the center of lineb. go is the permeability of free space. If the magnetic field along the cross section of lineb is approximated as Bo, we have,
(D= JB. dS =WidthLengh 2
i
where S is the surface of lineb on XY plane. By combining (1) - (3), WidthLengt h yo dI,
hitd
Pitch
2 c dt
From (1) and (4),
0-7803-9220-51051$20.00 2005 IEEE.
315
Ia
(3) (4)
L
ba=WidthLengt h
(5)
0
I
Pitch 27r As such, this simple closed-form calculation can be used for the inductance extraction of differential interconnects. ba
lina Pitch
l/-ia -t Width
B , JI'1
X
"
linebtfl
' X81-8F
Thickness
------Eind
MVin-d_ ----------------Figure 1. Magnetic field created by the time-variant current in linea induces voltage in lineb. The skin effect and proximity effect are ignored in this analysis because both the skin depth and proximity depth are larger than the line width used in our interconnect scheme. For a 5OpS rise time tr, the characteristic frequency can be defined as f - 0.35 = 7GHZ L-------------(4
tr
For an aluminum conductivity a=3.8xlO8( )n' skin depth 5 is given by [6], S=(;rfy0a)05 = 0.31 gm Line proximity effect can be modeled as [4], R PrOx (f)
(6)
- 2 Rshe Pitch
RDC[1 + ( Uojidh f)21 I
(7)
We define the proximity depth as a width where proximity effect changes the resistance by 5% of RDC. For R,she=0.076iWsquare, it is roughly 5,um. Driver pre-emphasis technique and current-mode signaling allow us to use interconnects as narrow as 0.4pm for signal transmission. It is smaller than both 28 and the proximity depth. Therefore, the skin effect and proximity effect are ignorable in this case. INTERCONNECT SCHEME As shown in Fig. 2, differential signaling and current-mode sensing are used to apply driver pre-emphasis technique to on-chip global interconnects [7]. A one-tap FIR filter is used to reduce driver power overhead. High frequency signal components are pre-emphasized at the driver side to improve interconnect channel bandwidth. A differential 200mV low signal swing is built on the bridge resistor RB. This bridge termination cuts the static current of current-mode signaling by half and provides a virtual ground of VDD/2. As a result from the driver size reduction, repeater minimization and differential signaling in this scheme, peak current is reduced by 63.8% comparing to a conventional voltage-mode bus design (Fig. 3). Driver
elay
oufL HU.
V
,.::
D2------
Digtl Figure 2. Interconnect scheme with driver pre-emphasis technique, differential signaling, current-mode sensing, and bridge termination.
316
6-3,8%-1
Figure 3. Peak current reduction. Fig. 4 shows the structure implementation of a 16Gb/s differential bus and a reference bench of a singleended full-swing bus. 10mm long metal-4 lines with 0.8gm pitch-minimum (Pmin) in TSMC 0.25gm technology are used. Every differential pair has a pitch of 3.2gm, or 2xPmin per line. The single-ended bus uses drivers with twice size of differential drivers. They still need wider wires with 3xPmin and two repeaters along each line to run signal at the same speed, plus one Vdd/Gnd shielding line for each 4-bit to provide signal return path. As such, the proposed differential bus takes only 7.9% more bus routing area than the single-ended bus and it requires none of the active area needed for repeaters. 2xPmin or lxPmin can be used to save the routing area of the reference bench, but that requires much more repeaters to meet the delay goal. This proposed bus architecture reduces power consumption by 26.0% to 51.2% for data activity factors above 0.2 comparing to the single-ended bus architecture and only consumes more power for data activity factors less than 0.1. Crosstalk from the same metal layer is examined by transitioning the two neighbor pairs in various directions. The coupling on the differential signal swing is always under 20% for any direction of transitions. Crosstalk of the full-swing signal from other metal layer is analyzed in Fig. 5. The worst case is that the signals on the 8-bit full-swing bus running orthogonally switch to the same direction. Their coupling on the low-swing differential bus is small due to the I fE coupling capacitance between the two layers. As shown in the figure, it can be rejected as common-mode noise. CONCLUSIONS Advanced signaling methods, driver pre-emphasis, differential, and current-mode sensing, were used in this proposed interconnect scheme. The improved channel bandwidth allowed a relatively well-defined signal loop and narrow lines to be used for global communication. Therefore, this scheme is suitable for loopbased inductance analysis and robust again crosstalk noise. It generates 63.8% less peak current to help reduce SSN noise and it is more power-efficient than a conventional voltage-mode bus scheme for data activity factors beyond 0.1. ACKNOWLEDGMENTS We thank Dr. Stephen Mick, Lei Luo, Jian Xu, Evan Erickson, Karthik Chandrasekar, and Dr. Steve Lipa for helpful discussions. This work is supported by NSF under CCR-9988334 and AFRL under F29601-033-0135 REFERENCES [1] A. Deutsch, et al., "On-chip wiring design challenges for gigahertz operation," proc of IEEE, vol. 89, pp. 529-555, Apr 2001. [2] V. Veremey and R. Mittra, "Efficient computation of interconnect capacitances using the domain decomposition approach," EPEP, pp. 277-280, Oct 1998.
317
[3] A. E. Ruehli, "Inductance calculation in a complex integrated circuit environment," IBM J. Res. Develop., pp. 16470-16485, 1972. [4] X. Huang, et al., "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design," IEEE J. Solid-State Circuits, vol. 38, no. 3, Mar 2003. [5] M. Beattie and L. Pileggi, "Inductance 101: modeling and extraction," DAC, pp. 323-328, Jun 2001. [6] J. Jackson, Classical Electrodynamics, 2nd Edition, J. Wiley, New York, 1984. [7] L. Zhang, et al., "Driver pre-emphasis techniques for on-chip global buses," Accepted by ISLPED, Aug 2005. Gnd
bu O]
[2
bus[12]
3
[15]
1
Gnd
K s0O] ] ]2 0-0 2 [150 1.2pm 21xm
16 bit differential bus with 2xPmin, shielded by I Gnd line at each side
2.4gm
H Rea,e ter_f_l7.I.4~.~f L [ LJ_KJ_ KJ__ KJ_ H _
Re pe ter
Gnd bus[O] [1]
[2]
Vdd bus[12] [13] [14] [15] Gnd [3] Vdd 16 bit single-ended bus with 3xPmin, shielded by I Gnd/Vdd line for every 4 bits
Figure 4. Differential and single-ended 16-bit bus structure. 1.40
F.F..
---------
---------
1.30
[ 1.20
F.
---------
-.......--....-.........-............-.-.-.-.---.. I1.On
1.10 ... --.... 1 0.On
---------
Low-swing differential bus .____ -
-
-
-
-__ -
--
I I I I
.......
time
12.0n
13.On
12.On
13.On
0.1
j1
r _iRJ1IVEFLFLJ1IFL
0.0
-0.1
8-bit full-swing bus orthogonally crossing from other metal layer
-
V''10.On
11.On
time
Figure 5. Crosstalk of full-swing signal from other metal layer.
318
