Digital Integrated Circuits
Digital Integrated Circuits A Design Perspective
Jan M. Rabaey
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
The First Computer
The Babbage Difference Engine (1832) 25,000 parts cost: ? 7,470 Digital Integrated Circuits
Introduction
© Prentice Hall 1995
ENIAC - The first electronic computer (1946)
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Evolution in Complexity
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Evolution in Transistor Count
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Evolution in Speed/Performance
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Intel 4004 Micro-Processor
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Intel Pentium (II) microprocessor
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Silicon in 2010 D ensity AccessTim e (Gbits/cm 2) (ns) Die Area: 2.5x2.5 cm D RAM 8.5 10 Voltage: 0.6 V D RAM (Logic) 2.5 10 Technology: 0.07 µm SRAM (Cache) 0.3 1.5 D ensity M ax.Ave.Pow er Clock Rate (GH z) (M gates/cm 2) (W /cm 2) 25 54 Custom 3 10 27 1.5 Std.Cell 5 18 1 Gate Array Single-M ask GA 2.5 12.5 0.7 0.4 4.5 0.25 FPGA Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Design Abstraction Levels SYSTEM
MODULE + GATE
CIRCUIT
DEVICE G S n+
Digital Integrated Circuits
Introduction
D n+
© Prentice Hall 1995
The Devices
Jan M. Rabaey
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Goal of this chapter • Present intuitive understanding of device operation • Introduction of basic device equations • Introduction of models for manual analysis • Introduction of models for SPICE simulation • Analysis of secondary and deep-sub-micron effects • Future trends Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Diode B
A
Al
SiO2
p n Cross-section of pn-junction in an IC process A
Al A
p n
B
B One-dimensional representation
Digital Integrated Circuits
diode symbol
Devices
© Prentice Hall 1995
Depletion Region hole diffusion electron diffusion p
(a) Current flow.
n hole drift electron drift Charge Density
ρ +
x Distance
-
Electrical Field
ξ
x
(b) Charge density.
(c) Electric field.
V Potential ψ0 -W 1
Digital Integrated Circuits
W2
Devices
x
(d) Electrostatic potential.
© Prentice Hall 1995
Diode Current
Digital Integrated Circuits
Devices
© Prentice Hall 1995
pn(W 2)
Forward Bias
pn0 Lp
np0
p-region
-W
1
0
W
2
n-region
x
diffusion Digital Integrated Circuits
Devices
© Prentice Hall 1995
Reverse Bias
pn0
np0
p-region
-W1 0
W2
x n-region
diffusion Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diode Types pn(x)
Short-base Diode (standard in semiconductor devices) x
pn0 Wn
pn(x)
pn0
Digital Integrated Circuits
Long-base Diode
x Wn
Devices
© Prentice Hall 1995
Models for Manual Analysis +
ID = IS(eV D/φT – 1)
VD
+ +
VD –
–
VDon
–
(a) Ideal diode model
Digital Integrated Circuits
ID
(b) First-order diode model
Devices
© Prentice Hall 1995
Junction Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diffusion Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diode Switching Time Rsrc
VD
V1
ID
Vsrc V2
t=0
t=T
VD
Excess charge Space charge
ON
OFF
ON
Time Digital Integrated Circuits
Devices
© Prentice Hall 1995
Secondary Effects
ID (A)
0.1
0
–0.1 –25.0
–15.0
–5.0
0
5.0
VD (V)
Avalanche Breakdown Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diode Model RS + VD
ID
CD
-
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE Parameters
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The MOS Transistor Gate Oxyde Gate Source
Polysilicon
n+
Drain n+
p-substrate
Field-Oxyde (SiO2)
p+ stopper
Bulk Contact
CROSS-SECTION of NMOS Transistor
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Cross-Section of CMOS Technology
Digital Integrated Circuits
Devices
© Prentice Hall 1995
MOS transistors Types and Symbols D
D
G
G S
S
NMOS Enhancement NMOS Depletion D
D
G
G S
S
PMOS Enhancement
Digital Integrated Circuits
B
Devices
NMOS with Bulk Contact © Prentice Hall 1995
Threshold Voltage: Concept +
S
VGS -
D
G
n+
n+
n-channel
Depletion Region p-substrate B
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Threshold Voltage
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Current-Voltage Relations VGS
S
VDS G
n+
–
V(x)
ID
D n+
+ L
x
p-substrate B
MOS transistor and its bias conditions Digital Integrated Circuits
Devices
© Prentice Hall 1995
Current-Voltage Relations
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Transistor in Saturation VGS VDS > VGS - VT
G
D
S n+
Digital Integrated Circuits
-
VGS - VT
Devices
+
n+
© Prentice Hall 1995
I-V Relation VDS = VGS-V T
Saturation VGS = 4V
1
0.0
VGS = 3V
1.0
2.0
3.0
VGS = 2V VGS = 1V 4.0 5.0
V DS (V)
0.020 ÷√ID
Triode
Square Dependence
ID (mA)
2
VGS = 5V
0.010
Subthreshold Current
0.0
2.0 VT1.0 VGS (V)
3.0
(b) √ID as a function of VGS (for V DS = 5V).
(a) ID as a function of VD S
NMOS Enhancement Transistor: W = 100 µm, L = 20 µm Digital Integrated Circuits
Devices
© Prentice Hall 1995
A model for manual analysis
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Dynamic Behavior of MOS Transistor G
CGS
CGD D
S
CGB
CSB
CDB
B
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Gate Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Average Gate Capacitance Different distributions of gate capacitance for varying operating conditions
Most important regions in digital design: saturation and cut-off
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diffusion Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Junction Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Sub-Micron MOS Transistor • Threshold Variations • Parasitic Resistances • Velocity Sauturation and Mobility Degradation • Subthreshold Conduction • Latchup
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Threshold Variations VT Long-channel threshold
Low VDS threshold
L Drain-induced barrier lowering (for low L)
Threshold as a function of the length (for low VDS)
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Parasitic Resistances Polysilicon gate LD
G
Drain contact
W
VGS,eff D
S RS
RD Drain
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Velocity Saturation (1)
constant velocity
Constant mobility (slope = µ)
Esat = 1.5
E ( V/µm)
700
250 0
Et (V/µm)
100
(b) Mobility degradation
(a) Velocity saturation
Digital Integrated Circuits
µn0
7 2 µn (cm /Vs)
υ n (cm/sec)
υ sat = 10
Devices
© Prentice Hall 1995
Velocity Saturation (2) 1.5
0.5
ID (m A)
VG S = 3 0.5 VG S = 2 VG S = 1 0.0
1.0
2.0
VD S
3.0 (V)
4.0
5.0
ID (m A)
VG S = 4
1.0
L inea r D ep en d en ce
VG S = 5
0 0.0
1.0
VG S
(a)ID as a function ofV D S
2.0 (V)
3.0
(b)ID as a function ofV G S (forVD S = 5 V).
Linear D ependence on VG S Digital Integrated Circuits
Devices
© Prentice Hall 1995
Sub-Threshold Conduction 10−2
ln(ID) (A)
10−4
Linear region
10−6 10−8 10−10 10−120.0
Digital Integrated Circuits
Subthreshold exponential region
VT 1.0
2.0
3.0
VGS (V)
Devices
© Prentice Hall 1995
Latchup VDD VDD +
p
n
+
+
n
+
p
p
n-well
+
+
p-source
n
Rnwell
Rpsubs
n-source p-substrate (a) Origin of latchup
Digital Integrated Circuits
Rnwell
Devices
Rpsubs
(b) Equivalent circuit
© Prentice Hall 1995
SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular
Digital Integrated Circuits
Devices
© Prentice Hall 1995
MAIN MOS SPICE PARAMETERS
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE Parameters for Parasitics
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE Transistors Parameters
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Fitting level-1 model for manual analysis Region of matching ID
Short-channel I-V curve
VGS = 5 V
Long-channel approximation VDS = 5 V
VDS
Select k’ and λ such that best matching is obtained @ Vgs= Vds = VDD
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Technology Evolution
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Bipolar Transistor E
B
p+
n+
p+ isolation
C
n+
p p+
n-epitaxy n+ buried layer p-substrate (a) Cross-sectional view. B
E
n+
p
n
C
(b) Idealized transistor structure.
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Schematic Symbols and Sign Conventions
VBC
–
C
VBC
IC
+
IC
+
+
B
IB
–
C
+
B
VCE + VBE
IB
– – E
+ VBE
IE
– – E
(a) npn
Digital Integrated Circuits
VCE
IE
(b) pnp
Devices
© Prentice Hall 1995
Operations Modes
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Forward Active Operation
Carrier Concentration
E
nb(0)
Depletion Regions
B
C
pc0 nb0
pe0
x 0
W WB
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Current Components B
E
C
1
IE 2
IC 3
x electrons
IB
holes
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Reverse Active Carrier Concentration
E
B
C
nb(W) pc0 pe0
nb0 nb(0)
x
0
W WB
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Saturation Mode Carrier Concentration nb (0)
E
B
C
nb(W)
QA
pc0
QS pe0 nb0 0
x W
WB
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Cutoff Carrier Concentration
E
B
nb (0)
pe0
nb0
C
nb (W)
pc0 x
0
W WB
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Bipolar Transistor Operation 0
15
I B=25 µA
Forward Operation
I B=50 µA
Active
I B=75 µA 10
IB =75 µA
IC(mA)
I B=100 µA IC (mA)
IB =100 µA
-0.25
IB =50 µA
5
IB =25 µA
Reverse Operation Saturation -0.5 -3.0
0 0.0
-1.0 VC E (V)
Digital Integrated Circuits
2.0 VCE (V)
Devices
© Prentice Hall 1995
A Model for Manual Analysis IB B
IB C
+ VBE
βF IB
B
C
VBE(on)
+ –
βF IB
– IB = IS(eV BE/φT – 1)
E
E
(a) Forward-active
(b) Forward-active (simplified)
IB C
B VBE(sat) + –
+ –
E
VCE(sat) IC < βFIB
(c) Forward-saturation
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Capacitive Model for Bipolar Transistor C QR
Cbc
Ccs collector-substrate junction capacitance
B QF
base charge
S
Cbe
E base-emitter junction capacitances base-collector
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Junction Capacitances
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Base Charge - Diffusion Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Bipolar Transistors - Secondary Effects
• Early Voltage • Parasitic Resistances • Beta Variations
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Early Voltage IC
Forward Active
VBE3
Saturation VBE2
VBE1
VCE
VA
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Parasitic Resistance E
B
rE
p+
n+
C
p+
p
n+
isolation rB
n-epitaxy
rC1
p+
rC3
n+ buried layer
rC2 p-substrate
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Beta Variations ln (I) IKF IC
High Level Injection βF
Recombination
IB
VBE (linear)
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE models for Bipolar
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Main Bipolar Transistor SPICE Models
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Spice Parameters for Parasitics
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE Transistor Parameters
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Process Variations Devices parameters vary between runs and even on the same die! Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices.
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Impact of Device Variations 2.10 2.10 Delay (nsec)
Delay (nsec)
1.90
1.90
1.70
1.70
1.50 1.10 1.20 1.30 1.40 1.50 1.60 Leff (in mm)
1.50 –0.90
–0.80
–0.70
–0.60
–0.50
VTp (V)
Delay of Adder circuit as a function of variations in L and VT Digital Integrated Circuits
Devices
© Prentice Hall 1995
Jan M. Rabaey
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
The First Computer
The Babbage Difference Engine (1832) 25,000 parts cost: ? 7,470 Digital Integrated Circuits
Introduction
© Prentice Hall 1995
ENIAC - The first electronic computer (1946)
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Evolution in Complexity
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Evolution in Transistor Count
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Evolution in Speed/Performance
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Intel 4004 Micro-Processor
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Intel Pentium (II) microprocessor
Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Silicon in 2010 D ensity AccessTim e (Gbits/cm 2) (ns) Die Area: 2.5x2.5 cm D RAM 8.5 10 Voltage: 0.6 V D RAM (Logic) 2.5 10 Technology: 0.07 µm SRAM (Cache) 0.3 1.5 D ensity M ax.Ave.Pow er Clock Rate (GH z) (M gates/cm 2) (W /cm 2) 25 54 Custom 3 10 27 1.5 Std.Cell 5 18 1 Gate Array Single-M ask GA 2.5 12.5 0.7 0.4 4.5 0.25 FPGA Digital Integrated Circuits
Introduction
© Prentice Hall 1995
Design Abstraction Levels SYSTEM
MODULE + GATE
CIRCUIT
DEVICE G S n+
Digital Integrated Circuits
Introduction
D n+
© Prentice Hall 1995
The Devices
Jan M. Rabaey
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Goal of this chapter • Present intuitive understanding of device operation • Introduction of basic device equations • Introduction of models for manual analysis • Introduction of models for SPICE simulation • Analysis of secondary and deep-sub-micron effects • Future trends Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Diode B
A
Al
SiO2
p n Cross-section of pn-junction in an IC process A
Al A
p n
B
B One-dimensional representation
Digital Integrated Circuits
diode symbol
Devices
© Prentice Hall 1995
Depletion Region hole diffusion electron diffusion p
(a) Current flow.
n hole drift electron drift Charge Density
ρ +
x Distance
-
Electrical Field
ξ
x
(b) Charge density.
(c) Electric field.
V Potential ψ0 -W 1
Digital Integrated Circuits
W2
Devices
x
(d) Electrostatic potential.
© Prentice Hall 1995
Diode Current
Digital Integrated Circuits
Devices
© Prentice Hall 1995
pn(W 2)
Forward Bias
pn0 Lp
np0
p-region
-W
1
0
W
2
n-region
x
diffusion Digital Integrated Circuits
Devices
© Prentice Hall 1995
Reverse Bias
pn0
np0
p-region
-W1 0
W2
x n-region
diffusion Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diode Types pn(x)
Short-base Diode (standard in semiconductor devices) x
pn0 Wn
pn(x)
pn0
Digital Integrated Circuits
Long-base Diode
x Wn
Devices
© Prentice Hall 1995
Models for Manual Analysis +
ID = IS(eV D/φT – 1)
VD
+ +
VD –
–
VDon
–
(a) Ideal diode model
Digital Integrated Circuits
ID
(b) First-order diode model
Devices
© Prentice Hall 1995
Junction Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diffusion Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diode Switching Time Rsrc
VD
V1
ID
Vsrc V2
t=0
t=T
VD
Excess charge Space charge
ON
OFF
ON
Time Digital Integrated Circuits
Devices
© Prentice Hall 1995
Secondary Effects
ID (A)
0.1
0
–0.1 –25.0
–15.0
–5.0
0
5.0
VD (V)
Avalanche Breakdown Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diode Model RS + VD
ID
CD
-
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE Parameters
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The MOS Transistor Gate Oxyde Gate Source
Polysilicon
n+
Drain n+
p-substrate
Field-Oxyde (SiO2)
p+ stopper
Bulk Contact
CROSS-SECTION of NMOS Transistor
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Cross-Section of CMOS Technology
Digital Integrated Circuits
Devices
© Prentice Hall 1995
MOS transistors Types and Symbols D
D
G
G S
S
NMOS Enhancement NMOS Depletion D
D
G
G S
S
PMOS Enhancement
Digital Integrated Circuits
B
Devices
NMOS with Bulk Contact © Prentice Hall 1995
Threshold Voltage: Concept +
S
VGS -
D
G
n+
n+
n-channel
Depletion Region p-substrate B
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Threshold Voltage
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Current-Voltage Relations VGS
S
VDS G
n+
–
V(x)
ID
D n+
+ L
x
p-substrate B
MOS transistor and its bias conditions Digital Integrated Circuits
Devices
© Prentice Hall 1995
Current-Voltage Relations
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Transistor in Saturation VGS VDS > VGS - VT
G
D
S n+
Digital Integrated Circuits
-
VGS - VT
Devices
+
n+
© Prentice Hall 1995
I-V Relation VDS = VGS-V T
Saturation VGS = 4V
1
0.0
VGS = 3V
1.0
2.0
3.0
VGS = 2V VGS = 1V 4.0 5.0
V DS (V)
0.020 ÷√ID
Triode
Square Dependence
ID (mA)
2
VGS = 5V
0.010
Subthreshold Current
0.0
2.0 VT1.0 VGS (V)
3.0
(b) √ID as a function of VGS (for V DS = 5V).
(a) ID as a function of VD S
NMOS Enhancement Transistor: W = 100 µm, L = 20 µm Digital Integrated Circuits
Devices
© Prentice Hall 1995
A model for manual analysis
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Dynamic Behavior of MOS Transistor G
CGS
CGD D
S
CGB
CSB
CDB
B
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Gate Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Average Gate Capacitance Different distributions of gate capacitance for varying operating conditions
Most important regions in digital design: saturation and cut-off
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Diffusion Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Junction Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest
Digital Integrated Circuits
Devices
© Prentice Hall 1995
The Sub-Micron MOS Transistor • Threshold Variations • Parasitic Resistances • Velocity Sauturation and Mobility Degradation • Subthreshold Conduction • Latchup
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Threshold Variations VT Long-channel threshold
Low VDS threshold
L Drain-induced barrier lowering (for low L)
Threshold as a function of the length (for low VDS)
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Parasitic Resistances Polysilicon gate LD
G
Drain contact
W
VGS,eff D
S RS
RD Drain
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Velocity Saturation (1)
constant velocity
Constant mobility (slope = µ)
Esat = 1.5
E ( V/µm)
700
250 0
Et (V/µm)
100
(b) Mobility degradation
(a) Velocity saturation
Digital Integrated Circuits
µn0
7 2 µn (cm /Vs)
υ n (cm/sec)
υ sat = 10
Devices
© Prentice Hall 1995
Velocity Saturation (2) 1.5
0.5
ID (m A)
VG S = 3 0.5 VG S = 2 VG S = 1 0.0
1.0
2.0
VD S
3.0 (V)
4.0
5.0
ID (m A)
VG S = 4
1.0
L inea r D ep en d en ce
VG S = 5
0 0.0
1.0
VG S
(a)ID as a function ofV D S
2.0 (V)
3.0
(b)ID as a function ofV G S (forVD S = 5 V).
Linear D ependence on VG S Digital Integrated Circuits
Devices
© Prentice Hall 1995
Sub-Threshold Conduction 10−2
ln(ID) (A)
10−4
Linear region
10−6 10−8 10−10 10−120.0
Digital Integrated Circuits
Subthreshold exponential region
VT 1.0
2.0
3.0
VGS (V)
Devices
© Prentice Hall 1995
Latchup VDD VDD +
p
n
+
+
n
+
p
p
n-well
+
+
p-source
n
Rnwell
Rpsubs
n-source p-substrate (a) Origin of latchup
Digital Integrated Circuits
Rnwell
Devices
Rpsubs
(b) Equivalent circuit
© Prentice Hall 1995
SPICE MODELS Level 1: Long Channel Equations - Very Simple Level 2: Physical Model - Includes Velocity Saturation and Threshold Variations Level 3: Semi-Emperical - Based on curve fitting to measured devices Level 4 (BSIM): Emperical - Simple and Popular
Digital Integrated Circuits
Devices
© Prentice Hall 1995
MAIN MOS SPICE PARAMETERS
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE Parameters for Parasitics
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE Transistors Parameters
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Fitting level-1 model for manual analysis Region of matching ID
Short-channel I-V curve
VGS = 5 V
Long-channel approximation VDS = 5 V
VDS
Select k’ and λ such that best matching is obtained @ Vgs= Vds = VDD
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Technology Evolution
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Bipolar Transistor E
B
p+
n+
p+ isolation
C
n+
p p+
n-epitaxy n+ buried layer p-substrate (a) Cross-sectional view. B
E
n+
p
n
C
(b) Idealized transistor structure.
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Schematic Symbols and Sign Conventions
VBC
–
C
VBC
IC
+
IC
+
+
B
IB
–
C
+
B
VCE + VBE
IB
– – E
+ VBE
IE
– – E
(a) npn
Digital Integrated Circuits
VCE
IE
(b) pnp
Devices
© Prentice Hall 1995
Operations Modes
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Forward Active Operation
Carrier Concentration
E
nb(0)
Depletion Regions
B
C
pc0 nb0
pe0
x 0
W WB
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Current Components B
E
C
1
IE 2
IC 3
x electrons
IB
holes
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Reverse Active Carrier Concentration
E
B
C
nb(W) pc0 pe0
nb0 nb(0)
x
0
W WB
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Saturation Mode Carrier Concentration nb (0)
E
B
C
nb(W)
QA
pc0
QS pe0 nb0 0
x W
WB
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Cutoff Carrier Concentration
E
B
nb (0)
pe0
nb0
C
nb (W)
pc0 x
0
W WB
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Bipolar Transistor Operation 0
15
I B=25 µA
Forward Operation
I B=50 µA
Active
I B=75 µA 10
IB =75 µA
IC(mA)
I B=100 µA IC (mA)
IB =100 µA
-0.25
IB =50 µA
5
IB =25 µA
Reverse Operation Saturation -0.5 -3.0
0 0.0
-1.0 VC E (V)
Digital Integrated Circuits
2.0 VCE (V)
Devices
© Prentice Hall 1995
A Model for Manual Analysis IB B
IB C
+ VBE
βF IB
B
C
VBE(on)
+ –
βF IB
– IB = IS(eV BE/φT – 1)
E
E
(a) Forward-active
(b) Forward-active (simplified)
IB C
B VBE(sat) + –
+ –
E
VCE(sat) IC < βFIB
(c) Forward-saturation
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Capacitive Model for Bipolar Transistor C QR
Cbc
Ccs collector-substrate junction capacitance
B QF
base charge
S
Cbe
E base-emitter junction capacitances base-collector
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Junction Capacitances
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Base Charge - Diffusion Capacitance
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Bipolar Transistors - Secondary Effects
• Early Voltage • Parasitic Resistances • Beta Variations
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Early Voltage IC
Forward Active
VBE3
Saturation VBE2
VBE1
VCE
VA
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Parasitic Resistance E
B
rE
p+
n+
C
p+
p
n+
isolation rB
n-epitaxy
rC1
p+
rC3
n+ buried layer
rC2 p-substrate
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Beta Variations ln (I) IKF IC
High Level Injection βF
Recombination
IB
VBE (linear)
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE models for Bipolar
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Main Bipolar Transistor SPICE Models
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Spice Parameters for Parasitics
Digital Integrated Circuits
Devices
© Prentice Hall 1995
SPICE Transistor Parameters
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Process Variations Devices parameters vary between runs and even on the same die! Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage. Variations in the dimensions of the devices, mainly resulting from the limited resolution of the photolithographic process. This causes (W/L) variations in MOS transistors and mismatches in the emitter areas of bipolar devices.
Digital Integrated Circuits
Devices
© Prentice Hall 1995
Impact of Device Variations 2.10 2.10 Delay (nsec)
Delay (nsec)
1.90
1.90
1.70
1.70
1.50 1.10 1.20 1.30 1.40 1.50 1.60 Leff (in mm)
1.50 –0.90
–0.80
–0.70
–0.60
–0.50
VTp (V)
Delay of Adder circuit as a function of variations in L and VT Digital Integrated Circuits
Devices
© Prentice Hall 1995
