Down Sense Amplifier for SRAM Design - CiteSeerX
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 10, OCTOBER 2008
1031
A Resilient and Power-Efficient Automatic-PowerDown Sense Amplifier for SRAM Design Ya-Chun Lai and Shi-Yu Huang
Abstract—A conventional latch-type sense amplifier in a static random access memory (SRAM) could trigger sensing failure under severe process variation. On the other hand, a traditional current-mirror sense amplifier could consume too much power. To strike a good balance, this paper presents an automatic-power-down (APD) sense amplifier, which can avoid sensing failure while keeping the power dissipation low. In this scheme, the operation window of the sense amplifier is adaptive to the real silicon speed of its associated column through Schmitt–Trigger-based dual- HL APD circuitry. A 64-kb SRAM design using the proposed technique in a 22-nm predictive technology model demonstrates that a power savings of 28%–87% over the traditional current-mirror sense amplifier is achievable. Index Terms—Automatic-power-down (APD) circuitry, sense amplifier, static random access memory (SRAM).
Fig. 1. Circuit diagram of a latch-type sense amplifier.
I. INTRODUCTION MBEDDED memory occupies an increasing percentage of the entire area of system-on-chip (SoC) circuits and therefore plays an increasingly important role on SoC designs. Embedded memory dominates not only the total area but also the power dissipation. Moreover, it could affect the yield of nanometer SoC designs. Among various types of embedded memory, static random access memory (SRAM) is widely used for SoC applications due to its highly integrated characteristic for standard CMOS logic process. Among all peripheral components of an SRAM circuit, a sense amplifier, which detects the small differential signal on a bitline pair and amplifies it to a full swing signal at data output port, plays an important role. The latch-type sense amplifier shown in Fig. 1[1], [2] is commonly used due to its advantages of low power dissipation and high speed. However, it is vulnerable to sensing failure, which is referred to as the parametric failure caused by malfunction of the sense amplifier due to insufficient sensing margin against the input offset voltage. Fig. 2 shows another voltage sense amplifier, known as current-mirror sense amplifier [3]. Unlike the latch-type sense amplifier, which could latch and amplify erroneous read data on the bitline pair when it is turned on too early, the current-mirror sense amplifier eventually amplifies correct read data once the
E
Manuscript received December 28, 2007; revised March 28, 2008 and May 3, 2008. Current version published October 15, 2008. This work was supported by National Science Council, R.O.C. (Taiwan) under Grant NSC 95-2220-E007-040 and Grant 96-2220-E-007-028. This paper was recommended by Associate Editor Y. Chiu. The authors are with the Department of Electrical Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan (e-mail: [email protected]. edu.tw; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2008.926797
Fig. 2. Circuit diagram using a current-mirror sense amplifier [3].
developed sensing margin overwhelms the input offset voltage of the sense amplifier. As a result, it can avoid the sensing failure much better. Nevertheless, such a current-mirror sense amplifier consumes more power than a typical latch-type sense amplifier due to its dc bias current. In this paper, we propose an automatic-power-down (APD) sense amplifier composed of a current-mirror sense amplifier and an APD circuitry. Unlike current-mirror sense amplifiers, the proposed APD sense amplifier not only avoids the sensing failure but also reduces the power dissipation since it can turn off the sense amplifier timely and automatically once the sense amplification is finished. Hence, the APD sense amplifier is more power-efficient than the previous current-mirror sense amplifier [3]. A similar concept has even been used in a current-mode sense amplifier as well [12]. The remainder of this paper is organized as follows. Section II presents a sensing failure analysis. Section III introduces the
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 10, OCTOBER 2008
Fig. 4. Sensing failure analysis for a latch-type sense amplifier.
the probability of sensing failure increases as well. Moreover, will incur a larger fail count due to increased larger input offset voltage of the sense amplifier. It is worth mentioning that the cell write failure will start to occur when reaches 40 mV (even when the sense amplifier does not have any input offset voltage) as shown in the diamond-marked line. Cell write failure can be mitigated by means of lowering supply voltage during write operations [6] or power-line-floating write technique [7]. III. PROPOSED APD SENSE AMPLIFIER
Fig. 3. Illustrations of sensing failure.
proposed APD sense amplifier. Section IV describes our SRAM circuit implementation. Section V shows the experimental results. Section VI concludes. II. SENSING FAILURE ANALYSIS Fig. 3 shows the simulation waveforms of a sensing operation using a current-mirror sense amplifier (Fig. 2) and a latch-type sense amplifier (Fig. 1), respectively. As shown in the figure, the current-mirror sense amplifier can function correctly under varying bitline swings, either large [Fig. 3(a)] or small [Fig. 3(b)]. By contrast, although latch-type sense amplifier can function correctly under large bitline swing [Fig. 3(c)], it could malfunction due to insufficient sensing margin against the input offset voltage [Fig. 3(d)]. As CMOS technology advances, local Vt variations of cell transistors become larger due to random dopant fluctuation [4], [5]. Therefore, the cell current distribution and sensing margin fluctuation could be much broader. In order to investigate the impact of these effects on latch-type sense amplifier in terms of sensing failure, we conduct Monte Carlo simulation. The results indicates the standard deviare shown in Fig. 4, where ation of local Vt variation of cell transistors and indicates the amount of Vt mismatch at the input transistor pair of a latch-type sense amplifier. According to the simulation results, increases, the fail count will rise. This is because when the number of bit cells with small read current increases. Thus,
Here, we first describe the circuit architecture of our APD sense amplifier and then investigate the impact of process variation. After that, we will show how we can use our dualAPD circuitry to tolerate severe process variation. A. Circuit Architecture Fig. 5 shows the circuit architecture of the APD sense amplifier composed of APD circuitry [Fig. 5(a)] and modified currentmirror sense amplifier [Fig. 5(b)]. The APD circuitry consists of Schmitt-Trigger buffers, a high-skew NAND gate, and a dynamic inverter. Among these components, the Schmitt–Trigger and buffer characterized by both low-to-high threshold is the key part because it monihigh-to-low threshold tors the output differential signal of the sense amplifier and triggers a power-down (pd) signal when certain criterion is satisfied. The triggered signal pd will then turn off the sense amplifier early, and thereby saving power dissipation. Unlike the feed-forward-controlled sense amplifier [13], which uses Schmitt Triggers to detect the input signals of the sense amplifier, our APD sense amplifier utilizes Schmitt-Trigger buffers to detect the output signals of the sense amplifier instead. Simulation waveforms associated with this APD sense amplifier are shown in Fig. 6. The signals of sense amplifier outputs (sa_out, /sa_out) are biased to a common middle voltage level before splitting up gradually. The output of the APD circuitry (i.e., the power-down signal pd) is triggered when the voltage of either one of the two sense amplifiers’ outputs decreases down . The value of is more importo a level lower than since it dictates when signal pd will be astant than that of is easy to adjust at the design stage serted. It is notable that by tuning the transistor sizes, so a circuit designer can choose a
Authorized licensed use limited to: IEEE Xplore. Downloaded on October 26, 2008 at 23:02 from IEEE Xplore. Restrictions apply.
LAI AND HUANG: RESILIENT AND POWER-EFFICIENT APD SENSE AMPLIFIER FOR SRAM DESIGN
1033
TABLE I DELAY AND POWER COMPARISON
Fig. 7. Simulation waveforms of proposed sense amplifier under (a) and (b) Vt variation imposed on APD.
010%
+10%
Fig. 5. Proposed APD sense amplifier. (a) Overall architecture. (b) Detailed circuit diagram of the sense amplifier.
though the delay increases a little due to extra output loading contributed by input capacitance of Schmitt-Trigger buffers, it can still reduce power-delay product (PDP) by 25%–89%. B. Impact of Process Variation on APD Circuitry
Fig. 6. Simulation waveforms of our APD sense amplifier.
proper to make the sense amplifier reliable and power-efficient simultaneously while considering process variation. Table I shows the comparison of delay and power between the conventional and the proposed sense amplifiers. Experimental results show that the proposed amplifier can achieve power reduction of 28%–89% depending on the operating frequency. Al-
, of the Since the high-to-low threshold, denoted as Schmitt-Trigger buffer in the APD circuitry is critical, we explore the impact of process variation on APD circuitry. According to the simulation waveforms shown in Fig. 7, positive larger and thus activating signal Vt variation will make pd earlier than the typical case. On the other hand, negative Vt smaller and slow down the activation variation will make of signal pd. The relationship between and the activation is used to indicate time of pd is shown in Fig. 8, where the activation time of pd, defined as the propagation delay from the rising edge of the wordline to the falling edge of pd. can lead to smaller so as to turn off Although higher sense amplifier earlier and save more power dissipation, the activation time of pd should be later than the transition time of data output signal (data_out) to warrant safe operation. C. Dual-
APD Circuitry
Although the APD circuitry can operate correctly under Vt variation, it could still malfunction when the Vt variation exceeds 10%. To combat such severe variation, we APD circuitry. As shown in propose a remedy called dual-
Authorized licensed use limited to: IEEE Xplore. Downloaded on October 26, 2008 at 23:02 from IEEE Xplore. Restrictions apply.
1034
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 10, OCTOBER 2008
Fig. 8. Relationship between V
and T
. Fig. 10. Block diagram of SRAM circuit using APD sense amplifier.
Fig. 9. Architecture of dual-V
APD circuitry.
Fig. 9, two pairs of Schmitt-Trigger buffers are adopted. One is while the other is deisgned with lower designed with upper . If rises due to process variation, the Schmitt-Trigger buffer pair with lower can be selected. On the contrary, if declines, the upper one can be selected. An extra external selection signal (vhl_sel) is used to choose which of the upper should be used. Consequently, the actual or the lower of this dualAPD circuitry is tunable after manufacturing to guarantee more reliable operation. Moreover, vhl_sel can be determined automatically through at-speed Built-In Self-Test (BIST) circuitry or other mechanisms during the power-on self-test (POST) stage. IV. SRAM CIRCUIT IMPLEMENTATION Fig. 10 shows the block diagram of a SRAM circuit using the proposed APD sense amplifier. According to the timing diagram shown in Fig. 11, the rising edge of signal CLK trigand the sense-enabling signal gers the selected wordline (SE). After all sense amplifiers complete the sense amplification, i.e., when the access data are passed on to data output , the APD circuitry of each sense amplifier will send out a power-down signal to the high fan-in NOR gate, which generand SE. Finally, ates a feedback reset signal (fb) to turn off the read operation ends. Such a timing control mechanism is especially suitable for an SRAM compiler since the same sense
Fig. 11. Timing diagram of SRAM circuit using APD sense amplifier.
amplifier circuitry can automatically adapt to the speed of its hosting column of varying lengths, which could range from 32 to 512 in an SRAM complier. In order to evaluate the access time and the power dissipation using our APD sense amplifier, we implemented a 64-kb SRAM macro with 256 rows and 256 columns in a 22-nm predictive technology model (PTM) [8], [9]. Moreover, we also implemented two SRAM designs with the same cell array configuration for comparison. One design uses the traditional current-mirror sense amplifier with a simple inverter chain for pulsed wordline and sensing control. The other uses the latch-type sense amplifier adopting replica cells as well as a dummy bitline for timing control [10], [11]. V. SIMULATION RESULTS Fig. 12 shows the access time of these three SRAM designs. Compared with the one using the traditional current-mirror sense amplifier, the access time of ours only increases by 3% and this result is consistent with that of Table I. Fig. 13 shows the power dissipation of three SRAM designs at different operating frequencies. Ours can significantly achieve a
Authorized licensed use limited to: IEEE Xplore. Downloaded on October 26, 2008 at 23:02 from IEEE Xplore. Restrictions apply.
LAI AND HUANG: RESILIENT AND POWER-EFFICIENT APD SENSE AMPLIFIER FOR SRAM DESIGN
1035
highly immune to sensing failure and the power dissipation is moderate among these three SRAM designs. VI. CONCLUSION
Fig. 12. Access time of three SRAM designs.
With the increase of the process variation, the operating speed could be significantly different from one column to another in an SRAM design. The traditional latch-type sense amplifier plus replica-based timing-tracking scheme may fall victim to sensing failure. In this paper, we have proposed an APD sense amplifier, which can avoid sensing failure even under severe process variation. Compared with the traditional current-mirror sense am-based APD sense amplifier can achieve plifier, this dualpower reduction of 28%–89% when operated in the frequency range from 100 MHz to 1 GHz. A 64-kb SRAM circuit using such a sense amplifier in a 22-nm PTM indicates power reduction of 87% at 125 MHz and 28% at 1 GHz. REFERENCES
Fig. 13. Power dissipation versus operating frequency.
TABLE II COMPARISONS OF THREE SRAM DESIGNS
power saving of 28%–87% as compared with the one using the traditional current-mirror sense amplifier. Finally, Table II summarizes some comparisons of three SRAM designs in terms of power, access time, silicon area cost of the sense amplifier, sensitivity of sensing failure, and pulsed wordline control mechanism. Though power dissipation of the SRAM design using latch-type sense amplifier is the smallest, it is sensitive to sensing failure. By contrast, our proposal is
[1] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A currentcontrolled latch sense amplifier and a static power-saving input buffer for low-power architecture,” IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523–527, Apr. 1993. [2] B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148–1158, Jul. 2004. [3] H. Nambu, K. Kanetani, K. Yamasaki, K. Higeta, M. Usami, Y. Fujimura, K. Ando, T. Kusunoki, K. Yamaguchi, and N. Homma, “A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM,” IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1650–1658, Nov. 1998. [4] R. Venkatraman, R. Castagnetti, and S. Ramesh, “The statistics of device variations and its impact on SRAM bitcell performance, leakage and stability,” in Proc. 7th Int. Symp. Quality Electronic Design (ISQED’06), Mar. 2006, pp. 178–183. [5] B. Cheng, S. Roy, and A. Asenov, “The impact of random doping effects on CMOS SRAM cell,” in Proc. 30th Eur. Solid-State Circuits Conf. (ESSCIRC 2004), Sep. 2004, pp. 219–222. [6] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 146–151, Jan. 2006. [7] M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, “90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 705–711, Mar. 2006. [8] Predictive Technology Model (PTM) [Online]. Available: http://www. eas.asu.edu/~ptm [9] W. Zhao and Y. Cao, “New generation of predictive technology model for sub-45 nm design exploration,” in Proc. Int. Symp. Quality Electronic Design, Mar. 2006, pp. 585–590. [10] B. S. Amrutur and M. A. Horowitz, “A replica technique for wordline and sense control in low-power SRAM’s,” IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1208–1219, Aug. 1998. [11] K. Osada, J. L. Shin, M. Khan, Y. Liou, K. Wang, K. Shoji, K. Kuroda, S. Ikeda, and K. Ishibashi, “Universal-Vdd 0.65–2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1738–1744, Nov. 2001. [12] B. Wicht, J.-Y. Larguier, and D. Schmitt-Landsiedel, “A 1.5V 1.7ns 4k x 32 SRAM with a fully-differential auto-power-down current sense amplifier,” in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 462–508. [13] H. Nguyen, “Feedforward-Controlled Sense Amplifier,” U.S. Patent 6300816, Oct. 9, 2001.
Authorized licensed use limited to: IEEE Xplore. Downloaded on October 26, 2008 at 23:02 from IEEE Xplore. Restrictions apply.
1031
A Resilient and Power-Efficient Automatic-PowerDown Sense Amplifier for SRAM Design Ya-Chun Lai and Shi-Yu Huang
Abstract—A conventional latch-type sense amplifier in a static random access memory (SRAM) could trigger sensing failure under severe process variation. On the other hand, a traditional current-mirror sense amplifier could consume too much power. To strike a good balance, this paper presents an automatic-power-down (APD) sense amplifier, which can avoid sensing failure while keeping the power dissipation low. In this scheme, the operation window of the sense amplifier is adaptive to the real silicon speed of its associated column through Schmitt–Trigger-based dual- HL APD circuitry. A 64-kb SRAM design using the proposed technique in a 22-nm predictive technology model demonstrates that a power savings of 28%–87% over the traditional current-mirror sense amplifier is achievable. Index Terms—Automatic-power-down (APD) circuitry, sense amplifier, static random access memory (SRAM).
Fig. 1. Circuit diagram of a latch-type sense amplifier.
I. INTRODUCTION MBEDDED memory occupies an increasing percentage of the entire area of system-on-chip (SoC) circuits and therefore plays an increasingly important role on SoC designs. Embedded memory dominates not only the total area but also the power dissipation. Moreover, it could affect the yield of nanometer SoC designs. Among various types of embedded memory, static random access memory (SRAM) is widely used for SoC applications due to its highly integrated characteristic for standard CMOS logic process. Among all peripheral components of an SRAM circuit, a sense amplifier, which detects the small differential signal on a bitline pair and amplifies it to a full swing signal at data output port, plays an important role. The latch-type sense amplifier shown in Fig. 1[1], [2] is commonly used due to its advantages of low power dissipation and high speed. However, it is vulnerable to sensing failure, which is referred to as the parametric failure caused by malfunction of the sense amplifier due to insufficient sensing margin against the input offset voltage. Fig. 2 shows another voltage sense amplifier, known as current-mirror sense amplifier [3]. Unlike the latch-type sense amplifier, which could latch and amplify erroneous read data on the bitline pair when it is turned on too early, the current-mirror sense amplifier eventually amplifies correct read data once the
E
Manuscript received December 28, 2007; revised March 28, 2008 and May 3, 2008. Current version published October 15, 2008. This work was supported by National Science Council, R.O.C. (Taiwan) under Grant NSC 95-2220-E007-040 and Grant 96-2220-E-007-028. This paper was recommended by Associate Editor Y. Chiu. The authors are with the Department of Electrical Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan (e-mail: [email protected]. edu.tw; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2008.926797
Fig. 2. Circuit diagram using a current-mirror sense amplifier [3].
developed sensing margin overwhelms the input offset voltage of the sense amplifier. As a result, it can avoid the sensing failure much better. Nevertheless, such a current-mirror sense amplifier consumes more power than a typical latch-type sense amplifier due to its dc bias current. In this paper, we propose an automatic-power-down (APD) sense amplifier composed of a current-mirror sense amplifier and an APD circuitry. Unlike current-mirror sense amplifiers, the proposed APD sense amplifier not only avoids the sensing failure but also reduces the power dissipation since it can turn off the sense amplifier timely and automatically once the sense amplification is finished. Hence, the APD sense amplifier is more power-efficient than the previous current-mirror sense amplifier [3]. A similar concept has even been used in a current-mode sense amplifier as well [12]. The remainder of this paper is organized as follows. Section II presents a sensing failure analysis. Section III introduces the
1549-7747/$25.00 © 2008 IEEE Authorized licensed use limited to: IEEE Xplore. Downloaded on October 26, 2008 at 23:02 from IEEE Xplore. Restrictions apply.
1032
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 10, OCTOBER 2008
Fig. 4. Sensing failure analysis for a latch-type sense amplifier.
the probability of sensing failure increases as well. Moreover, will incur a larger fail count due to increased larger input offset voltage of the sense amplifier. It is worth mentioning that the cell write failure will start to occur when reaches 40 mV (even when the sense amplifier does not have any input offset voltage) as shown in the diamond-marked line. Cell write failure can be mitigated by means of lowering supply voltage during write operations [6] or power-line-floating write technique [7]. III. PROPOSED APD SENSE AMPLIFIER
Fig. 3. Illustrations of sensing failure.
proposed APD sense amplifier. Section IV describes our SRAM circuit implementation. Section V shows the experimental results. Section VI concludes. II. SENSING FAILURE ANALYSIS Fig. 3 shows the simulation waveforms of a sensing operation using a current-mirror sense amplifier (Fig. 2) and a latch-type sense amplifier (Fig. 1), respectively. As shown in the figure, the current-mirror sense amplifier can function correctly under varying bitline swings, either large [Fig. 3(a)] or small [Fig. 3(b)]. By contrast, although latch-type sense amplifier can function correctly under large bitline swing [Fig. 3(c)], it could malfunction due to insufficient sensing margin against the input offset voltage [Fig. 3(d)]. As CMOS technology advances, local Vt variations of cell transistors become larger due to random dopant fluctuation [4], [5]. Therefore, the cell current distribution and sensing margin fluctuation could be much broader. In order to investigate the impact of these effects on latch-type sense amplifier in terms of sensing failure, we conduct Monte Carlo simulation. The results indicates the standard deviare shown in Fig. 4, where ation of local Vt variation of cell transistors and indicates the amount of Vt mismatch at the input transistor pair of a latch-type sense amplifier. According to the simulation results, increases, the fail count will rise. This is because when the number of bit cells with small read current increases. Thus,
Here, we first describe the circuit architecture of our APD sense amplifier and then investigate the impact of process variation. After that, we will show how we can use our dualAPD circuitry to tolerate severe process variation. A. Circuit Architecture Fig. 5 shows the circuit architecture of the APD sense amplifier composed of APD circuitry [Fig. 5(a)] and modified currentmirror sense amplifier [Fig. 5(b)]. The APD circuitry consists of Schmitt-Trigger buffers, a high-skew NAND gate, and a dynamic inverter. Among these components, the Schmitt–Trigger and buffer characterized by both low-to-high threshold is the key part because it monihigh-to-low threshold tors the output differential signal of the sense amplifier and triggers a power-down (pd) signal when certain criterion is satisfied. The triggered signal pd will then turn off the sense amplifier early, and thereby saving power dissipation. Unlike the feed-forward-controlled sense amplifier [13], which uses Schmitt Triggers to detect the input signals of the sense amplifier, our APD sense amplifier utilizes Schmitt-Trigger buffers to detect the output signals of the sense amplifier instead. Simulation waveforms associated with this APD sense amplifier are shown in Fig. 6. The signals of sense amplifier outputs (sa_out, /sa_out) are biased to a common middle voltage level before splitting up gradually. The output of the APD circuitry (i.e., the power-down signal pd) is triggered when the voltage of either one of the two sense amplifiers’ outputs decreases down . The value of is more importo a level lower than since it dictates when signal pd will be astant than that of is easy to adjust at the design stage serted. It is notable that by tuning the transistor sizes, so a circuit designer can choose a
Authorized licensed use limited to: IEEE Xplore. Downloaded on October 26, 2008 at 23:02 from IEEE Xplore. Restrictions apply.
LAI AND HUANG: RESILIENT AND POWER-EFFICIENT APD SENSE AMPLIFIER FOR SRAM DESIGN
1033
TABLE I DELAY AND POWER COMPARISON
Fig. 7. Simulation waveforms of proposed sense amplifier under (a) and (b) Vt variation imposed on APD.
010%
+10%
Fig. 5. Proposed APD sense amplifier. (a) Overall architecture. (b) Detailed circuit diagram of the sense amplifier.
though the delay increases a little due to extra output loading contributed by input capacitance of Schmitt-Trigger buffers, it can still reduce power-delay product (PDP) by 25%–89%. B. Impact of Process Variation on APD Circuitry
Fig. 6. Simulation waveforms of our APD sense amplifier.
proper to make the sense amplifier reliable and power-efficient simultaneously while considering process variation. Table I shows the comparison of delay and power between the conventional and the proposed sense amplifiers. Experimental results show that the proposed amplifier can achieve power reduction of 28%–89% depending on the operating frequency. Al-
, of the Since the high-to-low threshold, denoted as Schmitt-Trigger buffer in the APD circuitry is critical, we explore the impact of process variation on APD circuitry. According to the simulation waveforms shown in Fig. 7, positive larger and thus activating signal Vt variation will make pd earlier than the typical case. On the other hand, negative Vt smaller and slow down the activation variation will make of signal pd. The relationship between and the activation is used to indicate time of pd is shown in Fig. 8, where the activation time of pd, defined as the propagation delay from the rising edge of the wordline to the falling edge of pd. can lead to smaller so as to turn off Although higher sense amplifier earlier and save more power dissipation, the activation time of pd should be later than the transition time of data output signal (data_out) to warrant safe operation. C. Dual-
APD Circuitry
Although the APD circuitry can operate correctly under Vt variation, it could still malfunction when the Vt variation exceeds 10%. To combat such severe variation, we APD circuitry. As shown in propose a remedy called dual-
Authorized licensed use limited to: IEEE Xplore. Downloaded on October 26, 2008 at 23:02 from IEEE Xplore. Restrictions apply.
1034
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 55, NO. 10, OCTOBER 2008
Fig. 8. Relationship between V
and T
. Fig. 10. Block diagram of SRAM circuit using APD sense amplifier.
Fig. 9. Architecture of dual-V
APD circuitry.
Fig. 9, two pairs of Schmitt-Trigger buffers are adopted. One is while the other is deisgned with lower designed with upper . If rises due to process variation, the Schmitt-Trigger buffer pair with lower can be selected. On the contrary, if declines, the upper one can be selected. An extra external selection signal (vhl_sel) is used to choose which of the upper should be used. Consequently, the actual or the lower of this dualAPD circuitry is tunable after manufacturing to guarantee more reliable operation. Moreover, vhl_sel can be determined automatically through at-speed Built-In Self-Test (BIST) circuitry or other mechanisms during the power-on self-test (POST) stage. IV. SRAM CIRCUIT IMPLEMENTATION Fig. 10 shows the block diagram of a SRAM circuit using the proposed APD sense amplifier. According to the timing diagram shown in Fig. 11, the rising edge of signal CLK trigand the sense-enabling signal gers the selected wordline (SE). After all sense amplifiers complete the sense amplification, i.e., when the access data are passed on to data output , the APD circuitry of each sense amplifier will send out a power-down signal to the high fan-in NOR gate, which generand SE. Finally, ates a feedback reset signal (fb) to turn off the read operation ends. Such a timing control mechanism is especially suitable for an SRAM compiler since the same sense
Fig. 11. Timing diagram of SRAM circuit using APD sense amplifier.
amplifier circuitry can automatically adapt to the speed of its hosting column of varying lengths, which could range from 32 to 512 in an SRAM complier. In order to evaluate the access time and the power dissipation using our APD sense amplifier, we implemented a 64-kb SRAM macro with 256 rows and 256 columns in a 22-nm predictive technology model (PTM) [8], [9]. Moreover, we also implemented two SRAM designs with the same cell array configuration for comparison. One design uses the traditional current-mirror sense amplifier with a simple inverter chain for pulsed wordline and sensing control. The other uses the latch-type sense amplifier adopting replica cells as well as a dummy bitline for timing control [10], [11]. V. SIMULATION RESULTS Fig. 12 shows the access time of these three SRAM designs. Compared with the one using the traditional current-mirror sense amplifier, the access time of ours only increases by 3% and this result is consistent with that of Table I. Fig. 13 shows the power dissipation of three SRAM designs at different operating frequencies. Ours can significantly achieve a
Authorized licensed use limited to: IEEE Xplore. Downloaded on October 26, 2008 at 23:02 from IEEE Xplore. Restrictions apply.
LAI AND HUANG: RESILIENT AND POWER-EFFICIENT APD SENSE AMPLIFIER FOR SRAM DESIGN
1035
highly immune to sensing failure and the power dissipation is moderate among these three SRAM designs. VI. CONCLUSION
Fig. 12. Access time of three SRAM designs.
With the increase of the process variation, the operating speed could be significantly different from one column to another in an SRAM design. The traditional latch-type sense amplifier plus replica-based timing-tracking scheme may fall victim to sensing failure. In this paper, we have proposed an APD sense amplifier, which can avoid sensing failure even under severe process variation. Compared with the traditional current-mirror sense am-based APD sense amplifier can achieve plifier, this dualpower reduction of 28%–89% when operated in the frequency range from 100 MHz to 1 GHz. A 64-kb SRAM circuit using such a sense amplifier in a 22-nm PTM indicates power reduction of 87% at 125 MHz and 28% at 1 GHz. REFERENCES
Fig. 13. Power dissipation versus operating frequency.
TABLE II COMPARISONS OF THREE SRAM DESIGNS
power saving of 28%–87% as compared with the one using the traditional current-mirror sense amplifier. Finally, Table II summarizes some comparisons of three SRAM designs in terms of power, access time, silicon area cost of the sense amplifier, sensitivity of sensing failure, and pulsed wordline control mechanism. Though power dissipation of the SRAM design using latch-type sense amplifier is the smallest, it is sensitive to sensing failure. By contrast, our proposal is
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