VDD Option A Option B Option C Pin 1 open or VIH Pin 1 = VIL at Crossing point 20% VDD to 80% level VOL VOH 100Ω (Out-Outn)
Frequency Stability * Input Current Stand-by Current Output Symmetry Rise and Fall Times "0" level "1" level Output Load Differential output voltage Offset voltage Disable delay time Enable/Startup time RMS Jitter Aging (first year)