Effective Selection of Favorable Gates in BTI ... - Semantic Scholar
Effective Selection of Favorable Gates in BTI-Critical Paths to Enhance Circuit Reliability Andres Gomez, Victor Champac Dept. of Electronic Engineering National Institute for Astrophysics, Optics and Electronics (INAOE), Mexico Abstract—Bias Temperature Instability (BTI) has become a major issue for circuit reliability in deeply scaled CMOS technologies. Due to BTI, circuit delay increases as time progress, which may lead to a timing constraint violation. This paper proposes an efficient metric to select the most favorable gates to be resized to enhance circuit reliability. A close analysis is devoted to the main aspects allowing to identify the most favorable gates to be resized. The metric introduces a composited point of view of gate delay sensitivity to channel width sizing, which reflects the sizing impact on the initial gate delay and gate delay degradation. Other parameters are also considered to improve the metric effectiveness. The proposed metric has been applied in some ISCAS85 benchmark circuits along with an iterative gate-selection and gate-sizing procedure. The results show that our proposal is suitable to achieve higher product reliability with minimum area overhead.
I. I NTRODUCTION Reliability has become a major concern in deeply scaled CMOS technologies [1]. Design of reliable circuits that can operate correctly during a long period of time (i.e 10 years), even in extreme conditions, has become a very difficult challenge for safety critical applications. Bias Temperature Instability (BTI) has been shown to have significant impact in reliability of digital circuits [2], moreover, its effect is aggravated in new technology nodes due to high electric fields and elevated temperatures that devices experience [3]. BTI gradually increases transistors threshold voltage (V th) in the run-time, which is reflected in a continuous increment of circuit delay. If delay increases significantly, circuit correct functionality can not be assured. Ever greater guardbands are added to timing constraints to tolerate delay degradation, however, this penalizes performance. Hence, designers are forced to develop strategies to design circuits with enhanced reliability. In such way, circuit lifetime can be extended or required guardbands can be reduced as is shown in Figure 1. Several design techniques has been explored in the field of reliable circuits design. In [4] the authors proposed to use an Aging-aware standard cell library. Technology-mapping is performed to replace original gates by their robust counterpart. Although this technique can improve lifetime significantly, design and characterization of the cell library can be complex because it depends on specific workload conditions. Other design approaches are based in the formulation of a numerical optimization problem, which finds gates sizes that minimize circuit area while meeting the delay constraint [5][6][7]. However, these approaches require to identify the
-2
Figure 1. Delay degradation as function of time for a Reliability Enhanced Design and a non-Reliability Enhanced Design.
critical paths and gates within the circuit to be applied. Otherwise, they would result in area and power overhead. Design of reliable circuits requires more detailed guidance, such that designers can conduct effective reliability enhancement. Approaches in [8] and [9] use metrics to quantitatively estimate how much favorable is to take actions on a gate (i.e. to increase its size) to enhance circuit reliability. Although the metric in [8] allows to identify gates that suffer several delay degradation, it is not focused to any specific reliability-aware technique. For example, if gate sizing is going to be applied, delay sensitivity to channel width should be included in the metric. In [9] critical gates are identified by partitioning circuit delay constraint into gates delays constraints. Then, gates are ranked by applying a metric very similar to [8]. However, partitioning scheme does not consider that assigned constraint to each gate should consider specific gates workload. Previous works have only considered the BTI phenomenon in PMOS devices (NBTI), however, BTI in NMOS (PBTI) is an emerging reliability concern for subnanometer technologies with high-k dielectric materials, which should be considered in the design process. Furthermore, selection metrics should be formulated differently depending on the design technique to be applied to the circuit to provide better design guidelines. This paper proposes an efficient metric to select from BTIcritical paths, the most favorables gates that once oversized produce a greater benefit to circuit reliability. Parameters like gate delay sensitivity, gate sizing impact on circuit area, gate criticality and aged paths slack time are combined in the proposed metric to make it complete and accurate. Unlike other works, here gate delay sensitivity is considered to has two components corresponding to the sizing impact on the initial delay and the sizing impact on delay degradation. The
proposed metric was applied to some ISCAS85 benchmark circuits. The results show that our proposal provides adequate design guidance to achieve the required timing constraint along overall expected lifetime, and hence leading to higher product reliability, with low area overhead. The rest of this paper is organized as follows: In section II it is briefly reviewed how to compute gate delay degradation. In section III it is given a detailed explanation of the proposed metric formulation. In section IV, the overall reliability optimization procedure used in our work is exposed. In section V some results of the metric application to some ISCAS85 benchmark circuits to enhance circuit reliability are discused. Finally, conclusions and future work are given in section VI.
function of its gate terminal SP (SPB ), because its stress condition also depends on the status of the upper transistor in the series connection due to the stacking effect [12]. For M 2 transistor to be under NBTI stress condition, its gate has to be at logic zero and also M 1 has to be turned-on. Thus, TSP of transistor M 2 is equal to the probability of signals A and B being at logic zero simultaneously (See Figure 2). Finally, TSP of each NMOS device in the NOR2 gate is equal to its input signal probabilities. A similar analysis can be performed in other gate structures to obtain the TSP of each transistor.
II. D ELAY D EGRADATION M ODELING Delay degradation modeling is of great interest for designing reliable circuits. This section briefly reviews how circuit delay degradation can be estimated. A. Transistor Aging due to BTI Vth degradation due to BTI occurs during normal transistor operation at specific stress conditions: positive gate bias for NMOS (PBTI) and negative gate bias for PMOS (NBTI) transistors. In previous technology nodes, PBTI effect was negligible in comparison to NBTI. However, since the introduction of high-k metal-gate technologies, PBTI has also become a reliability concern [10]. V th degradation along the time depends on technology parameters, supply voltage, temperature and the average time the device is under the stress condition, which is usally expressed in terms of Transistor Stress Probability TSP. A simplified model of V th increment due to BTI (∆V thBT I ) is proposed in [11], ∆V thBT I = A · T SP n · tn
(1)
where A is a fitting constant that depends on technology node, temperature and Supply voltage, t is the aged time, and n is a constant with the value of 1/6. TSP can be seen as the probability of a transistor to be under the stress bias condition, and it depends on the signal probabilities of circuit inputs (workload pattern) and transistor position in the gate. In this work, it is assumed, without loss of generality, that both NBTI and PBTI mechanisms induce the same ∆V thBT I = 80mv at worst case stress conditions (T SP = 1). The constant A is fitted according to these assumptions. B. Transistor Stress Probability Computation TSP of each device in a gate can be computed based on signal probability at gate input nodes. Signal probability is usually defined as the probability of a node to be at high value (logic 1). Figure 2 shows an example to illustrate TSP computation of devices in a NOR2 gate. Let us to assume that inputs A and B have Signal Probabilities (SP) of 0.5 and 0.8, respectively. TSP of transistor M 1 is equal to the probability of signal A to be at logic zero, because this is the only condition required for M 1 to be negatively biased (stress condition). However, the TSP of transistor M 2 is not only a
Figure 2.
Stress probability computation for devices in a N OR2 gate.
In this work, the signal probabilities at gates inputs are obtained by Logic Simulation. A large number of randomly generated input vectors are applied to the circuit and it is counted how many times each internal node is settled at high logic level. Each node signal probability can be approximated as the ratio of the number of times the node was at high logic level to the total number of generated vectors. C. Aging-aware linear gate delay model The aged gate delay (Dage ) can be computed once the V th shift of each transistor is known. Assuming that the amount of V th degradation is small enough, a first order Taylor approximation at the nominal transistor parameter values can be used to obtain a gate delay expression as a linear function of V th shift of each transistor of the gate [13]. Dage = Dn +
X m∈Gate
∂Dn · ∆V thm ∂V thm
(2)
where Dn is the nominal (initial) gate delay, m is the set of transistors that belong to the gate and ∂V∂Dthnm is the gate delay sensitivitiy to V th shifts of transistor m. The sensitivity values are obtained during gate library characterization by polynomial fitting. Based on Equation 2, total aged delay can be expressed as the sum of nominal gate delay and gate delay degradation due to BTI, Dage = Dn + ∆D. Aged delay of a path can be obtained by adding all gates delays across it. If a path delay becomes larger than the clock period, the signal propagated by the path would reach memory elements, located at the end of the path, after the clock edge. Consequently, an incorrect logic value would be stored. III. M ETRIC F ORMULATION TO G UIDE S IZING TO E NHANCE R ELIABILITY Among all the gates in a circuit, there are some that once oversized result in a greater benefit to Circuit Reliability.
delay sensitivity can be underestimated, and as consequence, the most sensitive gates would not be selected to be resized.
The first parameter taken into account in the metric is delay sensitivity to channel width sizing. Selecting a gate with a greater sensitivity value results in greater delay reduction than selecting a gate with a lower sensitivity. When channel width of transistors that belong to a gate are resized, gate delay behavior over time is modified. Figure 3 shows the initial (nominal) delay and the gate delay degradation for rising output transition of a N OR2 gate as function of their PMOS transistors channel widths. Two effects can be observed: First, nominal delay reduces as the transistors channel widths increase because transistors current capability to charge (or discharge) capacitive loads is increased. Second, the gate delay degradation reduces as the transistors channel widths increase because gate delay sensitivity to V th shift due to BTI is reduced. Therefore, delay sensitivity to channel width sizing should be considered as a composite term of two components (See Equation 3): a) one corresponding to the sizing impact on initial gate delay, and b) a second corresponding to the sizing impact on gate delay degradation. (3)
60
12
50
11
-2
40
10
30
9
20
8 250
300
350
400
Channel Width (nm)
D (ps)
Dn (ps)
Dage Dn ∆D Sw = Sw + Sw
450
Figure 3. Nominal delay and Delay degradation for the rising transition of a N OR2 gate as function of PMOS channel width (T SP = 1, time = 10 years).
The two delay sensitivities can be obtained by the derivative of Equation 2 with respect to channel width. Figure 4 shows Dn ∆D the two delay sensitivities (Sw , Sw ) and the total gate Dage delay sensitivity (Sw ) as function of time (up to 10 years Dn or 120 months)for a N OR2 gate. It can be observed that Sw remains constant because it does not depends on the degra∆D dation that transistors experience. However, Sw becomes greater as devices ages due to BTI along time. The amount ∆D of Sw can be up to 15% of nominal sensitivity depending on gate structure, nominal gate size, input transition time, fan-out, and devices threshold voltage degradation. Thus, if this sensitivity component is not considered, the overall gate
Sensitivity (s/nm)
A. Gate Delay Sensitivity to Channel Width Sizing
x 10
-5
x 10 0
-3.9
Sw
-4
Sw
-4.1
Sw
Dn Dage
-1 -2
D
-4.2 -4.3 -4.4 0
20
-3 -4
-2
-6
Sensitivity (s/nm)
-3.8
-5
n
In this section, an efficient metric to identify those gates most favorable to be resized is developed. A close analysis is devoted to the main parameters allowing to identify the most favorable gates to be resized.
40 60 80 time (months)
100
-6 120
Figure 4. Delay Sensitivity components as function of time for the rising transition of a N OR2 gate (T SP = 1).
B. Gate Sizing Impact on Circuit Area Circuit area is a very important constraint in the design of digital circuits because it is proportional to power consumption and it affects the cost of a product. It is desirable to design circuits meeting delay and lifetime constraints at the cost of minimum area overhead. Therefore, it is important to consider the area cost of sizing-up a gate, in conjunction with its delay sensitivity to channel width. The total gate delay sensitivities and gate area of an INV and NOR2 gates as function of its transistors channel width are shown in Figures 5-a and 5-b, respectively. For similar delay sensitivities, i.e. W pmos = 200nm for INV gate and W pmos = 300nm for NOR2 gate, the area cost of the NOR2 gate is greater than for the INV gate. Based on this observation, in the proposed metric the gate delay sensitivities are normalized with respect to the gate area impact (ai ), which is a layout dependent parameter but can be estimated for a pre-designed gate Dage /ai ), library. By normalizing gate delays sensitivities (Sw the metric considers the gate delay reduction per unit increase in circuit area. C. Gate Criticality and Paths Slack Time Gate criticality: it can be considered as the number of critical paths passing across a gate [8]. Critical paths of a circuit, are those paths that do not met the timing constraint. Let us consider a circuit with two critical paths P 1 and P 2 (See Figure 6). If we resize a non-shared gate in one path (e.g. gate G1), it would be required to resize a gate in the other path. In this case two gates would be resized to meet timing constraint. However, if a shared gate (e.g G4 or G5) is resized, only one gate impacts the area cost. Usually, shared gates present higher criticality. Aged Path Slack Time: The aged delay of a critical path depends on its number of gates and their rate of degradation [11]. The amount of path delay degradation and its number of gates determine the severity of a path to violate the timing constraint. Therefore, we use aged path slack time to take
-4
paths, with high sensitivities (a greater fan-out, more degraded devices, etc.) would have a high metric value. Furthermore, the value given by the metric reduces for gates with high fan-in because they introduce a greater area overhead.
INV NOR2
-2
Sens
-3 -4 100
200
300 400 500 Wpmos (nm)
600
Sens+area+Crit
Sens+area+Crit+Slack
0.5 INV NOR2
0.6
-2 0.3
Figure 7. considered.
-2
0.2 0
2
0.4
0.8
-4.1 0.4
(a) Delay sensitivity as function of PMOS channel width.
Area ( m )
Sens+area
1
Normalized-Metric
(s/nm)
-1
Sw
Dage
x 10
n
0
0
1
2
3
Gate Label
4
5
Behavior of metric value when including each parameter
0.2 0.1 100
200
300 400 500 Wpmos (nm)
600
(b) Gate area as function of PMOS channel width. Figure 5. INV and NOR2 gates delays sensitivities and areas as function of PMOS transistors channel width for the rising transition at output. T SP = 0.5, time = 10 years.
Figure 6. Circuit example to illustrate gate criticality and slack time importance.
into account these effects. Aged path slack time (slackaged ) is defined as the difference between aged path delay and the delay constraint (See Equation 4). Then, its value is positive for critical paths and negative for non-critical paths. slackaged = Dage,pk − Dcons
(4)
D. Proposed Metric The proposed metric to select the most favorable gates to be up-sized is given in Equation 5. M etrici =
X (S Dn + S ∆D ) · slackaged,k Wi Wi ai
Figure 7 illustrates the impact of each parameter discussed above on the metric behavior of the gates in the circuit of Figure 6. Metric values are normalized with respect to the maximum obtained at each case. For the case when only sensitivity is considered (sens), the gates have metrics values of the same order. Some differences occur depending on the activated network, capacitive load and input slew rate at each gate. For the case when the gate impact on area due to sizing is included in the metric (sens+area), normalized metric values for inverter gates remains almost the same. However, NAND2 gate (G4) metric value decreases because increasing size of this gate requires more area. If gate criticality is now considered (sens+area+Crit), gates G4 and G5 becomes more important than the others because both critical paths P1 and P2 pass across them. Finally, including aged paths slack time (sens+area+crit+slack) significantly reduces G3 normalized metric value because it only belongs to the least critical path P 2 while importance of inverters G0 − G2 increase because they belongs to the most critical path P 1. For this example, inverter gate G1 is the most favorable gate to be resized. Although gates G4 and G5 impact on two paths, the slack time of one of them is very small (path G3-G4-G5 is not very critical). However, gate G1 has a greater sensitiviy and belongs to the most critical path. Thus, G1 achieves a greater metric value.
(5)
∀k∈CP
where the summation considers the gate criticality. From Equation 5, it is expected that gates in the most critical
IV. S IZING F RAMEWORK FOR R ELIABILITY E NHANCEMENT The proposed metric has been incorporated in the sizing framework for reliability enhancement shown in Figure 8. The sizing framework is as follows: Starting from a circuit designed with a standard gate library, logic simulation is performed to obtain internal nodes signal probabilities and transistors TSP. Next, the linear gate delay degradation model is used to perform a BTI-Aware Path-Based Static Timing
Table I A PPLICATION TO ISCAS B ENCHMARK C IRCUITS R ESULTS
CP
CG
5 years OG OD(%)
AO(%)
CP
CG
10 years OG OD(%)
175
12103
107
30
12.56
4.72
15872
111
31
13.47
9440
220
3532
173
5.82
48
13.26
4.90
4212
187
44
14.61
C880
4935
254
174
5.91
62
18
11.83
1.39
219
63
19
13.08
C1908
15638
253
1.76
1747
144
34
14.14
1.99
2176
148
47
15.77
C2670
3381
2.65
419
138
78
26
12.03
0.88
187
79
29
13.20
C5315
1.08
24662
1224
432
253
32
13.76
0.33
594
298
37
15.21
C7552
0.41
43174
1450
418
252
16
11.43
0.06
579
267
18
12.37
0.08
Circuit
Num.Paths
Num.Gates
C432
82364
C499
AO(%)
CP=Critical Paths, CG=Critical Gates, OG=Optimized Gates, OD=Optimized Delay, AO=Area Overhead.
V. A PPLICATION TO ISCAS B ENCHMARK C IRCUITS
-4.1
n
-2
Figure 8.
Sizing Framework for Realiability Enhancement.
Analysis (STA), which allows to obtain aged delay information of each path. The set of all circuit paths is reduced to a critical path set composed only by those paths that do not meet the required delay constraint for the expected lifetime (i.e. 5 or 10 years). Here, the delay constraint is assumed to be the initial (without aging) circuit delay that is the maximum initial delay within overall paths. Once the set of critical paths is obtained, the proposed critical gate selection metric is evaluated for each gate belonging to the critical path set. The metric is separately evaluated for the pull-up and pull-down network of each gate because they can impact differently on circuit delay. Then, gates are ranked from the highest to the lowest value of the metric and an user-defined number N of gates with the highest metric value are selected to be resized by a small step size increment. In order to reduce area overhead, only the specific selected network on each gate is resized. This is done because a gate can be severely affected by NBTI in PMOS while it is not greatly affected by PBTI in NMOS. The above process is iteratively repeated several times until the delay constraint is met. Once some gates are resized, a non-critical path could now become critical due to loading effects. Also a critical path can now become non-critical because its timing behavior has been improved. Therefore, the set of critical paths is updated at each iteration. Note that the proposed flow require to perform STA each time that selected gates are resized. Thus, to avoid runtime issues the number of critical gates selected at each iteration can be modified according to circuit size, also step size increment of selected gates can be changed.
Table I summarizes the results obtained applying the proposed metric to some ISCAS benchmark circuits. Information about, critical paths (CP), critical gates (CG), Optimized Gates (OG), Optimized Delay (OD) and Area Overhead (AO) are provided for two different lifetime intervals (5 years and 10 years). Here, the timing constraint was settled at the nominal (without aging) circuit delay. Using the proposed metric, up to ten gates are selected at each iteration (N = 10). As can be seen, the number of optimized gates to achieve the required delay constraint is small compared to the overall critical gates set. This indicates that not all gates in critical paths provide as delay improvement as this small gates set. Therefore, the proposed metric gives good design guidelines since delay constraint can be met by focusing optimization only on these gates. It can be seen from table I that optimized delay is around within 11% to 16% depending on the circuit and its expected lifetime (5 years or 10 years). These optimization values correspond to the delay degradation of the initial circuit design since delay constraint was settled as the initial circuit delay. Therefore, the results correspond to the case where guardband is reduced by 100% (see Figure 1) for all circuits. Lower area overhead would be obtained if some small guardband is allowed to tolerate BTI induced delay degradation. Table I also shows that as degradation time increases, more circuit paths can become critical due to BTI effects because lifetime constraint is more stringent. However, these extra critical paths can be considered in the reliability enhancement framework with a low increase in area overhead. In other words, circuits lifetime can be extended from 5 years to 10 years at the cost of very low additional area overhead (i.e from 4.72% to 5.82% for C432 circuit ). Figure 9 shows delay reduction of circuit C1908 at each iteration for two different metrics used in the sizing framework for comparison purposes. Blue curve corresponds to the metric used in this work while red curve corresponds to the metric used in [8], which takes into account criticality and delay degradation, but slack time or sensitivity are not considered. The proposed metric performs much better since it requires less iterations to achieve the same delay constraint. Figure 10 shows a comparison between area overhead obtained using the metric in [8] and the metric proposed here. For all circuits
Prop.dMetric Metricdofd[8]
1.15 1.1 1.05 -4.1 1 0.95 0
-2
Spec.
n
NormalizeddDelay
1.2
20
40 60 80 100 120 Iteration
Figure 9. Delay Reduction at each iteration for C1908 ISCAS circuit. Two different metrics were used in the sizing framework: the proposed metric (Blue curve) and the metric in [8] (Red curve).
the proposed metric reduces significantly the area overhead in comparison to the metric in [8]. These results makes evident that gate selection metrics should be developed according to the design technique that would be applied to the circuit. In our case, including delay sensitivity to channel width, gate sizing impact on circuit area, gate criticality and aged path slack time, provides a better guidance for the sizing approach.
AreaMOverheadM(%)
15 Prop.MMetric MetricMofM[8] 10
5
0
Figure 10.
C499 C880 C1908 C2670 C5315 C7552 Circuit
Area Overhead comparison for different ISCAS circuits.
VI. C ONCLUSIONS AND F UTURE W ORK An efficient metric to identify circuit gates that once resized provide a greater improvement in circuit reliability was proposed. The metric combines the impact of gate delay sensitivity to channel width sizing, gate sizing impact on circuit area, gate criticality and aged paths slack time. The concept of sensitivity was refined to consider two components related to the gate sizing impact on its initial delay and the gate sizing impact on delay degradation due to BTI. It was shown that not considering this second component may result in a significative underestimation of total gate delay sensitivity, and as consequence, an inappropriate design guidance would be provided. The metric was incorporated in a Sizing Framework for Reliability Enhancement to evaluate its effectiveness in different ISCAS benchmark circuits. The results show that the proposed metric provides good design guidance since only a small set of circuit gates need to be resized to assure that the delay constraint is met during overall expected lifetime. The results also show that circuit
lifetime can be further extended leading to higher product reliability, with low area overhead. Other gate selection metric in literature was used in the sizing framework for comparison purposes. It was shown the metric proposed here performs better since it provides a greater speed of convergence towards the timing constraint. This results also suggest that metrics to guide reliability enhancement should be developed according to the design technique to be applied in the circuit. As future work, we are planning to include the effect of process variations in the metric formulation problem. Aged timing behavior of each gate strongly depends on process variations, which further increase the complexity of the selection of the most favorable gates to enhance circuit reliability. R EFERENCES [1] M.S. Khan, S. Hamdioui, N.Z.B. Haron, CMOS scaling impacts on Reliability, What do we understand?, 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008. [2] J.H. Stathis, M. Wang, K. Zhao, “Reliability of advanced high-k/metalgate n-FET devices”, Microelectronics Reliability, Volume 50, Issues 911, SeptemberNovember 2010. [3] M.S. Khan, S. Hamdioui, “Temperature Impact on NBTI Modeling in the Framework of Technology Scaling” 2nd HiPEAC Workshop on Design for Reliability, 24 January 2010. [4] Kiamehr, S.; Firouzi, F.; Ebrahimi, M.; Tahoori, M.B., ”Aging-aware standard cell library design,” Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,4, 24-28 March 2014 [5] Khan, S.; Hamdioui, S., “Modeling and mitigating NBTI in nanoscale circuits,” On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International , vol., no., pp.1,6, 13-15 July 2011. [6] Kunhyuk Kang; Kufluoglu, H.; Alain, M.A.; Roy, K., “Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI,” Computer Design, 2006. ICCD 2006. International Conference on , vol., no., pp.216,221, 1-4 Oct. 2007. [7] Xiangning Yang; Saluja, K., “Combating NBTI Degradation via Gate Sizing,” Quality Electronic Design, 2007. ISQED ’07. 8th International Symposium on , vol., no., pp.47,52, 26-28 March 2007. [8] Wenping Wang; Shengqi Yang; Yu Cao, “Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect,” Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on , vol., no., pp.763,768, 17-19 March 2008. [9] Kostin, S.; Raik, J.; Ubar, R.; Jenihhin, M.; Vargas, F.; Bolzani Poehls, L.M.; Copetti, T.S., “Hierarchical identification of NBTI-critical gates in nanoscale logic,” Test Workshop - LATW, 2014 15th Latin American , vol., no., pp.1,6, 12-15 March 2014 [10] Zafar, S.; Kim, Y.H.; Narayanan, V.; Cabral, C.; Paruchuri, V.; Doris, B.; Stathis, J.; Callegari, A.; Chudzik, M., “A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates,” VLSI Technology, 2006. [11] Wenping Wang; Shengqi Yang; Bhardwaj, S.; Vrudhula, S.; Liu, F.; Yu Cao, “The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.18, no.2, pp.173,183, Feb. 2010 [12] Kiamehr, S.; Firouzi, F.; Tahoori, M.B., “Aging-aware timing analysis considering combined effects of NBTI and PBTI,” Quality Electronic Design (ISQED), 2013 14th International Symposium on , vol., no., pp.53,59, 4-6 March 2013. [13] Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann, “Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level”, ITInformation Technology, Volume 52, Issue 4, Pages 181187, July 2010.
I. I NTRODUCTION Reliability has become a major concern in deeply scaled CMOS technologies [1]. Design of reliable circuits that can operate correctly during a long period of time (i.e 10 years), even in extreme conditions, has become a very difficult challenge for safety critical applications. Bias Temperature Instability (BTI) has been shown to have significant impact in reliability of digital circuits [2], moreover, its effect is aggravated in new technology nodes due to high electric fields and elevated temperatures that devices experience [3]. BTI gradually increases transistors threshold voltage (V th) in the run-time, which is reflected in a continuous increment of circuit delay. If delay increases significantly, circuit correct functionality can not be assured. Ever greater guardbands are added to timing constraints to tolerate delay degradation, however, this penalizes performance. Hence, designers are forced to develop strategies to design circuits with enhanced reliability. In such way, circuit lifetime can be extended or required guardbands can be reduced as is shown in Figure 1. Several design techniques has been explored in the field of reliable circuits design. In [4] the authors proposed to use an Aging-aware standard cell library. Technology-mapping is performed to replace original gates by their robust counterpart. Although this technique can improve lifetime significantly, design and characterization of the cell library can be complex because it depends on specific workload conditions. Other design approaches are based in the formulation of a numerical optimization problem, which finds gates sizes that minimize circuit area while meeting the delay constraint [5][6][7]. However, these approaches require to identify the
-2
Figure 1. Delay degradation as function of time for a Reliability Enhanced Design and a non-Reliability Enhanced Design.
critical paths and gates within the circuit to be applied. Otherwise, they would result in area and power overhead. Design of reliable circuits requires more detailed guidance, such that designers can conduct effective reliability enhancement. Approaches in [8] and [9] use metrics to quantitatively estimate how much favorable is to take actions on a gate (i.e. to increase its size) to enhance circuit reliability. Although the metric in [8] allows to identify gates that suffer several delay degradation, it is not focused to any specific reliability-aware technique. For example, if gate sizing is going to be applied, delay sensitivity to channel width should be included in the metric. In [9] critical gates are identified by partitioning circuit delay constraint into gates delays constraints. Then, gates are ranked by applying a metric very similar to [8]. However, partitioning scheme does not consider that assigned constraint to each gate should consider specific gates workload. Previous works have only considered the BTI phenomenon in PMOS devices (NBTI), however, BTI in NMOS (PBTI) is an emerging reliability concern for subnanometer technologies with high-k dielectric materials, which should be considered in the design process. Furthermore, selection metrics should be formulated differently depending on the design technique to be applied to the circuit to provide better design guidelines. This paper proposes an efficient metric to select from BTIcritical paths, the most favorables gates that once oversized produce a greater benefit to circuit reliability. Parameters like gate delay sensitivity, gate sizing impact on circuit area, gate criticality and aged paths slack time are combined in the proposed metric to make it complete and accurate. Unlike other works, here gate delay sensitivity is considered to has two components corresponding to the sizing impact on the initial delay and the sizing impact on delay degradation. The
proposed metric was applied to some ISCAS85 benchmark circuits. The results show that our proposal provides adequate design guidance to achieve the required timing constraint along overall expected lifetime, and hence leading to higher product reliability, with low area overhead. The rest of this paper is organized as follows: In section II it is briefly reviewed how to compute gate delay degradation. In section III it is given a detailed explanation of the proposed metric formulation. In section IV, the overall reliability optimization procedure used in our work is exposed. In section V some results of the metric application to some ISCAS85 benchmark circuits to enhance circuit reliability are discused. Finally, conclusions and future work are given in section VI.
function of its gate terminal SP (SPB ), because its stress condition also depends on the status of the upper transistor in the series connection due to the stacking effect [12]. For M 2 transistor to be under NBTI stress condition, its gate has to be at logic zero and also M 1 has to be turned-on. Thus, TSP of transistor M 2 is equal to the probability of signals A and B being at logic zero simultaneously (See Figure 2). Finally, TSP of each NMOS device in the NOR2 gate is equal to its input signal probabilities. A similar analysis can be performed in other gate structures to obtain the TSP of each transistor.
II. D ELAY D EGRADATION M ODELING Delay degradation modeling is of great interest for designing reliable circuits. This section briefly reviews how circuit delay degradation can be estimated. A. Transistor Aging due to BTI Vth degradation due to BTI occurs during normal transistor operation at specific stress conditions: positive gate bias for NMOS (PBTI) and negative gate bias for PMOS (NBTI) transistors. In previous technology nodes, PBTI effect was negligible in comparison to NBTI. However, since the introduction of high-k metal-gate technologies, PBTI has also become a reliability concern [10]. V th degradation along the time depends on technology parameters, supply voltage, temperature and the average time the device is under the stress condition, which is usally expressed in terms of Transistor Stress Probability TSP. A simplified model of V th increment due to BTI (∆V thBT I ) is proposed in [11], ∆V thBT I = A · T SP n · tn
(1)
where A is a fitting constant that depends on technology node, temperature and Supply voltage, t is the aged time, and n is a constant with the value of 1/6. TSP can be seen as the probability of a transistor to be under the stress bias condition, and it depends on the signal probabilities of circuit inputs (workload pattern) and transistor position in the gate. In this work, it is assumed, without loss of generality, that both NBTI and PBTI mechanisms induce the same ∆V thBT I = 80mv at worst case stress conditions (T SP = 1). The constant A is fitted according to these assumptions. B. Transistor Stress Probability Computation TSP of each device in a gate can be computed based on signal probability at gate input nodes. Signal probability is usually defined as the probability of a node to be at high value (logic 1). Figure 2 shows an example to illustrate TSP computation of devices in a NOR2 gate. Let us to assume that inputs A and B have Signal Probabilities (SP) of 0.5 and 0.8, respectively. TSP of transistor M 1 is equal to the probability of signal A to be at logic zero, because this is the only condition required for M 1 to be negatively biased (stress condition). However, the TSP of transistor M 2 is not only a
Figure 2.
Stress probability computation for devices in a N OR2 gate.
In this work, the signal probabilities at gates inputs are obtained by Logic Simulation. A large number of randomly generated input vectors are applied to the circuit and it is counted how many times each internal node is settled at high logic level. Each node signal probability can be approximated as the ratio of the number of times the node was at high logic level to the total number of generated vectors. C. Aging-aware linear gate delay model The aged gate delay (Dage ) can be computed once the V th shift of each transistor is known. Assuming that the amount of V th degradation is small enough, a first order Taylor approximation at the nominal transistor parameter values can be used to obtain a gate delay expression as a linear function of V th shift of each transistor of the gate [13]. Dage = Dn +
X m∈Gate
∂Dn · ∆V thm ∂V thm
(2)
where Dn is the nominal (initial) gate delay, m is the set of transistors that belong to the gate and ∂V∂Dthnm is the gate delay sensitivitiy to V th shifts of transistor m. The sensitivity values are obtained during gate library characterization by polynomial fitting. Based on Equation 2, total aged delay can be expressed as the sum of nominal gate delay and gate delay degradation due to BTI, Dage = Dn + ∆D. Aged delay of a path can be obtained by adding all gates delays across it. If a path delay becomes larger than the clock period, the signal propagated by the path would reach memory elements, located at the end of the path, after the clock edge. Consequently, an incorrect logic value would be stored. III. M ETRIC F ORMULATION TO G UIDE S IZING TO E NHANCE R ELIABILITY Among all the gates in a circuit, there are some that once oversized result in a greater benefit to Circuit Reliability.
delay sensitivity can be underestimated, and as consequence, the most sensitive gates would not be selected to be resized.
The first parameter taken into account in the metric is delay sensitivity to channel width sizing. Selecting a gate with a greater sensitivity value results in greater delay reduction than selecting a gate with a lower sensitivity. When channel width of transistors that belong to a gate are resized, gate delay behavior over time is modified. Figure 3 shows the initial (nominal) delay and the gate delay degradation for rising output transition of a N OR2 gate as function of their PMOS transistors channel widths. Two effects can be observed: First, nominal delay reduces as the transistors channel widths increase because transistors current capability to charge (or discharge) capacitive loads is increased. Second, the gate delay degradation reduces as the transistors channel widths increase because gate delay sensitivity to V th shift due to BTI is reduced. Therefore, delay sensitivity to channel width sizing should be considered as a composite term of two components (See Equation 3): a) one corresponding to the sizing impact on initial gate delay, and b) a second corresponding to the sizing impact on gate delay degradation. (3)
60
12
50
11
-2
40
10
30
9
20
8 250
300
350
400
Channel Width (nm)
D (ps)
Dn (ps)
Dage Dn ∆D Sw = Sw + Sw
450
Figure 3. Nominal delay and Delay degradation for the rising transition of a N OR2 gate as function of PMOS channel width (T SP = 1, time = 10 years).
The two delay sensitivities can be obtained by the derivative of Equation 2 with respect to channel width. Figure 4 shows Dn ∆D the two delay sensitivities (Sw , Sw ) and the total gate Dage delay sensitivity (Sw ) as function of time (up to 10 years Dn or 120 months)for a N OR2 gate. It can be observed that Sw remains constant because it does not depends on the degra∆D dation that transistors experience. However, Sw becomes greater as devices ages due to BTI along time. The amount ∆D of Sw can be up to 15% of nominal sensitivity depending on gate structure, nominal gate size, input transition time, fan-out, and devices threshold voltage degradation. Thus, if this sensitivity component is not considered, the overall gate
Sensitivity (s/nm)
A. Gate Delay Sensitivity to Channel Width Sizing
x 10
-5
x 10 0
-3.9
Sw
-4
Sw
-4.1
Sw
Dn Dage
-1 -2
D
-4.2 -4.3 -4.4 0
20
-3 -4
-2
-6
Sensitivity (s/nm)
-3.8
-5
n
In this section, an efficient metric to identify those gates most favorable to be resized is developed. A close analysis is devoted to the main parameters allowing to identify the most favorable gates to be resized.
40 60 80 time (months)
100
-6 120
Figure 4. Delay Sensitivity components as function of time for the rising transition of a N OR2 gate (T SP = 1).
B. Gate Sizing Impact on Circuit Area Circuit area is a very important constraint in the design of digital circuits because it is proportional to power consumption and it affects the cost of a product. It is desirable to design circuits meeting delay and lifetime constraints at the cost of minimum area overhead. Therefore, it is important to consider the area cost of sizing-up a gate, in conjunction with its delay sensitivity to channel width. The total gate delay sensitivities and gate area of an INV and NOR2 gates as function of its transistors channel width are shown in Figures 5-a and 5-b, respectively. For similar delay sensitivities, i.e. W pmos = 200nm for INV gate and W pmos = 300nm for NOR2 gate, the area cost of the NOR2 gate is greater than for the INV gate. Based on this observation, in the proposed metric the gate delay sensitivities are normalized with respect to the gate area impact (ai ), which is a layout dependent parameter but can be estimated for a pre-designed gate Dage /ai ), library. By normalizing gate delays sensitivities (Sw the metric considers the gate delay reduction per unit increase in circuit area. C. Gate Criticality and Paths Slack Time Gate criticality: it can be considered as the number of critical paths passing across a gate [8]. Critical paths of a circuit, are those paths that do not met the timing constraint. Let us consider a circuit with two critical paths P 1 and P 2 (See Figure 6). If we resize a non-shared gate in one path (e.g. gate G1), it would be required to resize a gate in the other path. In this case two gates would be resized to meet timing constraint. However, if a shared gate (e.g G4 or G5) is resized, only one gate impacts the area cost. Usually, shared gates present higher criticality. Aged Path Slack Time: The aged delay of a critical path depends on its number of gates and their rate of degradation [11]. The amount of path delay degradation and its number of gates determine the severity of a path to violate the timing constraint. Therefore, we use aged path slack time to take
-4
paths, with high sensitivities (a greater fan-out, more degraded devices, etc.) would have a high metric value. Furthermore, the value given by the metric reduces for gates with high fan-in because they introduce a greater area overhead.
INV NOR2
-2
Sens
-3 -4 100
200
300 400 500 Wpmos (nm)
600
Sens+area+Crit
Sens+area+Crit+Slack
0.5 INV NOR2
0.6
-2 0.3
Figure 7. considered.
-2
0.2 0
2
0.4
0.8
-4.1 0.4
(a) Delay sensitivity as function of PMOS channel width.
Area ( m )
Sens+area
1
Normalized-Metric
(s/nm)
-1
Sw
Dage
x 10
n
0
0
1
2
3
Gate Label
4
5
Behavior of metric value when including each parameter
0.2 0.1 100
200
300 400 500 Wpmos (nm)
600
(b) Gate area as function of PMOS channel width. Figure 5. INV and NOR2 gates delays sensitivities and areas as function of PMOS transistors channel width for the rising transition at output. T SP = 0.5, time = 10 years.
Figure 6. Circuit example to illustrate gate criticality and slack time importance.
into account these effects. Aged path slack time (slackaged ) is defined as the difference between aged path delay and the delay constraint (See Equation 4). Then, its value is positive for critical paths and negative for non-critical paths. slackaged = Dage,pk − Dcons
(4)
D. Proposed Metric The proposed metric to select the most favorable gates to be up-sized is given in Equation 5. M etrici =
X (S Dn + S ∆D ) · slackaged,k Wi Wi ai
Figure 7 illustrates the impact of each parameter discussed above on the metric behavior of the gates in the circuit of Figure 6. Metric values are normalized with respect to the maximum obtained at each case. For the case when only sensitivity is considered (sens), the gates have metrics values of the same order. Some differences occur depending on the activated network, capacitive load and input slew rate at each gate. For the case when the gate impact on area due to sizing is included in the metric (sens+area), normalized metric values for inverter gates remains almost the same. However, NAND2 gate (G4) metric value decreases because increasing size of this gate requires more area. If gate criticality is now considered (sens+area+Crit), gates G4 and G5 becomes more important than the others because both critical paths P1 and P2 pass across them. Finally, including aged paths slack time (sens+area+crit+slack) significantly reduces G3 normalized metric value because it only belongs to the least critical path P 2 while importance of inverters G0 − G2 increase because they belongs to the most critical path P 1. For this example, inverter gate G1 is the most favorable gate to be resized. Although gates G4 and G5 impact on two paths, the slack time of one of them is very small (path G3-G4-G5 is not very critical). However, gate G1 has a greater sensitiviy and belongs to the most critical path. Thus, G1 achieves a greater metric value.
(5)
∀k∈CP
where the summation considers the gate criticality. From Equation 5, it is expected that gates in the most critical
IV. S IZING F RAMEWORK FOR R ELIABILITY E NHANCEMENT The proposed metric has been incorporated in the sizing framework for reliability enhancement shown in Figure 8. The sizing framework is as follows: Starting from a circuit designed with a standard gate library, logic simulation is performed to obtain internal nodes signal probabilities and transistors TSP. Next, the linear gate delay degradation model is used to perform a BTI-Aware Path-Based Static Timing
Table I A PPLICATION TO ISCAS B ENCHMARK C IRCUITS R ESULTS
CP
CG
5 years OG OD(%)
AO(%)
CP
CG
10 years OG OD(%)
175
12103
107
30
12.56
4.72
15872
111
31
13.47
9440
220
3532
173
5.82
48
13.26
4.90
4212
187
44
14.61
C880
4935
254
174
5.91
62
18
11.83
1.39
219
63
19
13.08
C1908
15638
253
1.76
1747
144
34
14.14
1.99
2176
148
47
15.77
C2670
3381
2.65
419
138
78
26
12.03
0.88
187
79
29
13.20
C5315
1.08
24662
1224
432
253
32
13.76
0.33
594
298
37
15.21
C7552
0.41
43174
1450
418
252
16
11.43
0.06
579
267
18
12.37
0.08
Circuit
Num.Paths
Num.Gates
C432
82364
C499
AO(%)
CP=Critical Paths, CG=Critical Gates, OG=Optimized Gates, OD=Optimized Delay, AO=Area Overhead.
V. A PPLICATION TO ISCAS B ENCHMARK C IRCUITS
-4.1
n
-2
Figure 8.
Sizing Framework for Realiability Enhancement.
Analysis (STA), which allows to obtain aged delay information of each path. The set of all circuit paths is reduced to a critical path set composed only by those paths that do not meet the required delay constraint for the expected lifetime (i.e. 5 or 10 years). Here, the delay constraint is assumed to be the initial (without aging) circuit delay that is the maximum initial delay within overall paths. Once the set of critical paths is obtained, the proposed critical gate selection metric is evaluated for each gate belonging to the critical path set. The metric is separately evaluated for the pull-up and pull-down network of each gate because they can impact differently on circuit delay. Then, gates are ranked from the highest to the lowest value of the metric and an user-defined number N of gates with the highest metric value are selected to be resized by a small step size increment. In order to reduce area overhead, only the specific selected network on each gate is resized. This is done because a gate can be severely affected by NBTI in PMOS while it is not greatly affected by PBTI in NMOS. The above process is iteratively repeated several times until the delay constraint is met. Once some gates are resized, a non-critical path could now become critical due to loading effects. Also a critical path can now become non-critical because its timing behavior has been improved. Therefore, the set of critical paths is updated at each iteration. Note that the proposed flow require to perform STA each time that selected gates are resized. Thus, to avoid runtime issues the number of critical gates selected at each iteration can be modified according to circuit size, also step size increment of selected gates can be changed.
Table I summarizes the results obtained applying the proposed metric to some ISCAS benchmark circuits. Information about, critical paths (CP), critical gates (CG), Optimized Gates (OG), Optimized Delay (OD) and Area Overhead (AO) are provided for two different lifetime intervals (5 years and 10 years). Here, the timing constraint was settled at the nominal (without aging) circuit delay. Using the proposed metric, up to ten gates are selected at each iteration (N = 10). As can be seen, the number of optimized gates to achieve the required delay constraint is small compared to the overall critical gates set. This indicates that not all gates in critical paths provide as delay improvement as this small gates set. Therefore, the proposed metric gives good design guidelines since delay constraint can be met by focusing optimization only on these gates. It can be seen from table I that optimized delay is around within 11% to 16% depending on the circuit and its expected lifetime (5 years or 10 years). These optimization values correspond to the delay degradation of the initial circuit design since delay constraint was settled as the initial circuit delay. Therefore, the results correspond to the case where guardband is reduced by 100% (see Figure 1) for all circuits. Lower area overhead would be obtained if some small guardband is allowed to tolerate BTI induced delay degradation. Table I also shows that as degradation time increases, more circuit paths can become critical due to BTI effects because lifetime constraint is more stringent. However, these extra critical paths can be considered in the reliability enhancement framework with a low increase in area overhead. In other words, circuits lifetime can be extended from 5 years to 10 years at the cost of very low additional area overhead (i.e from 4.72% to 5.82% for C432 circuit ). Figure 9 shows delay reduction of circuit C1908 at each iteration for two different metrics used in the sizing framework for comparison purposes. Blue curve corresponds to the metric used in this work while red curve corresponds to the metric used in [8], which takes into account criticality and delay degradation, but slack time or sensitivity are not considered. The proposed metric performs much better since it requires less iterations to achieve the same delay constraint. Figure 10 shows a comparison between area overhead obtained using the metric in [8] and the metric proposed here. For all circuits
Prop.dMetric Metricdofd[8]
1.15 1.1 1.05 -4.1 1 0.95 0
-2
Spec.
n
NormalizeddDelay
1.2
20
40 60 80 100 120 Iteration
Figure 9. Delay Reduction at each iteration for C1908 ISCAS circuit. Two different metrics were used in the sizing framework: the proposed metric (Blue curve) and the metric in [8] (Red curve).
the proposed metric reduces significantly the area overhead in comparison to the metric in [8]. These results makes evident that gate selection metrics should be developed according to the design technique that would be applied to the circuit. In our case, including delay sensitivity to channel width, gate sizing impact on circuit area, gate criticality and aged path slack time, provides a better guidance for the sizing approach.
AreaMOverheadM(%)
15 Prop.MMetric MetricMofM[8] 10
5
0
Figure 10.
C499 C880 C1908 C2670 C5315 C7552 Circuit
Area Overhead comparison for different ISCAS circuits.
VI. C ONCLUSIONS AND F UTURE W ORK An efficient metric to identify circuit gates that once resized provide a greater improvement in circuit reliability was proposed. The metric combines the impact of gate delay sensitivity to channel width sizing, gate sizing impact on circuit area, gate criticality and aged paths slack time. The concept of sensitivity was refined to consider two components related to the gate sizing impact on its initial delay and the gate sizing impact on delay degradation due to BTI. It was shown that not considering this second component may result in a significative underestimation of total gate delay sensitivity, and as consequence, an inappropriate design guidance would be provided. The metric was incorporated in a Sizing Framework for Reliability Enhancement to evaluate its effectiveness in different ISCAS benchmark circuits. The results show that the proposed metric provides good design guidance since only a small set of circuit gates need to be resized to assure that the delay constraint is met during overall expected lifetime. The results also show that circuit
lifetime can be further extended leading to higher product reliability, with low area overhead. Other gate selection metric in literature was used in the sizing framework for comparison purposes. It was shown the metric proposed here performs better since it provides a greater speed of convergence towards the timing constraint. This results also suggest that metrics to guide reliability enhancement should be developed according to the design technique to be applied in the circuit. As future work, we are planning to include the effect of process variations in the metric formulation problem. Aged timing behavior of each gate strongly depends on process variations, which further increase the complexity of the selection of the most favorable gates to enhance circuit reliability. R EFERENCES [1] M.S. Khan, S. Hamdioui, N.Z.B. Haron, CMOS scaling impacts on Reliability, What do we understand?, 19th Annual Workshop on Circuits, Systems and Signal Processing (ProRISC 2008), 27-28 November 2008. [2] J.H. Stathis, M. Wang, K. Zhao, “Reliability of advanced high-k/metalgate n-FET devices”, Microelectronics Reliability, Volume 50, Issues 911, SeptemberNovember 2010. [3] M.S. Khan, S. Hamdioui, “Temperature Impact on NBTI Modeling in the Framework of Technology Scaling” 2nd HiPEAC Workshop on Design for Reliability, 24 January 2010. [4] Kiamehr, S.; Firouzi, F.; Ebrahimi, M.; Tahoori, M.B., ”Aging-aware standard cell library design,” Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,4, 24-28 March 2014 [5] Khan, S.; Hamdioui, S., “Modeling and mitigating NBTI in nanoscale circuits,” On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International , vol., no., pp.1,6, 13-15 July 2011. [6] Kunhyuk Kang; Kufluoglu, H.; Alain, M.A.; Roy, K., “Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI,” Computer Design, 2006. ICCD 2006. International Conference on , vol., no., pp.216,221, 1-4 Oct. 2007. [7] Xiangning Yang; Saluja, K., “Combating NBTI Degradation via Gate Sizing,” Quality Electronic Design, 2007. ISQED ’07. 8th International Symposium on , vol., no., pp.47,52, 26-28 March 2007. [8] Wenping Wang; Shengqi Yang; Yu Cao, “Node Criticality Computation for Circuit Timing Analysis and Optimization under NBTI Effect,” Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on , vol., no., pp.763,768, 17-19 March 2008. [9] Kostin, S.; Raik, J.; Ubar, R.; Jenihhin, M.; Vargas, F.; Bolzani Poehls, L.M.; Copetti, T.S., “Hierarchical identification of NBTI-critical gates in nanoscale logic,” Test Workshop - LATW, 2014 15th Latin American , vol., no., pp.1,6, 12-15 March 2014 [10] Zafar, S.; Kim, Y.H.; Narayanan, V.; Cabral, C.; Paruchuri, V.; Doris, B.; Stathis, J.; Callegari, A.; Chudzik, M., “A Comparative Study of NBTI and PBTI (Charge Trapping) in SiO2/HfO2 Stacks with FUSI, TiN, Re Gates,” VLSI Technology, 2006. [11] Wenping Wang; Shengqi Yang; Bhardwaj, S.; Vrudhula, S.; Liu, F.; Yu Cao, “The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.18, no.2, pp.173,183, Feb. 2010 [12] Kiamehr, S.; Firouzi, F.; Tahoori, M.B., “Aging-aware timing analysis considering combined effects of NBTI and PBTI,” Quality Electronic Design (ISQED), 2013 14th International Symposium on , vol., no., pp.53,59, 4-6 March 2013. [13] Dominik Lorenz, Georg Georgakos, Ulf Schlichtmann, “Aging-aware Timing Analysis of Combinatorial Circuits on Gate Level”, ITInformation Technology, Volume 52, Issue 4, Pages 181187, July 2010.
