Efficient Determination of Feedback DAC Errors for Digital Correction ...
Efficient Determination of Feedback DAC Errors for Digital Correction in ∆Σ A/D converters 2010 International Symposium on Circuits and Systems, Paris, France Nagendra Krishnapura Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India
31 May 2010
Outline
• Motivation • DAC realizations • Element usage in idle channel • Determining correction values • Simulation results • Conclusions
Multi bit ∆Σ ADC
Loop filter u
+
L(z)
Σ
ADC
v
z
v z
DAC
Multi bit ∆Σ ADC—DAC nonlinearity
Loop filter u
+
L(z)
Σ
ADC
v
z
v z
DAC
Effect of DAC nonlinearity OSR=64, OBG=3, 17 levels, 3σDAC=0.001LSB Ideal With DAC errors
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
Mitigating DAC nonlinearity—Dynamic element matching Loop filter u
+
L(z)
Σ
ADC
v
z
v z
DAC
DEM
• Excess loop delay • Tones for low OSR • Increased DAC dynamic nonlinearity
Mitigating DAC nonlinearity—Digital correction Loop filter u
+
L(z)
Σ
-
ADC
v
+ +
w
Σ
Ek(v) z
DAC
Ek
N elements
k=0...N
• Reconfigure the loop as a 1 bit ∆Σ modulator and
measure all DAC error values Ek J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electronics Letters, vol. 37, no. 12, 2001.
Multi bit feedback DAC-generic representation C0
±I0
±I0
C0
±I0
z0 z1
zN
R0
C0
R0
R0
+Vref
+Vref
-Vref
-Vref
= −D1 − D2 − D3 − . . . − DN = +D1 − D2 − D3 − . . . − DN .. . = +D1 + D2 + D3 + . . . + DN
• D0 : I0 , C0 Vref , Vref /R0 • Dk = D0 (1 + δk ) • Assume D0 = 1: Nominal LSB = 2, max = +N, min = −N
Multi bit ∆Σ modulator—Idle channel
Doff u
+
L(z)
Σ
v
Loop filter
-
ADC
v t
z
DAC
u
+
Loop filter L(z)
Σ
z
DAC
ADC
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
Multi bit ∆Σ modulator—Idle channel
u
+
Loop filter L(z)
Σ
z
DAC
ADC
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
Multi bit ∆Σ modulator—Idle channel
u
+
Loop filter L(z)
Σ
ADC
w
DAC
0
±I0
±I0
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
D1 removed from the DAC
Loop filter
D1
+
L(z)
Σ
ADC
w
DAC
±I0
±I0
±I0
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
D1 removed from the DAC
Estimating DAC errors Doff u
+
Doff
Loop filter L(z)
Σ
ADC
v
-
u
+
Loop filter L(z)
Σ
ADC
v
-
w
w
DAC
0
±I0
±I0
DAC
±I0
0
±I0
• Remove D1 from the DAC
• Remove D2 from the DAC
• Vav ,1 = D1 + Doff + NL|D1 +Doff
• Vav ,2 = D2 + Doff + NL|D2 +Doff
NL|D1 +Doff
≈ NL|D1 +Doff
D2 − D1 ≈ Vav ,2 − Vav ,1 Dk +1 − Dk
= Vav ,k +1 − Vav ,k
u
+
Loop filter L(z)
Σ
ADC
w
DAC
±I0
±I0
0
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
D16 removed from the DAC
Loop filter
-D16
+
L(z)
Σ
ADC
w
DAC
±I0
±I0
±I0
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
D16 removed from the DAC
Estimating DAC errors
• Remove D16 from the DAC
• Remove D15 from the DAC
• Vav ,16 = −D16 +Doff +NL|−D16 +Doff
• Vav ,15 = −D15 +Doff +NL|−D15 +Doff
NL|−D15 +Doff
≈ NL|−D16 +Doff
D16 − D15 ≈ −Vav ,16 + Vav ,15 Dk +1 − Dk
= −Vav ,k +1 + Vav ,k
Estimating DAC errors Doff uoff
+
Loop filter L(z)
Σ
ADC
z
DAC
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
Doff uoff
+
Loop filter L(z)
Σ
ADC
z
DAC
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
• Add a positive offset
• Add a negative offset
• Determine Dk +1 − Dk for
• Determine Dk +1 − Dk for
k = 1...8 • Dk +1 − Dk = Vav ,k +1 − Vav ,k
k = 9 . . . 16 • Dk +1 − Dk = −Vav ,k +1 + Vav ,k
All successive differences Dk +1 − Dk , k = 2 . . . 16 thus obtained
Digital error correction Loop filter u
+
L(z)
Σ
-
ADC
v
+ +
w
Σ
Ek(v) z
DAC
Ek
N elements
k=0...N
• Correction at DAC output • DAC has unequal element values Dk • Add D1 − Dk to Dk (k = 2 . . . 16) to make all elements equal • Equivalent correction at DAC input • Add ±(D1 − Dk ), k = 2 . . . 16 to v • +(D1 − Dk ) if Dk is switched positively • −(D1 − Dk ) if Dk is switched negatively
Determine errors wrt one element (D1 ) D2-D1
MUX
D3-D2
D2-D1 D3-D1
16:1
D16-D15
control
D16-D1
D2 − D1 D3 − D1 = (D3 − D2 ) + (D2 − D1 ) .. . DN − D1 = (DN − DN−1 ) + (DN−1 − DN−2 ) + . . . + (D2 − D1 )
Determine correction values Ek for each level k E1 D2-D1
E2
MUX
D3-D1 16:1
twos compl.
D16-D1 control
E17
E0 −1 −1 . . . −1 0 E2 +1 −1 . . . −1 D2 − D1 .. = .. .. . . . EN +1 +1 . . . +1 DN − D1
Extra hardware required
Determining calibration values • 3 registers • 1 MUX • 1 accumulator with 2’s complement
Simulation results: Ideal DAC OSR=64, OBG=3, 17 levels Ideal
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
Simulation results: Effect of DAC nonlinearity OSR=64, OBG=3, 17 levels, 3σDAC=0.001LSB Ideal With DAC errors
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
After one correction step—residual distortion OSR=64, OBG=3, 17 levels, 3σDAC=0.001LSB Ideal With DAC errors After 1 calibration step
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
Repeat calibration using first correction—nearly ideal OSR=64, OBG=3, 17 levels, 3σDAC=0.001LSB Ideal With DAC errors After 1 calibration step After 2 calibration steps
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
OSR=64, OBG=3, 17 levels, σDAC = 0.001LSB
Ideal Without correction One correction step Two correction steps
SNR 121.9 dB 97.0 dB 120.5 dB 122.0 dB
HD2 — 74.2 dB 112.0 dB —
HD3 — 83.8 dB 119.3 dB 126.0 dB
Using only first order averaging • ∼ 216 samples for the first step • ∼ 218 samples for second step • ∼ 16(216 + 218 ) ∼ 5 × 106 samples for calibration
Simulation results: Ideal DAC OSR=16, OBG=3, 17 levels, 3σDAC=0.01LSB Ideal
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.02
0.04
f/fs
0.06
0.08
0.1
Simulation results: Effect of DAC nonlinearity OSR=16, OBG=3, 17 levels, 3σDAC=0.01LSB Ideal With DAC errors
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.02
0.04
f/fs
0.06
0.08
0.1
After one correction step—residual distortion OSR=16, OBG=3, 17 levels, 3σDAC=0.01LSB Ideal With DAC errors After 1 calibration step
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.02
0.04
f/fs
0.06
0.08
0.1
Repeat calibration using first correction—nearly ideal OSR=16, OBG=3, 17 levels, 3σDAC=0.01LSB Ideal With DAC errors After 1 calibration step After 2 calibration steps
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.02
0.04
f/fs
0.06
0.08
0.1
OSR=16, OBG=3, 17 levels, σDAC = 0.01LSB
Ideal Without correction One correction step Two correction steps
SNR 83.0 dB 73.9 dB 83.2 dB 83.2 dB
HD2 — 54.2 dB 88.7 dB —
HD3 — 63.7 dB 102.8 dB —
Using only first order averaging • ∼ 215 samples for the first step • ∼ 215 samples for second step • ∼ 16(215 + 215 ) ∼ 106 samples for calibration
Conclusions
• DAC errors estimated by disabling DAC elements one by
one in idle channel • No reconfiguration of the loop • Two steps sufficient to recover DAC errors accurately
References
S. R. Norsworthy, R. Schreier, and G. C. Temes (Eds.), Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, 1997 J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electron. Lett., vol. 37, no. 12, 2001. S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, “A power optimized continuous-time ∆Σ ADC for audio applications,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 351 - 360, February 2008.
31 May 2010
Outline
• Motivation • DAC realizations • Element usage in idle channel • Determining correction values • Simulation results • Conclusions
Multi bit ∆Σ ADC
Loop filter u
+
L(z)
Σ
ADC
v
z
v z
DAC
Multi bit ∆Σ ADC—DAC nonlinearity
Loop filter u
+
L(z)
Σ
ADC
v
z
v z
DAC
Effect of DAC nonlinearity OSR=64, OBG=3, 17 levels, 3σDAC=0.001LSB Ideal With DAC errors
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
Mitigating DAC nonlinearity—Dynamic element matching Loop filter u
+
L(z)
Σ
ADC
v
z
v z
DAC
DEM
• Excess loop delay • Tones for low OSR • Increased DAC dynamic nonlinearity
Mitigating DAC nonlinearity—Digital correction Loop filter u
+
L(z)
Σ
-
ADC
v
+ +
w
Σ
Ek(v) z
DAC
Ek
N elements
k=0...N
• Reconfigure the loop as a 1 bit ∆Σ modulator and
measure all DAC error values Ek J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electronics Letters, vol. 37, no. 12, 2001.
Multi bit feedback DAC-generic representation C0
±I0
±I0
C0
±I0
z0 z1
zN
R0
C0
R0
R0
+Vref
+Vref
-Vref
-Vref
= −D1 − D2 − D3 − . . . − DN = +D1 − D2 − D3 − . . . − DN .. . = +D1 + D2 + D3 + . . . + DN
• D0 : I0 , C0 Vref , Vref /R0 • Dk = D0 (1 + δk ) • Assume D0 = 1: Nominal LSB = 2, max = +N, min = −N
Multi bit ∆Σ modulator—Idle channel
Doff u
+
L(z)
Σ
v
Loop filter
-
ADC
v t
z
DAC
u
+
Loop filter L(z)
Σ
z
DAC
ADC
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
Multi bit ∆Σ modulator—Idle channel
u
+
Loop filter L(z)
Σ
z
DAC
ADC
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
Multi bit ∆Σ modulator—Idle channel
u
+
Loop filter L(z)
Σ
ADC
w
DAC
0
±I0
±I0
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
D1 removed from the DAC
Loop filter
D1
+
L(z)
Σ
ADC
w
DAC
±I0
±I0
±I0
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
D1 removed from the DAC
Estimating DAC errors Doff u
+
Doff
Loop filter L(z)
Σ
ADC
v
-
u
+
Loop filter L(z)
Σ
ADC
v
-
w
w
DAC
0
±I0
±I0
DAC
±I0
0
±I0
• Remove D1 from the DAC
• Remove D2 from the DAC
• Vav ,1 = D1 + Doff + NL|D1 +Doff
• Vav ,2 = D2 + Doff + NL|D2 +Doff
NL|D1 +Doff
≈ NL|D1 +Doff
D2 − D1 ≈ Vav ,2 − Vav ,1 Dk +1 − Dk
= Vav ,k +1 − Vav ,k
u
+
Loop filter L(z)
Σ
ADC
w
DAC
±I0
±I0
0
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
D16 removed from the DAC
Loop filter
-D16
+
L(z)
Σ
ADC
w
DAC
±I0
±I0
±I0
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
always +ve
Doff
always -ve
D16 removed from the DAC
Estimating DAC errors
• Remove D16 from the DAC
• Remove D15 from the DAC
• Vav ,16 = −D16 +Doff +NL|−D16 +Doff
• Vav ,15 = −D15 +Doff +NL|−D15 +Doff
NL|−D15 +Doff
≈ NL|−D16 +Doff
D16 − D15 ≈ −Vav ,16 + Vav ,15 Dk +1 − Dk
= −Vav ,k +1 + Vav ,k
Estimating DAC errors Doff uoff
+
Loop filter L(z)
Σ
ADC
z
DAC
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
Doff uoff
+
Loop filter L(z)
Σ
ADC
z
DAC
v
D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
• Add a positive offset
• Add a negative offset
• Determine Dk +1 − Dk for
• Determine Dk +1 − Dk for
k = 1...8 • Dk +1 − Dk = Vav ,k +1 − Vav ,k
k = 9 . . . 16 • Dk +1 − Dk = −Vav ,k +1 + Vav ,k
All successive differences Dk +1 − Dk , k = 2 . . . 16 thus obtained
Digital error correction Loop filter u
+
L(z)
Σ
-
ADC
v
+ +
w
Σ
Ek(v) z
DAC
Ek
N elements
k=0...N
• Correction at DAC output • DAC has unequal element values Dk • Add D1 − Dk to Dk (k = 2 . . . 16) to make all elements equal • Equivalent correction at DAC input • Add ±(D1 − Dk ), k = 2 . . . 16 to v • +(D1 − Dk ) if Dk is switched positively • −(D1 − Dk ) if Dk is switched negatively
Determine errors wrt one element (D1 ) D2-D1
MUX
D3-D2
D2-D1 D3-D1
16:1
D16-D15
control
D16-D1
D2 − D1 D3 − D1 = (D3 − D2 ) + (D2 − D1 ) .. . DN − D1 = (DN − DN−1 ) + (DN−1 − DN−2 ) + . . . + (D2 − D1 )
Determine correction values Ek for each level k E1 D2-D1
E2
MUX
D3-D1 16:1
twos compl.
D16-D1 control
E17
E0 −1 −1 . . . −1 0 E2 +1 −1 . . . −1 D2 − D1 .. = .. .. . . . EN +1 +1 . . . +1 DN − D1
Extra hardware required
Determining calibration values • 3 registers • 1 MUX • 1 accumulator with 2’s complement
Simulation results: Ideal DAC OSR=64, OBG=3, 17 levels Ideal
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
Simulation results: Effect of DAC nonlinearity OSR=64, OBG=3, 17 levels, 3σDAC=0.001LSB Ideal With DAC errors
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
After one correction step—residual distortion OSR=64, OBG=3, 17 levels, 3σDAC=0.001LSB Ideal With DAC errors After 1 calibration step
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
Repeat calibration using first correction—nearly ideal OSR=64, OBG=3, 17 levels, 3σDAC=0.001LSB Ideal With DAC errors After 1 calibration step After 2 calibration steps
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.01
0.02
f/fs
0.03
0.04
0.05
OSR=64, OBG=3, 17 levels, σDAC = 0.001LSB
Ideal Without correction One correction step Two correction steps
SNR 121.9 dB 97.0 dB 120.5 dB 122.0 dB
HD2 — 74.2 dB 112.0 dB —
HD3 — 83.8 dB 119.3 dB 126.0 dB
Using only first order averaging • ∼ 216 samples for the first step • ∼ 218 samples for second step • ∼ 16(216 + 218 ) ∼ 5 × 106 samples for calibration
Simulation results: Ideal DAC OSR=16, OBG=3, 17 levels, 3σDAC=0.01LSB Ideal
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.02
0.04
f/fs
0.06
0.08
0.1
Simulation results: Effect of DAC nonlinearity OSR=16, OBG=3, 17 levels, 3σDAC=0.01LSB Ideal With DAC errors
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.02
0.04
f/fs
0.06
0.08
0.1
After one correction step—residual distortion OSR=16, OBG=3, 17 levels, 3σDAC=0.01LSB Ideal With DAC errors After 1 calibration step
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.02
0.04
f/fs
0.06
0.08
0.1
Repeat calibration using first correction—nearly ideal OSR=16, OBG=3, 17 levels, 3σDAC=0.01LSB Ideal With DAC errors After 1 calibration step After 2 calibration steps
40 20 0
dB
−20 −40 −60 −80 −100 −120 0
0.02
0.04
f/fs
0.06
0.08
0.1
OSR=16, OBG=3, 17 levels, σDAC = 0.01LSB
Ideal Without correction One correction step Two correction steps
SNR 83.0 dB 73.9 dB 83.2 dB 83.2 dB
HD2 — 54.2 dB 88.7 dB —
HD3 — 63.7 dB 102.8 dB —
Using only first order averaging • ∼ 215 samples for the first step • ∼ 215 samples for second step • ∼ 16(215 + 215 ) ∼ 106 samples for calibration
Conclusions
• DAC errors estimated by disabling DAC elements one by
one in idle channel • No reconfiguration of the loop • Two steps sufficient to recover DAC errors accurately
References
S. R. Norsworthy, R. Schreier, and G. C. Temes (Eds.), Delta-Sigma Data Converters: Theory, Design, and Simulation, IEEE Press, 1997 J. Silva, U. Moon, J. Steensgaard, and G. C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electron. Lett., vol. 37, no. 12, 2001. S. Pavan, N. Krishnapura, R. Pandarinathan, and P. Sankar, “A power optimized continuous-time ∆Σ ADC for audio applications,” IEEE Journal of Solid-State Circuits, vol. 43, pp. 351 - 360, February 2008.
