embedded systems - Semantic Scholar
EMBEDDED SYSTEMS: REAL-TIME OPERATING SYSTEMS FOR ARM ® CORTEX™-M MICROCONTROLLERS
Volume 3 Second Edition
Jonathan W. Valvano
ii
Jonathan Valvano
Second edition
ARM and uVision are registered trademarks of ARM Limited. Cortex and Keil are trademarks of ARM Limited. Stellaris is a registered trademark Texas Instruments. Code Composer Studio is a trademark of Texas Instruments. All other product or service names mentioned herein are the trademarks of their respective owners.
In order to reduce costs, this college textbook has been self-published. For more information about my classes, my research, and my books, see http://users.ece.utexas.edu/~valvano/ For corrections and comments, please contact me at: [email protected]. Please cite this book as: J. W. Valvano, Embedded Systems: Real-Time Operating Systems for ARM® Cortex™-M Microcontrollers, Volume 3, http://users.ece.utexas.edu/~valvano/, ISBN: 978-1466468863. Copyright © 2012 Jonathan W. Valvano All rights reserved. No part of this work covered by the copyright herein may be reproduced, transmitted, stored, or used in any form or by any means graphic, electronic, or mechanical, including but not limited to photocopying, recording, scanning, digitizing, taping, web distribution, information networks, or information storage and retrieval, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without the prior written permission of the publisher. ISBN-13: 978-1466468863 ISBN-10: 1466468866
Jonathan Valvano
Table of Contents Preface to The Second Edition ................................................................. ix Preface to Volume 3................................................................................... x Acknowledgements ................................................................................... xi 1. Review of Computer Architecture ........................................................ 1 1.1. Embedded Systems........................................................................ 1 1.2. Computer Architecture................................................................... 2 1.2.1. Computers, processors, memory, and microcontrollers................ 2 1.2.2. Cortex™-M processor ......................................................................... 6 1.3. Cortex™-M Processor Architecture .............................................. 7 1.3.1. Registers................................................................................................ 7 1.3.2. Memory................................................................................................. 9 1.3.3. Stack....................................................................................................... 11 1.3.4. Operating modes ................................................................................. 13 1.3.5. Reset ...................................................................................................... 14 1.4. Stellaris® LM3S8962 I/O pins ........................................................ 14 1.4.1 Stellaris® LM3S8962 I/O pins............................................................ 15 1.4.2 Stellaris® LM3S2110 I/O pins............................................................ 19 1.4.3. Stellaris® LM4F120 LaunchPad I/O pins........................................ 20 1.5. ARM® Cortex™-M Assembly Language ....................................... 24 1.5.1. Syntax.................................................................................................... 25 1.5.2. Addressing modes and operands ..................................................... 26 1.5.3. Memory access instructions ............................................................... 29 1.5.4. Logical operations ............................................................................... 31 1.5.5. Shift operations .................................................................................... 32 1.5.6. Arithmetic operations ......................................................................... 34 1.5.7. Functions and control flow ................................................................ 37
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1.5.8. Stack usage ...........................................................................................41 1.5.9. Assembler directives ...........................................................................42 1.6. ARM® Cortex™ Microcontroller Software Interface Standard.... 43 1.7. Exercises ......................................................................................... 43 2. Design of I/O Interfaces ......................................................................... 45 2.1. Flowcharts....................................................................................... 45 2.2. Digital Logic and Open Collector .................................................. 48 2.3. Parallel I/O ports ............................................................................. 59 2.4. Phase-Lock-Loop............................................................................ 62 2.5. NVIC on the ARM® Cortex™-M Processor ................................... 63 2.6. SysTick Timer ................................................................................. 67 2.7. Edge-triggered Interfacing ............................................................. 70 2.8. Configuring Digital Output Pins .................................................... 74 2.9. UART Interface................................................................................ 75 2.9.1. Transmitting in asynchronous mode................................................77 2.9.2. Receiving in asynchronous mode .....................................................78 2.9.3. LM3S/LM4F UART Details ...............................................................79 2.9.4. UART device driver ............................................................................81 2.9.5. Interrupt-Driven UART......................................................................82 2.10. Synchronous Transmission and Receiving using the SSI........ 85 2.11. DAC Operation and Performance Measures .............................. 89 2.12 Analog to Digital Converters ........................................................ 93 2.12.1. ADC Parameters ................................................................................93 2.12.2. Internal ADC ......................................................................................95 2.13. Data Acquisition Systems............................................................ 99 2.14. Exercises ....................................................................................... 106 3. Software Design..................................................................................... 109 3.1. The Design Process ....................................................................... 110 3.1.1. Requirements document ....................................................................110 3.1.2. Top-down design.................................................................................111
Jonathan Valvano
3.2. Memory Management and the Heap.............................................. 117 3.2.1. Use of the Heap.................................................................................... 117 3.2.2. Simple Fixed-Size Heap...................................................................... 119 3.2.3. Memory Manager: malloc and free................................................... 121 3.3. Threads............................................................................................ 125 3.4. First In First Out Queue.................................................................. 131 3.4.1. Classical definition of a FIFO............................................................. 131 3.4.2. Two-pointer FIFO implementation................................................... 132 3.4.3. FIFO build macros............................................................................... 136 3.5. Interthread Communication and Synchronization....................... 138 3.6. Critical Sections ............................................................................. 145 3.7. Introduction to Debugging............................................................. 151 3.7.1. Debugging Tools ................................................................................. 151 3.7.2. Debugging Theory .............................................................................. 153 3.7.3. Functional Debugging ........................................................................ 155 3.7.4. Performance Debugging..................................................................... 158 3.7.5. Profiling ............................................................................................... 161 4. Real-Time Operating Systems .............................................................. 163 4.1. Fundamentals ................................................................................. 164 4.2. Round-Robin Scheduler................................................................. 171 4.3. Semaphores .................................................................................... 178 4.3.1. Spin-lock semaphore implementation ............................................. 178 4.3.2. Blocking semaphore implementation............................................... 181 4.4. Thread Synchronization and Communication ............................. 183 4.4.1. Thread synchronization or rendezvous ........................................... 183 4.4.2. Resource sharing, nonreentrant code or mutual exclusion........... 183 4.4.3. Thread communication between two threads using a mailbox ... 184 4.4.4. Thread communication between threads using a FIFO queue..... 185 4.4.5. Readers-Writers Problem ................................................................... 186 4.4.6. Switch Debouncing ............................................................................. 187
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4.4.7. Deadlocks..............................................................................................189 4.5. Monitors........................................................................................... 191 4.6. Fixed Scheduling ............................................................................ 193 4.7. OS Considerations for I/O Devices ............................................... 198 4.7.1 Board Support Package .......................................................................198 4.7.2 Path Expression.....................................................................................200 4.8. Exercises ......................................................................................... 202 4.9. Lab Assignments............................................................................ 207 5. Digital Signal Processing ...................................................................... 209 5.1. Basic Principles .............................................................................. 210 5.2. Audio Input/Output ......................................................................... 215 5.3. Multiple Access Circular Queue .................................................... 217 5.4. Using the Z-Transform to Derive Filter Response ....................... 220 5.5. IIR Filter Design Using the Pole-Zero Plot .................................... 224 5.6. Discrete Fourier Transform............................................................ 229 5.7. FIR Filter Design ............................................................................. 230 5.8. Direct-Form Implementations. ....................................................... 233 5.9. Exercises ......................................................................................... 235 5.10. Lab Assignments.......................................................................... 237 6. High-Speed Interfacing.......................................................................... 239 6.1. The Need for Speed ........................................................................ 239 6.2. High-Speed I/O Applications.......................................................... 240 6.3. General Approaches to High-Speed Interfaces............................ 242 6.3.1. Hardware FIFO ....................................................................................242 6.3.2. Dual Port Memory...............................................................................243 6.3.3. Bank-Switched Memory .....................................................................244 6.4. Fundamental Approach to DMA .................................................... 245 6.4.1. DMA Cycles .........................................................................................245 6.4.2. DMA Initiation.....................................................................................246 6.4.3. Burst versus Single Cycle DMA ........................................................246
Jonathan Valvano
6.4.4. Single Address versus Dual Address DMA .................................... 247 6.4.5. DMA programming on the LF4F120 ................................................ 250 6.5. Programming Flash EEPROM ....................................................... 253 6.6. Secure digital card interface.......................................................... 256 6.7. Camera Interface ............................................................................ 261 6.8. Exercises......................................................................................... 265 6.9. Lab Assignments............................................................................ 266 7. File system management ...................................................................... 267 7.1. Introduction..................................................................................... 267 7.2. File System Allocation ................................................................... 267 7.3. Simple File System ......................................................................... 271 7.4. File Allocation Table....................................................................... 273 7.5. Internal Fragmentation................................................................... 274 7.6. External Fragmentation.................................................................. 275 7.7. Exercises......................................................................................... 275 7.8. Lab Assignments............................................................................ 279 8. Interfacing Robotic Components ......................................................... 281 8.1. Input Capture or Input Edge Time Mode....................................... 281 8.1.1. Basic Principles .................................................................................... 281 8.1.2. Input Capture Details on the LM3S/LM4F ..................................... 284 8.1.3. Period Measurement........................................................................... 288 8.1.4. Pulse Width Measurement................................................................. 290 8.2. Output Compare or Periodic Timer ............................................... 291 8.3. Pulse Width Modulation ................................................................. 294 8.4. Binary Actuators............................................................................. 295 8.4.1. Electrical Interface ............................................................................... 295 8.4.2. DC Motor Interface with PWM ......................................................... 299 8.5. Sensors ........................................................................................... 303 8.6. Odometry......................................................................................... 306 9. High-Speed Networks............................................................................ 309
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9.1. Fundamentals ................................................................................. 309 9.2. Controller Area Network (CAN) ..................................................... 315 9.2.1. The Fundamentals of CAN ................................................................315 9.2.2. Stellaris LM3S/LM4F CAN................................................................318 9.3. Embedded Internet ......................................................................... 322 9.3.1. Abstraction ...........................................................................................322 9.3.2. Message Protocols ...............................................................................325 9.3.3. Ethernet Physical Layer ......................................................................327 9.3.4. Ethernet on the LM3S8962..................................................................329 9.4. Exercises ......................................................................................... 335 9.5. Lab Assignments............................................................................ 336 10. Robotic Systems.................................................................................. 337 10.1. Introduction to Digital Control Systems ..................................... 337 10.2. Simple Closed-Loop Control Systems........................................ 338 10.3. PID Controllers.............................................................................. 341 10.3.1. General Approach to a PID Controller...........................................341 10.3.2. Design Process for a PID Controller ...............................................345 10.4. Fuzzy Logic Control...................................................................... 349 10.5. Exercises ....................................................................................... 358 10.6. Lab Assignments.......................................................................... 360 Appendix 1. Glossary ................................................................................ 361 Appendix 2. Solutions to Checkpoints..................................................... 379 Index ........................................................................................................... 385 Reference Material ..................................................................................... 394
Volume 3 Second Edition
Jonathan W. Valvano
ii
Jonathan Valvano
Second edition
ARM and uVision are registered trademarks of ARM Limited. Cortex and Keil are trademarks of ARM Limited. Stellaris is a registered trademark Texas Instruments. Code Composer Studio is a trademark of Texas Instruments. All other product or service names mentioned herein are the trademarks of their respective owners.
In order to reduce costs, this college textbook has been self-published. For more information about my classes, my research, and my books, see http://users.ece.utexas.edu/~valvano/ For corrections and comments, please contact me at: [email protected]. Please cite this book as: J. W. Valvano, Embedded Systems: Real-Time Operating Systems for ARM® Cortex™-M Microcontrollers, Volume 3, http://users.ece.utexas.edu/~valvano/, ISBN: 978-1466468863. Copyright © 2012 Jonathan W. Valvano All rights reserved. No part of this work covered by the copyright herein may be reproduced, transmitted, stored, or used in any form or by any means graphic, electronic, or mechanical, including but not limited to photocopying, recording, scanning, digitizing, taping, web distribution, information networks, or information storage and retrieval, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without the prior written permission of the publisher. ISBN-13: 978-1466468863 ISBN-10: 1466468866
Jonathan Valvano
Table of Contents Preface to The Second Edition ................................................................. ix Preface to Volume 3................................................................................... x Acknowledgements ................................................................................... xi 1. Review of Computer Architecture ........................................................ 1 1.1. Embedded Systems........................................................................ 1 1.2. Computer Architecture................................................................... 2 1.2.1. Computers, processors, memory, and microcontrollers................ 2 1.2.2. Cortex™-M processor ......................................................................... 6 1.3. Cortex™-M Processor Architecture .............................................. 7 1.3.1. Registers................................................................................................ 7 1.3.2. Memory................................................................................................. 9 1.3.3. Stack....................................................................................................... 11 1.3.4. Operating modes ................................................................................. 13 1.3.5. Reset ...................................................................................................... 14 1.4. Stellaris® LM3S8962 I/O pins ........................................................ 14 1.4.1 Stellaris® LM3S8962 I/O pins............................................................ 15 1.4.2 Stellaris® LM3S2110 I/O pins............................................................ 19 1.4.3. Stellaris® LM4F120 LaunchPad I/O pins........................................ 20 1.5. ARM® Cortex™-M Assembly Language ....................................... 24 1.5.1. Syntax.................................................................................................... 25 1.5.2. Addressing modes and operands ..................................................... 26 1.5.3. Memory access instructions ............................................................... 29 1.5.4. Logical operations ............................................................................... 31 1.5.5. Shift operations .................................................................................... 32 1.5.6. Arithmetic operations ......................................................................... 34 1.5.7. Functions and control flow ................................................................ 37
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Jonathan Valvano
1.5.8. Stack usage ...........................................................................................41 1.5.9. Assembler directives ...........................................................................42 1.6. ARM® Cortex™ Microcontroller Software Interface Standard.... 43 1.7. Exercises ......................................................................................... 43 2. Design of I/O Interfaces ......................................................................... 45 2.1. Flowcharts....................................................................................... 45 2.2. Digital Logic and Open Collector .................................................. 48 2.3. Parallel I/O ports ............................................................................. 59 2.4. Phase-Lock-Loop............................................................................ 62 2.5. NVIC on the ARM® Cortex™-M Processor ................................... 63 2.6. SysTick Timer ................................................................................. 67 2.7. Edge-triggered Interfacing ............................................................. 70 2.8. Configuring Digital Output Pins .................................................... 74 2.9. UART Interface................................................................................ 75 2.9.1. Transmitting in asynchronous mode................................................77 2.9.2. Receiving in asynchronous mode .....................................................78 2.9.3. LM3S/LM4F UART Details ...............................................................79 2.9.4. UART device driver ............................................................................81 2.9.5. Interrupt-Driven UART......................................................................82 2.10. Synchronous Transmission and Receiving using the SSI........ 85 2.11. DAC Operation and Performance Measures .............................. 89 2.12 Analog to Digital Converters ........................................................ 93 2.12.1. ADC Parameters ................................................................................93 2.12.2. Internal ADC ......................................................................................95 2.13. Data Acquisition Systems............................................................ 99 2.14. Exercises ....................................................................................... 106 3. Software Design..................................................................................... 109 3.1. The Design Process ....................................................................... 110 3.1.1. Requirements document ....................................................................110 3.1.2. Top-down design.................................................................................111
Jonathan Valvano
3.2. Memory Management and the Heap.............................................. 117 3.2.1. Use of the Heap.................................................................................... 117 3.2.2. Simple Fixed-Size Heap...................................................................... 119 3.2.3. Memory Manager: malloc and free................................................... 121 3.3. Threads............................................................................................ 125 3.4. First In First Out Queue.................................................................. 131 3.4.1. Classical definition of a FIFO............................................................. 131 3.4.2. Two-pointer FIFO implementation................................................... 132 3.4.3. FIFO build macros............................................................................... 136 3.5. Interthread Communication and Synchronization....................... 138 3.6. Critical Sections ............................................................................. 145 3.7. Introduction to Debugging............................................................. 151 3.7.1. Debugging Tools ................................................................................. 151 3.7.2. Debugging Theory .............................................................................. 153 3.7.3. Functional Debugging ........................................................................ 155 3.7.4. Performance Debugging..................................................................... 158 3.7.5. Profiling ............................................................................................... 161 4. Real-Time Operating Systems .............................................................. 163 4.1. Fundamentals ................................................................................. 164 4.2. Round-Robin Scheduler................................................................. 171 4.3. Semaphores .................................................................................... 178 4.3.1. Spin-lock semaphore implementation ............................................. 178 4.3.2. Blocking semaphore implementation............................................... 181 4.4. Thread Synchronization and Communication ............................. 183 4.4.1. Thread synchronization or rendezvous ........................................... 183 4.4.2. Resource sharing, nonreentrant code or mutual exclusion........... 183 4.4.3. Thread communication between two threads using a mailbox ... 184 4.4.4. Thread communication between threads using a FIFO queue..... 185 4.4.5. Readers-Writers Problem ................................................................... 186 4.4.6. Switch Debouncing ............................................................................. 187
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4.4.7. Deadlocks..............................................................................................189 4.5. Monitors........................................................................................... 191 4.6. Fixed Scheduling ............................................................................ 193 4.7. OS Considerations for I/O Devices ............................................... 198 4.7.1 Board Support Package .......................................................................198 4.7.2 Path Expression.....................................................................................200 4.8. Exercises ......................................................................................... 202 4.9. Lab Assignments............................................................................ 207 5. Digital Signal Processing ...................................................................... 209 5.1. Basic Principles .............................................................................. 210 5.2. Audio Input/Output ......................................................................... 215 5.3. Multiple Access Circular Queue .................................................... 217 5.4. Using the Z-Transform to Derive Filter Response ....................... 220 5.5. IIR Filter Design Using the Pole-Zero Plot .................................... 224 5.6. Discrete Fourier Transform............................................................ 229 5.7. FIR Filter Design ............................................................................. 230 5.8. Direct-Form Implementations. ....................................................... 233 5.9. Exercises ......................................................................................... 235 5.10. Lab Assignments.......................................................................... 237 6. High-Speed Interfacing.......................................................................... 239 6.1. The Need for Speed ........................................................................ 239 6.2. High-Speed I/O Applications.......................................................... 240 6.3. General Approaches to High-Speed Interfaces............................ 242 6.3.1. Hardware FIFO ....................................................................................242 6.3.2. Dual Port Memory...............................................................................243 6.3.3. Bank-Switched Memory .....................................................................244 6.4. Fundamental Approach to DMA .................................................... 245 6.4.1. DMA Cycles .........................................................................................245 6.4.2. DMA Initiation.....................................................................................246 6.4.3. Burst versus Single Cycle DMA ........................................................246
Jonathan Valvano
6.4.4. Single Address versus Dual Address DMA .................................... 247 6.4.5. DMA programming on the LF4F120 ................................................ 250 6.5. Programming Flash EEPROM ....................................................... 253 6.6. Secure digital card interface.......................................................... 256 6.7. Camera Interface ............................................................................ 261 6.8. Exercises......................................................................................... 265 6.9. Lab Assignments............................................................................ 266 7. File system management ...................................................................... 267 7.1. Introduction..................................................................................... 267 7.2. File System Allocation ................................................................... 267 7.3. Simple File System ......................................................................... 271 7.4. File Allocation Table....................................................................... 273 7.5. Internal Fragmentation................................................................... 274 7.6. External Fragmentation.................................................................. 275 7.7. Exercises......................................................................................... 275 7.8. Lab Assignments............................................................................ 279 8. Interfacing Robotic Components ......................................................... 281 8.1. Input Capture or Input Edge Time Mode....................................... 281 8.1.1. Basic Principles .................................................................................... 281 8.1.2. Input Capture Details on the LM3S/LM4F ..................................... 284 8.1.3. Period Measurement........................................................................... 288 8.1.4. Pulse Width Measurement................................................................. 290 8.2. Output Compare or Periodic Timer ............................................... 291 8.3. Pulse Width Modulation ................................................................. 294 8.4. Binary Actuators............................................................................. 295 8.4.1. Electrical Interface ............................................................................... 295 8.4.2. DC Motor Interface with PWM ......................................................... 299 8.5. Sensors ........................................................................................... 303 8.6. Odometry......................................................................................... 306 9. High-Speed Networks............................................................................ 309
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Jonathan Valvano
9.1. Fundamentals ................................................................................. 309 9.2. Controller Area Network (CAN) ..................................................... 315 9.2.1. The Fundamentals of CAN ................................................................315 9.2.2. Stellaris LM3S/LM4F CAN................................................................318 9.3. Embedded Internet ......................................................................... 322 9.3.1. Abstraction ...........................................................................................322 9.3.2. Message Protocols ...............................................................................325 9.3.3. Ethernet Physical Layer ......................................................................327 9.3.4. Ethernet on the LM3S8962..................................................................329 9.4. Exercises ......................................................................................... 335 9.5. Lab Assignments............................................................................ 336 10. Robotic Systems.................................................................................. 337 10.1. Introduction to Digital Control Systems ..................................... 337 10.2. Simple Closed-Loop Control Systems........................................ 338 10.3. PID Controllers.............................................................................. 341 10.3.1. General Approach to a PID Controller...........................................341 10.3.2. Design Process for a PID Controller ...............................................345 10.4. Fuzzy Logic Control...................................................................... 349 10.5. Exercises ....................................................................................... 358 10.6. Lab Assignments.......................................................................... 360 Appendix 1. Glossary ................................................................................ 361 Appendix 2. Solutions to Checkpoints..................................................... 379 Index ........................................................................................................... 385 Reference Material ..................................................................................... 394
