Enhanced Analytic Noise Model for RF CMOS ... - Semantic Scholar
Enhanced Analytic Noise Model for RF CMOS Design Jim Koeppe and Ramesh Harjani Department of Electrical & Computer Engineering, University of Minnesota Minneapolis, MN 55455 Abstract
Minimum Noise Figure Measured
Basic Noise Model
4
10*log NFMIN
In this paper we develop a simple physics based noise model for short channel RF CMOS devices that is targeted towards analytic hand calculations but is easily incorporated into a circuit simulator. Classical CMOS transistor noise theory set forth by A. Van der Zeil is combined with more recent noise studies. A novel de-embedding technique is used to extract experimental noise parameter results that confirm the model’s accuracy from 2-20 GHz for 0.18µ length devices in the TSMC CMOS process. While some authors have assumed a fixed excess noise factor (γ) for predicting RF noise at a particular channel length, we show here that γ is sensitive to both device bias and process parameters and cannot be assumed constant for fixed channel length.
3
2
1
0 0
Introduction As CMOS minimum process lengths have shrunk below one micron, parasitic electric fields and velocity saturation, normally ignored at longer lengths, strongly influence device characteristics. In particular, the noise from a sub-micron gate length transistor can far exceed the noise produced by its long channel counterparts [2-6,11-12]. Recently, Scholten et al., have demonstrated the ability to model noise in RF CMOS short-channel devices effectively [12]. However, their segmented model is rather complex and leaves designers at a loss when doing hand calculations. The model we propose is based on the classical noise modeling approach by Van der Zeil [1] and gives designers a powerful tool for hand calculations to predict noise performance. 2. RF CMOS Noise Model 2.1 General Model Overview The standard CMOS low frequency, long channel noise model drastically underestimates noise for short-channel devices operating at moderate to high frequencies [4,5,11]. This is illustrated in Figure 1 where we compare the minimum noise figure of a single 0.18µm NMOS device predicted by a standard simulator and measured results. The standard BSIM3v3 model used in simulation, predicts the minimum noise figure to be 0.7-1.5 dB lower than what measurements indicate. Clearly, the standard noise model fails to accurately predict noise performance for shortchannel devices at RF frequencies. In this section we outline a method to scale the standard long channel MOSFET noise model to RF frequencies for sub-
5
10
15
20
Frequency (GHz)
Fig 1: Typical simulation noise versus measured data micron devices. The method is analytical and simple and is targeted for designers performing hand calculations but is easily included in a simulation tool. The dominant noise contributors in short-channel CMOS devices at radio frequencies are channel thermal noise, induced gate noise, and parasitic gate and bulk resistance. The parasitic gate and substrate resistance due to finite sheet resistance of the semiconductor materials can add to the overall noise floor of the MOSFET at high frequencies and if overlooked can easily become the dominant noise contributor for the device [9-12]. The designer can minimize these resistances by scaling the aspect ratio, adding fingers to the gate, and by contacting both ends of each finger of the transistor. A detailed discussion of layout optimization to minimize gate resistance is given in [12]. 2.3 Channel Thermal Noise The thermal noise in the channel of a MOSFET device can be expressed according to Equation 1 [1].
I n2 = 4kTγgdo
(1)
For long channel devices, the excess noise factor (γ) is 2/3. However, for short channel devices this factor can be considerably higher [2-6,11,12]. Van der Ziel derived an equation for γ based on device bias conditions, device channel length (L), and device critical electric field (Ec) assuming electron temperature is proportional to the square of electric field strength [1].
y=
Vgs − Vt Ec ⋅ L
=
∆V
z=
Ec ⋅ L
Vdst
(2)
Ec ⋅ L
closely correlated to the excess noise factor. Therefore, the induced gate noise is also a function of channel length, bias conditions, and process parameters.
In the original analysis γ is provided in terms of y and z as shown in Equation 2. Note that y and z are defined in terms of device bias conditions, critical E-field, and device channel length. Van der Zeil’s final equation is shown in Equation 3. 1−
γ =
z y
+
1−
1 z
3 y 1 z
2
(3)
(1 + 2 y )
2 y
We can recast the excess noise factor equation above using a more familiar set of terms. In particular, if we use the set of relationships given in Equation 2 and Equation 4 we can rewrite Equation 3 to that shown in Equation 5. Ec =
vsat
µo
Vdst z b= = ∆V y
(4)
Here γ is a function of the device overdrive voltage (∆V), process parameters (µο, vsat), channel length (L), and the ratio (b = Vdst/∆V) caused by short channel effects. We note that γ become equal to 2/3 for b=1 and ∆V 2γ [12]. Therefore, this may account for the noise figure discrepancy at lower frequencies. M easured
Basic Noise M odel
RF Noise M odel
Minimum Noise Figure (dB)
4
Fig 3: Die photo of probed test structure for 0.18µm device a a S12 S 21Γopt a Γopt ' = S 22 + a 1 − S11Γopt
(8)
Figure 4 compares measured data both before and after deembedding with simulated models using process parameters directly from the foundry. There is a difference in both the gain and phase of the optimum noise reflection coefficient. However, we only present the phase information here due to space limitations. Without de-embedding the optimum noise reflection coefficient, designers will inevitably miscalculate the optimum noise match for the device and thereby increase the minimum noise figure that can be achieved.
2 1 0 0
5
10
15
20
Frequency (GHz)
Fig 5: Enhanced Van der Zeil RF model, standard model vs. measured data 4. APPLICATIONS AND DESIGN
In this section we consider the design implications as a result of a better understanding of the thermal noise for short channel devices. In particular, let us consider the graphs in Fig 6. Here we have plotted the measured Rn (equivalent gate-referred noise resistance) for a 0.18µm device, a 1.0µm device and the simulated Rn for the 0.18µm device assuming a fixed γ of 2/3 vs Ids. All devices have a fixed width =148µm broken up into 30 fingers.
M easured wit h de-embedding M easured no de-embedding Simulat ed wit h TSM C process dat a
140 120 100 80 60
Rn (1.0u)
40
Rn (0.18u)
Rn (0.18u [gamma=2/3])
160
20 0 0
5
10 15 Frequency (GHz)
20
Fig 4: Impact of de-embedding noise parameters 3.2 Measurement Comparison with RF Noise Model Minimum noise figure is the most transparent metric when evaluating the accuracy of simulation noise models. The enhanced Van der Ziel model presented here was embedded in the Cadence SpectreRF simulator [15] and used to predict the minimum noise figure. The measured results for minimum noise figure from 2-20GHz are plotted for a 0.18µm NMOS device and compared to both the standard BSIM3v3 model and the enhanced Van der Zeil noise model in Figure 5.The BSIM noise model is overly optimistic when
120 Rn (ohm)
Optimum Noise Reflection Phase (degrees)
3
80 40 0 0.5
1
2
5 10 Ids (m A)
18
25
50
Fig 6: Measured Rn for 0.18µm, 1.0µm & Rn for fixed γ =2/3 We note that, not surprisingly the Rn decreases with increased Ids. This is because the effective gdo increases roughly as the square-root of current. However, we note that the Rn for the 0.18µm device starts to once again increase as
For example, in Figure 7, the excess noise factor is plotted for various overdrive voltages based on the same TSMC 0.18µm run. Note that γ is a strong function of the overdrive voltage. In this case, the noise increases about 50% for a 0.18 micron device when the overdrive voltage is increased from 0.1V to 0.5V. L := 0.1⋅ u , 0.2⋅ u .. 10⋅ u
1.6 1.5
L := 0.1⋅ u , 0.2⋅ u .. 10⋅ u
L = 0.18um γmin=1.1 γmax=1.3
1.4 Excess noise factor
we increase Ids. For comparison purposes we have also plotted the simulated Rn using a typical TSMC 0.18µm process run and assuming a fixed γ of 2/3. This choice of γ may be on the low side however using a larger value for γ would only move the graph up or down. It would not alter its shape. The only explanation is that γ increases with increased ∆V. This is in fact predicted by Equation 5.
1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.1
1 Channel length (um)
Fig 8: Excess noise factor (γ) change due to process variations in mobility (µο) and saturation velocity (vsat)
1.5
1.3 Excess noise factor
Improvements are added to van der Zeil’s work based on recent noise studies, new process technology, and measurements done by the authors. We have shown that the excess noise factor (γ) is very sensitive to both device bias and process parameters and should not be assumed to be constant for a fixed channel length.
∆V = 0.5
1.4
∆V = 0.3
1.2 1.1
∆V = 0.1
1 0.9 0.8
6. REFERENCES
0.7
γ = 2/3
0.6 0.5
0.1
1 Channel length (um)
Fig 7: Excess noise factor (γ) for different overdrive voltages (∆V) for the TSMC 0.18µm RF process In addition to bias conditions, process parameters can significantly influence device noise. Engineers are accustomed to putting margins into their designs to account for process variation for device mismatch. However, most don’t consider that in addition to device mismatch, for high performance low noise circuits, margins should be built into designs to account for noise variation due to process mismatch. To illustrate this point, 10 different process runs for the TSMC 0.18 micron process were analyzed [19]. Plotting the minimum, maximum, and mean noise (Fig. 8) for those circuits, there can be a 10% change in device noise for a 0.18µm device due solely due to random process variations. We also note that the impact of process variations increase with gate overdrive voltage. 5. CONCLUSIONS
In this paper we developed a RF CMOS noise model that accounts for process variation, bias conditions, and device sizing that is valid for frequencies approaching 20 GHz. The physics based model is simple enough to be used for hand calculations and can be implemented in any circuit simulator. The model is an enhancement of the fundamental CMOS transistor noise theory set forth by A. van der Zeil [1].
[1] A. van der Ziel, “Thermal noise in field-effect transistors,” Proc. IRE, vol. 50, pp.1808-1812, August 1962. [2] A. A. Abidi, “High-frequency noise measurements on FET’s with small dimensions,” IEEE Trans. Electron Devices, pp. 1801-1805, Nov. 1986. [3] R.P. Jindal, “Hot-electron effects on channel thermal noise in fineline NMOS field-effect transistors,” IEEE Trans. Electron Devices, vol. ED33, pp. 1395-1397, Sept. 1986. [4] S. Tedja, J. Van der Spiegel, and H. H. Williams, “Analytical and experimental studies of thermal noise in MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, pp. 2069-2075, Nov. 1994. [5] B. Wang, J.R. Hellums, and C.G. Sodini, “MOSFET thermal noise modeling for analog integrated circuits,” IEEE J. Solid-State Circuits, vol. 29, pp. 833-835, July 1994. [6] D. P. Triantis, A. N. Birbas, and D. Kondis, “Thermal noise modeling for short-channel MOSFET’s,” IEEE Trans. Electron Devices, Nov. 1996. [7] Y. Tsividis, Operation and Modeling of The MOS Transistor-Second Edition, McGraw-Hill, 1999. [8] D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley, 1997. [9] B. Razavi, R. Yan, and K. Lee, “Impact of distributed gate resistance on the performance of MOS devices,” IEEE Trans. Circuits and Systems, vol. 41, no. 11, pp. 750-754, Nov. 1994. [10] R.P. Jindal, “Distrubuted Substrate Resistance Noise in Fine-Line NMOS Field-Effect Transistors,” IEEE Trans. Electron Devices, vol. ED32, pp. 2450-2453, Nov. 1985. [11] D. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, May 1997. [12] A. Scholten, L. Tiemeijer, R. vsn Langevelde, R. Havens, A. Zegers-van Duijnhoven, and V. Venezia “Noise modeling for RF CMOS circuit simulation,” IEEE Transactions on Electron Devices, vol. 50, no. 3, March 2003. [13] M. Steer et al., “Introducing the through-line deembedding procedure,” IEEE MTT-S, pp. 1455-1458, 1992. [14] G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design 2nd Edition, Prentice Hall, 1997. [15] Cadence Incorporated: www.cadence.com [16] Zeevo Incorporated: www.zeevo.com [17] RFMD Incorporated: www.rfmd.com [18] Bermai Incorporated: www.bermai.com [19] MOSIS website www.mosis.org
Minimum Noise Figure Measured
Basic Noise Model
4
10*log NFMIN
In this paper we develop a simple physics based noise model for short channel RF CMOS devices that is targeted towards analytic hand calculations but is easily incorporated into a circuit simulator. Classical CMOS transistor noise theory set forth by A. Van der Zeil is combined with more recent noise studies. A novel de-embedding technique is used to extract experimental noise parameter results that confirm the model’s accuracy from 2-20 GHz for 0.18µ length devices in the TSMC CMOS process. While some authors have assumed a fixed excess noise factor (γ) for predicting RF noise at a particular channel length, we show here that γ is sensitive to both device bias and process parameters and cannot be assumed constant for fixed channel length.
3
2
1
0 0
Introduction As CMOS minimum process lengths have shrunk below one micron, parasitic electric fields and velocity saturation, normally ignored at longer lengths, strongly influence device characteristics. In particular, the noise from a sub-micron gate length transistor can far exceed the noise produced by its long channel counterparts [2-6,11-12]. Recently, Scholten et al., have demonstrated the ability to model noise in RF CMOS short-channel devices effectively [12]. However, their segmented model is rather complex and leaves designers at a loss when doing hand calculations. The model we propose is based on the classical noise modeling approach by Van der Zeil [1] and gives designers a powerful tool for hand calculations to predict noise performance. 2. RF CMOS Noise Model 2.1 General Model Overview The standard CMOS low frequency, long channel noise model drastically underestimates noise for short-channel devices operating at moderate to high frequencies [4,5,11]. This is illustrated in Figure 1 where we compare the minimum noise figure of a single 0.18µm NMOS device predicted by a standard simulator and measured results. The standard BSIM3v3 model used in simulation, predicts the minimum noise figure to be 0.7-1.5 dB lower than what measurements indicate. Clearly, the standard noise model fails to accurately predict noise performance for shortchannel devices at RF frequencies. In this section we outline a method to scale the standard long channel MOSFET noise model to RF frequencies for sub-
5
10
15
20
Frequency (GHz)
Fig 1: Typical simulation noise versus measured data micron devices. The method is analytical and simple and is targeted for designers performing hand calculations but is easily included in a simulation tool. The dominant noise contributors in short-channel CMOS devices at radio frequencies are channel thermal noise, induced gate noise, and parasitic gate and bulk resistance. The parasitic gate and substrate resistance due to finite sheet resistance of the semiconductor materials can add to the overall noise floor of the MOSFET at high frequencies and if overlooked can easily become the dominant noise contributor for the device [9-12]. The designer can minimize these resistances by scaling the aspect ratio, adding fingers to the gate, and by contacting both ends of each finger of the transistor. A detailed discussion of layout optimization to minimize gate resistance is given in [12]. 2.3 Channel Thermal Noise The thermal noise in the channel of a MOSFET device can be expressed according to Equation 1 [1].
I n2 = 4kTγgdo
(1)
For long channel devices, the excess noise factor (γ) is 2/3. However, for short channel devices this factor can be considerably higher [2-6,11,12]. Van der Ziel derived an equation for γ based on device bias conditions, device channel length (L), and device critical electric field (Ec) assuming electron temperature is proportional to the square of electric field strength [1].
y=
Vgs − Vt Ec ⋅ L
=
∆V
z=
Ec ⋅ L
Vdst
(2)
Ec ⋅ L
closely correlated to the excess noise factor. Therefore, the induced gate noise is also a function of channel length, bias conditions, and process parameters.
In the original analysis γ is provided in terms of y and z as shown in Equation 2. Note that y and z are defined in terms of device bias conditions, critical E-field, and device channel length. Van der Zeil’s final equation is shown in Equation 3. 1−
γ =
z y
+
1−
1 z
3 y 1 z
2
(3)
(1 + 2 y )
2 y
We can recast the excess noise factor equation above using a more familiar set of terms. In particular, if we use the set of relationships given in Equation 2 and Equation 4 we can rewrite Equation 3 to that shown in Equation 5. Ec =
vsat
µo
Vdst z b= = ∆V y
(4)
Here γ is a function of the device overdrive voltage (∆V), process parameters (µο, vsat), channel length (L), and the ratio (b = Vdst/∆V) caused by short channel effects. We note that γ become equal to 2/3 for b=1 and ∆V 2γ [12]. Therefore, this may account for the noise figure discrepancy at lower frequencies. M easured
Basic Noise M odel
RF Noise M odel
Minimum Noise Figure (dB)
4
Fig 3: Die photo of probed test structure for 0.18µm device a a S12 S 21Γopt a Γopt ' = S 22 + a 1 − S11Γopt
(8)
Figure 4 compares measured data both before and after deembedding with simulated models using process parameters directly from the foundry. There is a difference in both the gain and phase of the optimum noise reflection coefficient. However, we only present the phase information here due to space limitations. Without de-embedding the optimum noise reflection coefficient, designers will inevitably miscalculate the optimum noise match for the device and thereby increase the minimum noise figure that can be achieved.
2 1 0 0
5
10
15
20
Frequency (GHz)
Fig 5: Enhanced Van der Zeil RF model, standard model vs. measured data 4. APPLICATIONS AND DESIGN
In this section we consider the design implications as a result of a better understanding of the thermal noise for short channel devices. In particular, let us consider the graphs in Fig 6. Here we have plotted the measured Rn (equivalent gate-referred noise resistance) for a 0.18µm device, a 1.0µm device and the simulated Rn for the 0.18µm device assuming a fixed γ of 2/3 vs Ids. All devices have a fixed width =148µm broken up into 30 fingers.
M easured wit h de-embedding M easured no de-embedding Simulat ed wit h TSM C process dat a
140 120 100 80 60
Rn (1.0u)
40
Rn (0.18u)
Rn (0.18u [gamma=2/3])
160
20 0 0
5
10 15 Frequency (GHz)
20
Fig 4: Impact of de-embedding noise parameters 3.2 Measurement Comparison with RF Noise Model Minimum noise figure is the most transparent metric when evaluating the accuracy of simulation noise models. The enhanced Van der Ziel model presented here was embedded in the Cadence SpectreRF simulator [15] and used to predict the minimum noise figure. The measured results for minimum noise figure from 2-20GHz are plotted for a 0.18µm NMOS device and compared to both the standard BSIM3v3 model and the enhanced Van der Zeil noise model in Figure 5.The BSIM noise model is overly optimistic when
120 Rn (ohm)
Optimum Noise Reflection Phase (degrees)
3
80 40 0 0.5
1
2
5 10 Ids (m A)
18
25
50
Fig 6: Measured Rn for 0.18µm, 1.0µm & Rn for fixed γ =2/3 We note that, not surprisingly the Rn decreases with increased Ids. This is because the effective gdo increases roughly as the square-root of current. However, we note that the Rn for the 0.18µm device starts to once again increase as
For example, in Figure 7, the excess noise factor is plotted for various overdrive voltages based on the same TSMC 0.18µm run. Note that γ is a strong function of the overdrive voltage. In this case, the noise increases about 50% for a 0.18 micron device when the overdrive voltage is increased from 0.1V to 0.5V. L := 0.1⋅ u , 0.2⋅ u .. 10⋅ u
1.6 1.5
L := 0.1⋅ u , 0.2⋅ u .. 10⋅ u
L = 0.18um γmin=1.1 γmax=1.3
1.4 Excess noise factor
we increase Ids. For comparison purposes we have also plotted the simulated Rn using a typical TSMC 0.18µm process run and assuming a fixed γ of 2/3. This choice of γ may be on the low side however using a larger value for γ would only move the graph up or down. It would not alter its shape. The only explanation is that γ increases with increased ∆V. This is in fact predicted by Equation 5.
1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.1
1 Channel length (um)
Fig 8: Excess noise factor (γ) change due to process variations in mobility (µο) and saturation velocity (vsat)
1.5
1.3 Excess noise factor
Improvements are added to van der Zeil’s work based on recent noise studies, new process technology, and measurements done by the authors. We have shown that the excess noise factor (γ) is very sensitive to both device bias and process parameters and should not be assumed to be constant for a fixed channel length.
∆V = 0.5
1.4
∆V = 0.3
1.2 1.1
∆V = 0.1
1 0.9 0.8
6. REFERENCES
0.7
γ = 2/3
0.6 0.5
0.1
1 Channel length (um)
Fig 7: Excess noise factor (γ) for different overdrive voltages (∆V) for the TSMC 0.18µm RF process In addition to bias conditions, process parameters can significantly influence device noise. Engineers are accustomed to putting margins into their designs to account for process variation for device mismatch. However, most don’t consider that in addition to device mismatch, for high performance low noise circuits, margins should be built into designs to account for noise variation due to process mismatch. To illustrate this point, 10 different process runs for the TSMC 0.18 micron process were analyzed [19]. Plotting the minimum, maximum, and mean noise (Fig. 8) for those circuits, there can be a 10% change in device noise for a 0.18µm device due solely due to random process variations. We also note that the impact of process variations increase with gate overdrive voltage. 5. CONCLUSIONS
In this paper we developed a RF CMOS noise model that accounts for process variation, bias conditions, and device sizing that is valid for frequencies approaching 20 GHz. The physics based model is simple enough to be used for hand calculations and can be implemented in any circuit simulator. The model is an enhancement of the fundamental CMOS transistor noise theory set forth by A. van der Zeil [1].
[1] A. van der Ziel, “Thermal noise in field-effect transistors,” Proc. IRE, vol. 50, pp.1808-1812, August 1962. [2] A. A. Abidi, “High-frequency noise measurements on FET’s with small dimensions,” IEEE Trans. Electron Devices, pp. 1801-1805, Nov. 1986. [3] R.P. Jindal, “Hot-electron effects on channel thermal noise in fineline NMOS field-effect transistors,” IEEE Trans. Electron Devices, vol. ED33, pp. 1395-1397, Sept. 1986. [4] S. Tedja, J. Van der Spiegel, and H. H. Williams, “Analytical and experimental studies of thermal noise in MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, pp. 2069-2075, Nov. 1994. [5] B. Wang, J.R. Hellums, and C.G. Sodini, “MOSFET thermal noise modeling for analog integrated circuits,” IEEE J. Solid-State Circuits, vol. 29, pp. 833-835, July 1994. [6] D. P. Triantis, A. N. Birbas, and D. Kondis, “Thermal noise modeling for short-channel MOSFET’s,” IEEE Trans. Electron Devices, Nov. 1996. [7] Y. Tsividis, Operation and Modeling of The MOS Transistor-Second Edition, McGraw-Hill, 1999. [8] D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley, 1997. [9] B. Razavi, R. Yan, and K. Lee, “Impact of distributed gate resistance on the performance of MOS devices,” IEEE Trans. Circuits and Systems, vol. 41, no. 11, pp. 750-754, Nov. 1994. [10] R.P. Jindal, “Distrubuted Substrate Resistance Noise in Fine-Line NMOS Field-Effect Transistors,” IEEE Trans. Electron Devices, vol. ED32, pp. 2450-2453, Nov. 1985. [11] D. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, no. 5, May 1997. [12] A. Scholten, L. Tiemeijer, R. vsn Langevelde, R. Havens, A. Zegers-van Duijnhoven, and V. Venezia “Noise modeling for RF CMOS circuit simulation,” IEEE Transactions on Electron Devices, vol. 50, no. 3, March 2003. [13] M. Steer et al., “Introducing the through-line deembedding procedure,” IEEE MTT-S, pp. 1455-1458, 1992. [14] G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design 2nd Edition, Prentice Hall, 1997. [15] Cadence Incorporated: www.cadence.com [16] Zeevo Incorporated: www.zeevo.com [17] RFMD Incorporated: www.rfmd.com [18] Bermai Incorporated: www.bermai.com [19] MOSIS website www.mosis.org
