Evaluation of Granularity on Threshold Voltage Control in Flex Power ...
Evaluation of Granularity on Threshold Voltage Control in Flex Power FPGA Masakazu Hioki∗ , Takashi Kawanami∗ , Toshiyuki Tsutsumi† , Tadashi Nakagawa∗ , Toshihiro Sekigawa∗ and Hanpei Koike∗ ∗ National
Institute of Advanced Industrial Science and Technology (AIST) Email:{m.hioki, t-kawanami, nakagawa.tadashi, t-sekigawa, h.koike}@aist.go.jp † Department of Computer Science, School of Science and Technology, Meiji University Email:[email protected]
Abstract— The Flex Power FPGA can flexibly control speed and power in a trade-off relationship by a flexible assignment of proper threshold voltage generated from body-bias units to transistors. This paper evaluates static power consumption and an area-overhead by the body-bias units on various threshold voltage control granularity in the Flex Power FPGA. There is also a trade-off relationship between the static power consmption and the area-overhead for granular control of the threshold voltages. Both a grain size and its style of division have a strong influence on the trade-off. Own evaluation results show that static power reduces less than 1/5 of original level, while increase an area overhead of less than 40%. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained.
I. Introduction Field Programmable Gate Array (FPGA) is a hardware technology that provides flexible functionality through software. However, due to the wider flexibility produced by this device, the FPGA incurs significant circuit redundancy, resulting in larger circuit area, lower operating speeds and larger power consumption compared with the ASICs. Power consumption of current CMOS integrated circuits increases dramatically due to increase in static power, primarily related to sub-threshold leakage current and gate leakage current. Especially, as the sub-threshold leakage current increases with the technology scaling, the proportion of static power in the total power consumption of CMOS integrated circuits has increased rapidly year after year [1]. For FPGAs in particular, which contain large proportion of unused transistors that doesn’t compose logic elements, the increase in static power is even more serious. Several recent studies have examined reduction of the static power in FPGAs. The static power is reduced by using the pre-defined (fixed) high-threshold voltage transistors in several circuits such as configuration SRAMs where highspeed operation is not required [2], [3]. Since the circuit utilization rate is typically low in FPGAs, significant static power reduction is expected by isolating the unused circuit blocks from the power supply, i.e. power gating method [4], [5], [6], [7], [8]. Static power reduction by these methods is, however, rather limited, since used logic blocks, which are source of unnecessarily large static power, are left unchanged.
0-7803-9729-0/06/$20.00 2006 IEEE
High threshold voltage: Low threshold Drain current (log scale) voltage: Small leakage Ion current, but Large On Small On current, but current. Large leakage Ioff (Powercurrent as well. Oriented) (SpeedThreshold voltage Vth Oriented)
Voff
Von
Gate voltage
Voltage swing Fig. 1. Comparison of Id-Vg characteristics of MOS transistors with different threshold voltages
Flex Power FPGA has been proposed as an FPGA with the electrical adjustment method of threshold voltage by appling the bias voltage to the body of transistor to control the subthreshold leakage current [9]. Raising the threshold voltage of the transistor results in exponential reduction in the subthreshold leakage current at the expense of transistor operating speed in a trade-off relationship. It is expected that configuring the trade-off between speed and power in the circuit blocks makes it possible to control the static power flexibly, resulting in further reduction in power consumption. Many design issues should be discussed for the optimal Flex Power FPGA, such as: • The implementation of threshold voltage control (body bias, double-gate transistor...). • The granularity of the circuit for which independent threshold voltage control is applied. • Selection of the threshold voltage values. • The number of threshold voltage control steps. • The power-mapping algorithm. This paper reports the investigation and evaluation of the second item, granularity of the circuit within which identical threshold voltage is assinged. II. Flex Power FPGA Figure 1 shows the Id-Vg characteristics for MOS transistors with various threshold voltages. An on-state current of a
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FPT 2006
Routing channel
Circuit configuration register
Logic block
Power configuration register
Power configuration registers are added.
Control line to well
Threshold voltage control circuit
Power configuration register Control line to second gate
(a)
Threshold voltage control circuit
(b)
Fig. 4. Threshold voltage control configuration in (a)Bulk MOS transistor and (b)XMOS transistor Power configuration register
Power configuration register
Power configuration register
Power configuration register
Margin between transistor area and well
Fig. 2.
Margin between wells
Flex Power FPGA
Low Vt
Flex Power FPGA
Well bias voltage selector switch
Power configuration register
Fig. 5. Area overhead based on electrical threshold voltage control
High Vt
Critical path
Fig. 3. Assignments of low and high threshold voltage values in the Flex Power FPGA
transistor is increased by reducing its threshold voltage so that the transistor operates at high speed, but its static power consumption increases. Conversely, static power consumption can be reduced by increasing threshold voltage, but this causes the operating speed to drop. Flex Power FPGA has a threshold voltage adjustment function for each configuration circuit in order to flexibly adjust this trade-off relationship. As shown in Fig. 2, in addition to the configuration register for circuit configuration found in conventional FPGAs, the Flex Power FPGA has power configuration registers that records the threshold voltage setting information. This allows Flex Power FPGA to reconfigure the circuit itself, as well as the power consumption and operating speed. Flex Power FPGA assigns low- and high-threshold voltage to transistors through threshold voltage configuration circuits by setting appropriate values to the power configuration registers based on the analysis of the circuit (Fig. 3). A lowthreshold voltage is assigned to transistors on critical paths, which determine the operating speed of the circuit. Using a low threshold value increases the drive capability and operating speed of the transistor, thereby reducing critical path delay and improving the operating frequency. A high threshold value is set for transistors on paths except critical paths. the transistors
don’t have a influence on the operating frequency of the chip though operating speed of the transistors becomes slow. On the other hand, assignment of high threshold value for the transistors decreases subthreshold leakage current of the transistors because of the trade-off relatinship as shown in Fig. 1. Since such paths except critical paths comprise nearly 90% of the total signal paths, this makes it possible to reduce unnecessary static power consumption without reducing the operating speed. An evaluation tool called Flex Power VPR was developed [10]. The effectiveness of Flex Power FPGA in reducing static power consumption and controlling the operating speed were reported previously [9], [10], [11].
LUT
IBUF IMUX LBUF
DFF OMUX
BLE BLE BLE BLE CMUX
CLB Fig. 6.
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CLB: CMUX: CBUF: IBUF: IMUX: LBUF: BLE: LUT: DFF: OMUX:
Configurable logic block Multiplexer for CLB input Tri-state buffer for CLB output Buffer for CLB input Multiplexer for BLE input Local routing buffer Basic logic element Lookup table D flip flop Multiplexer for BLE output
CBUF The schematic of configurable logic block
III. Trade-off in threshold voltage control granularity
IV. Evaluation on the threshold voltage Control Granularity As indicated in Section 3, there is a trade-off in threshold voltage control granularity between the area overhead and the static power consumption, and appropriate selections must be made. The static power consumption and area overhead in various threshold voltage control granularity are therefore evaluated based on specific settings in CLB of Flex Power FPGA. The procedure for evaluation is as follows. 1) Several division patterns for threshold voltage controlled transistor area are considered. 2) A representative critical path is set. 3) Static power consumption and area overhead are evaluated. Specific division patterns for the threshold voltage controlled transistor area in a CLB are set according to the policies described in Section 4. In the present evaluation, six division
Inner area of CLB
Input area
CLB CMUX
IBUF
Output area CBUF
LBUF
IMUX
LUT
A threshold voltage can be controlled electrically in two way; by applying bias voltage to the wells of the conventional bulk MOS transistors (Fig. 4(a)) [12], and through the use of a double-gate MOS transistor which originates XMOS (Fig. 4(b)). The XMOS has been proposed by one of the present authors in 1980, and has received much worldwide attention as a next-generation semiconductor device [13], [14], [15]. Flex Power FPGA is one of the candidates of the application for the XMOS transistor [16]. In this paper, to demonstrate effectiveness of granular control for the threshold voltages, the way of applying bias voltage to the wells of bulk MOS transistors is employed, which can be achieved with current technology. When the threshold voltage is adjusted electrically by applying well bias voltage, transistors to which the same bodybias is applied are arranged on a single well to separate ohter transistors. Therefore, the threshold voltage control granularity determines its area overhead. The area overhead occurs primarily as a result of the following factors: • Margin between a transistor area and an well • Margin between wells • Switches to select well bias voltage • Power configuration registers As shown in Fig. 5, with coarse control granularity, the area overhead stays small because many circuits can be arranged in a single well. However, it possibly happens that the threshold voltage is reduced even in the circuit resources which don’t need high-speed operation, and static power reduction is not satisfactory. Conversely, the threshold voltage can be adjusted independently for the various circuit resources with fine control granularity, achieving thorough reduction of the static power. However, the fine control granularity requires the separation of circuits with many wells, and a lot of selector switches and power configuration registers. These factors increase the area overhead.
Policy 3: Separately controlled
Policy 2: Separately controlled
OMUX DFF
BLE
Fig. 7.
Fig. 8. CLB
Policy 1: Collectively controlled
Policies for division of controlled transistor area
No control
1 division
5 divisions
25 divisions
30 divisions
84 divisions
Division patterns for threshold voltage controlled transistor areas in
patterns of the CLB for threshold voltage controlled transistor area are examined, as shown in Fig. 8. Areas in which the threshold voltage is controlled simultaneously are outlined. In the block marked "No control", no threshold voltage control is carried out. In the block showing one division, the threshold voltage is controlled for the entire CLB as a whole. In the block showing five divisions, the BLE inside the CLB and the IMUX, LBUF and CBUF connected to BLE are split off as one area, and the elements on the input side are treated as one area. In the block showing 25 divisions, the five divisions are broken down further, where the CMUX and IBUF on the input side and output side are divided into smaller areas. In the block showing 30 divisions, the divisions are even smaller than those of the 25-division block, with the CMUX and IBUF on the input side divided further into smaller areas. Finally, in the block showing 84 divisions, all of the elements configuring the CLB are divided into individual areas.
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Sqrt(xy)
y
Power config. memory Config. memory CBUF LBUF DFF OMUX LUT IMUX IBUF CMUX
1.2 x
1 Static power
Sqrt(xy) Area defined by VPR area model Additional area by the margins among diffusions and wells (a) Area increase by well separation
(b) Layout estimated to square of the same area as (a)
0.8 0.6 0.4 0.2
Fig. 9.
Extended area model
0 No 1 5 25 30 84 control division divisions divisions divisions divisions
A. Configurable Logic Block Figure 10 shows the results of the static power consumption evaluation. Without threshold voltage control, as in the blocks
Fig. 10.
Area overhead
A critical path considered to be representative is then set to pass through this CLB. We assume that the critical path passes through CMUX, IBUF, IMUX, LUT, OMUX and CBUF in order as indicated by the solid-line arrow in Fig. 8. It is thought that a very simple, straightforward assumption such as this would be adequate for the present evaluation because the preliminary evaluations have shown that the critical path comprises only a portion of all of the signal paths. Based on the above, the static power consumption is evaluated by combining the critical path and the division patterns for the threshold voltage controlled transistor areas. Threshold voltage control steps are two, low threshold value and a high threshold value. Well bias voltages Vbias nmos = 0V, −VDD and Vbias pmos = +VDD , +2VDD are applied to the wells for nmos and pmos, respetively to set the low- and high- threshold voltages. In Fig. 8, the low threshold voltage is assigned to circuits with areas through which the critical path passes, and these are indicated by a solid outline. The high threshold voltage is assigned to circuits areas through which the critical path does’t pass, and these are indicated by dotted outlines. A simulation of the static power consumption for various circuit components, such as CMUX, IBUF, etc, with two levels of threshold voltage is conducted using the SPICE [17] with a BPTM 70 nm transistor model [18] (UC Berkeley). The results of the SPICE simulation are used to evaluate the static power consumption of the CLB. To evaluate the area for the division patterns of the various threshold voltage controlled transistor areas, the extended area model reported in [19] is used (Fig. 9). This is generally performed as follows. The extended area model is a simple model in which the VPR area model [20] has been extended by adding margins between the wells and transistors, which are necessary in order to implement threshold voltage control by applying a well bias voltage. The margins between the wells themselves are also included. A square approximation is then applied to the area calculated by the conventional VPR area model to determine the length of one side. The increases resulting from the addition of well margins are then added and the result is squared to determine the area in which the well margins are included.
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0
Static power reduction for CLB
Well bias voltage selector switch Power config. Memory Amount of increase in well Config. Memory Logic
No 1 5 25 30 84 control division divisions divisions divisions divisions
Fig. 11. Area overhead for CLB
labeled "No control", a low threshold value is assigned to all of the transistors. In the one-division block, the threshold voltage of all transistors in the CLB is collectively controlled. Static power consumption is very much the same as that with no control because a low threshold voltage is assigned to all of the transistors in the CLB. However, when the FPGA as a whole is considered, the static power consumption of CLBs that are not used or are not within a critical path can be reduced. In comparison with the no-control block, the power consumption in the five-division block has been reduced by more than 60%. Treating each BLE inside the CLB and the elements connected to the BLE, that is IMUX, LBUF and CBUF, as an area for threshold voltage control is expected effective. The input and output buffer sections are further subdivided, as in the 25-division and 30-division blocks, the power consumption can be reduced by 80% from that with no control. If the threshold voltage controlled transistor areas are broken down even further, as in the 84-division block, into the minimum circuit units configuring the FPGA, the static power consumption can be reduced by more than 90%, but the area overhead will be extremely large, as discussed below. Figure 11 shows the results of area overhead evaluation. The area is expressed as the minimum number of transistors, and is standardized against the result for no control. As is indicated by the one-division block, when threshold control is
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FPGA Routing channel
Detailed circuit of routing switch
Switch block I/O pad
Power config. Memory Config. Memory Switch
1.2 1 Static power
Logic block
0.8 0.6 0.4 0.2
Fig. 12.
The schematic of switch block
0 No control 1 division
Fig. 14.
No control
1 division
96 divisions
Static power reduction for switch block
3
8 divisions
Area overhead
2.5
32 divisions
32 divisions
8 divisions
96 divisions
B. Switch Block The policies discussed in Section 4 for splitting the threshold voltage controlled transistor areas can also be applied to the FPGA switch blocks. In this section, the area and static power consumption of the switch blocks are evaluated for the five types of area divisions indicated in Fig. 13. In the switch blocks as shown in Fig. 12, the wires are connected by means of groups of switches in each of 12 tri-state buffers serve as routing switches, and signals propagate bidirectionally to any of wires. The switch blocks are composed of 8 switch groups, and there are a total of 96 tri-state buffers. In Fig.13, "No control" indicates that no threshold voltage control is applied, "1 division" indicates that threshold voltage control is carried out for all of the tri-state buffers in the switch block as a whole, "8 divisions" indicates threshold voltage control for each of the 8 switch groups, "32 divisions" indicates that threshold voltage control is carried out for three tri-state buffers with the common input wire as a group, and "96 divisions" indicates that the threshold voltage is controlled individually for the 96 tri-state buffers in the switch block. A simple critical path, just as in the CLB evaluation, is assumed as indicated by the solid arrow in Fig. 13.
1.5 1 0.5
Fig. 13. Division patterns for threshold voltage controlled transistor areas in switch blocks
implemented for the entire CLB as a whole, the area overhead is only 10%. As the threshold voltage controlled transistor areas are further broken down into 5, 25, and 30 divisions, the overhead increases to 20%, 35%, and 45%, respectively, and finally exceeds 80% when broken down to the smallest subdivision level of 84 divisions.
2
Well bias voltage selector switch Power config. Memory Amount of increase in well Config. Memory Switch
0 No control 1 division 8 divisions
32 divisions
96 divisions
Fig. 15. Area overhead for switch block
Figure 14 shows the results of the static power consumption evaluation. In the one-division block, no reduction is seen in static power consumption, similar to the case for CLB. However, this becomes important when evaluating the static power consumption in unused switch blocks and in used switch blocks outside of the critical path. If a switch block is divided into 8 segments, the static power consumption of the switch block can be reduced to 1/8 of the original level. This is because the threshold voltage of the 7 switch groups outside of the critical path can be set higher. Further subdividing into 32 divisions makes it possible to assign a high threshold value to the tri-state buffers (more efficiently than with 8 divisions), and the static power consumption can be reduced to 1/32. Breaking the switch block down even further into 96 divisions makes it possible to reduce the static power consumption to a level equivalent to that for a single tri-state buffer, but caution is required because this causes a dramatic increase in the area overhead. Figure 15 shows the results of the area overhead evaluation. The area increase in one division to no control is only 10%. Increasing the number of divisions to 8 and then to 32 increases the area overhead by 40% and 70%, respectively. With 96 divisions, where each tri-state buffer is controlled individually, the area is 2.5 times larger than when no threshold voltage control is applied.
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CLB
Critical path
1.2
0.8 0.6 0.4
Static power
1
0.2 No control 1 division 8 divisions 32 divisions Switch 96 divisions block
84
l ro nt co o n N io vis di s n 1 io vis s di on 5 si vi di s 25 on si vi di s 30 on si vi di
Finest granularity
Fig. 17. Fig. 16.
Logic block CLB
Static power reduction for FPGA tile
The schematic of FPGA tile and critical path
C. FPGA Tile
Finest granularity
s on si vi di s 84 on si vi di s 30 on si vi di 25 ns io vis di 5 n io vis di l ro nt co 1
o
96 divisions 32 divisions 8 divisions 1 division Switch No control block
N
The evaluation results for CLBs and switch blocks described in Sections 5.1 and 5.2 are used to evaluate the area overhead and static power consumption of the FPGA tile. Figure 16 shows the FPGA tile and the assumed critical path. The FPGA tile combines one CLB and one switch block considered in Sections 5.1 and 5.2. It is assumed that one critical path passes through a single tri-state buffer in the switch block and then passes through a CMUX, IBUF, IMUX, LUT, OMUX and OBUF in the CLB before exiting to external routing. This is a combination of the critical paths assumed in the CLB and switch block described in Sections 5.1 and 5.2. Figure 17 shows the results of the static power consumption evaluation. The horizontal axis indicates the number of divisions of the CLB and switch block. Whereas the maximum reduction in static power consumption is 40% when only the CLB is divided, it is possible to reduce the static power consumption by up to 60% when only the switch block is divided. The static power consumption can be effectively reduced by breaking down the threshold voltage controlled transistor area into even finer divisions and by applying the methodology to the switch block. Figure 18 shows the results for area overhead. The horizontal axis indicates the number of divisions of the CLB and switch block. For simplification, the position of the origin point is shifted from that shown in Fig. 17. For the FPGA tile as a whole, a 50% increase in area is incurred when the threshold voltage controlled transistor area of the CLB is broken down to the smallest possible level, or when the switch block is broken down to the smallest possible level. When both blocks are broken down to the smallest possible level, the area of the FPGA tile is doubled. Summarizing the results presented in Figs. 17 and 18, breaking down the CLB into 25 divisions and the switch block into 8 divisions reduces the static power consumption
2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0
Area overhead
Switch block
0
Logic block CLB
Fig. 18. Area overhead for FPGA tile
to less than 1/5 of the original level, while incurring an area overhead of less than 40%, as indicated by the black circle in the illustration. If an area increase of 50% is allowed, then breaking down the switch block into 32 divisions, as indicated by the white circle in the illustration, leads to a reduction in static power consumption to 1/10 or less. V. Conclusion Flex Power FPGA, which is capable of flexibly controlling operating speed and power consumption through threshold voltage control, is investigated with respect to the granularity of the FPGA circuit block on which threshold voltage control is applied. It is found that the application of threshold voltage control by applying well bias voltage to the bulk MOS transistors produces a trade-off relationship between the area overhead and the reduction in static power consumption. The static power consumption could be reduced effectively by dividing the areas for threshold voltage control along the critical path of the circuit. The static power consumption and area overhead of the CLB, switch block and FPGA tile are evaluated, and it is found to be possible to reduce the static
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power consumption of the CLB by 90% by breaking down into the area into 84 divisions, although this is achieved at the expense of an area overhead of 80%. It is also shown to be possible to reduce the static power consumption of the switch block to the level of a single tri-state buffer by splitting the block into 96 divisions, but with a 2.5-fold increase in area. In an evaluation of the FPGA tile incorporating both CLB and switch block, dividing the CLB into 25 divisions and the switch block into 8 divisions is found to realize a reduction in static power consumption to 1/5 of the original level with an area overhead of 40% or less. If an area increase of 50% are allowed, the switch block can be broken down into 32 divisions, providing a reduction in static power consumption to 1/10 or less. A prototype chip is currently being designed using these results as a reference. Although bulk MOS transistors are employed in the present evaluation, XMOS has advantages over bulk MOS transistors in terms of threshold voltage controllability and exclusive occupation of area. Future evaluations are planned for Flex Power FPGAs based on the XMOS architecture.
[15] H. Koike, T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki and E. Suzuki, “Xmos 1.0 : A physics-based spice model for the 4-terminal double-gate mosfet,” in IEEE 2004 SNW, pp.69–70, 2004. [16] H. Koike and T. Sekigawa, “Xdxmos : A novel technique for the doublegate mosfets logic circuits - to achieve high drive current and small input capacitance together,” in CICC, 2005. [17] SmartSpice User’s Manual, SILVACO International, 2002. [18] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “New paradigm of predictive mosfet and interconnect modeling for early circuit design,” in CICC, pp.201–204, 2000. [19] T. Kawanami, M. Hioki, T. Tsutsumi, T. Nakagawa,T. Sekigawa and H. Koike, “Area overhead estimation for vth control in flex power fpga,” in IEICE Technical Report, pp.61–66, May 2004. [20] V. Betz J. Rose and A. Marquardt, “Architecture and CAD for DeepSubmicron FPGAs,” Kluwer Academic Publishers, 1999.
Acknowledgement This research is partly supported by CREST, JST. References [1] S. Borkar, “Low power design challenges for the decade,” in ASP-DAC, pp.293–296, 2001. [2] F. Li, Y. Lin, L. He and J. Cong, “Low-power FPGA using predefined dual-Vdd/dual-Vt fabrics,” in ISFPGA, pp.42-50, 2004. [3] A. Rahman and V. Polavarapuv, “Evaluation of low-leakage design techniquesfor field programmable gate arrays,” in ISFPGA, pp.23-30, 2004. [4] A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and T. Tuan, “Reducing leakage energy in FPGAs using region-constrained placement,” in ISFPGA, pp.51-58, 2004. [5] J. H. Anderson and F. N. Najim, “Low-power programmable routing circuitry for FPGAs,” in ICCAD, pp.602-609, 2004. [6] Y. Lin, F. Li and L. He, “Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction,” in ASP-DAC, pp.645-650, 2005. [7] C. Q. Tran, H. Kawaguchi and T. Sakurai, “95% leakage-reduced FPGA using zigzag power-gating dual-Vth/Vdd and macro-Vdd-hopping,” in A-SSCC, pp.149-152, 2005. [8] T. Tuan, S. Kao, A. Rahman, S. Das and S. Trimberger, “A 90nm lowpower FPGA for battery-powered applications,” in ISFPGA, pp.3-11, 2006. [9] T.Kawanami, M.Hioki, H.Nagase, T.Tsutsumi, T.Nakagawa, T.Sekigawa and H.Koike, “Preliminary performance analysis of flex power fpga, a power reconfigurable device with fine granularity,” in ISFPGA, page 257, 2004. [10] T.Kawanami, M.Hioki, H.Nagase, T.Tsutsumi, T.Nakagawa, T.Sekigawa and H.Koike, “Preliminary evaluation of flex power fpga: A power reconfigurable architecture with fine granularity,” IEICE Trans. Information and Systems, E87-D(8):2004–2010, August 2004. [11] M.Hioki, T.Kawanami, T.Tsutsumi, T.Nakagawa, T.Sekigawa and H.Koike, “Can a cool chip be hot? yes, flex power fpga can,” in COOL Chips VII, pp.49–57, 2004. [12] T. Kuroda, T. Fujita, S. Mita, T. Nagamatu and T. Sakurai, “A 0.9v 150mhz 10mw 4mm 2-d discrete cosine transform core processor with variable-threshold-voltage scheme,” in ISSCC Dig. of Tech. Papers, pp.166–167, 1996. [13] T. Sekigawa and Y. Hayashi, “Caluculated threshold-voltage characteristics of and xmos transistor having an additional bottom gate,” Solid State Electron, 27(8/9):827–828, 1984. [14] T. Nakagawa, T. Sekigawa, T. Tsutsumi, E. Suzuki and H. Koike, “Primary consideration on compact modeling of dg mosfets with fourterminal operation mode,” in WCM, pp.330–333, 2003.
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Institute of Advanced Industrial Science and Technology (AIST) Email:{m.hioki, t-kawanami, nakagawa.tadashi, t-sekigawa, h.koike}@aist.go.jp † Department of Computer Science, School of Science and Technology, Meiji University Email:[email protected]
Abstract— The Flex Power FPGA can flexibly control speed and power in a trade-off relationship by a flexible assignment of proper threshold voltage generated from body-bias units to transistors. This paper evaluates static power consumption and an area-overhead by the body-bias units on various threshold voltage control granularity in the Flex Power FPGA. There is also a trade-off relationship between the static power consmption and the area-overhead for granular control of the threshold voltages. Both a grain size and its style of division have a strong influence on the trade-off. Own evaluation results show that static power reduces less than 1/5 of original level, while increase an area overhead of less than 40%. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained.
I. Introduction Field Programmable Gate Array (FPGA) is a hardware technology that provides flexible functionality through software. However, due to the wider flexibility produced by this device, the FPGA incurs significant circuit redundancy, resulting in larger circuit area, lower operating speeds and larger power consumption compared with the ASICs. Power consumption of current CMOS integrated circuits increases dramatically due to increase in static power, primarily related to sub-threshold leakage current and gate leakage current. Especially, as the sub-threshold leakage current increases with the technology scaling, the proportion of static power in the total power consumption of CMOS integrated circuits has increased rapidly year after year [1]. For FPGAs in particular, which contain large proportion of unused transistors that doesn’t compose logic elements, the increase in static power is even more serious. Several recent studies have examined reduction of the static power in FPGAs. The static power is reduced by using the pre-defined (fixed) high-threshold voltage transistors in several circuits such as configuration SRAMs where highspeed operation is not required [2], [3]. Since the circuit utilization rate is typically low in FPGAs, significant static power reduction is expected by isolating the unused circuit blocks from the power supply, i.e. power gating method [4], [5], [6], [7], [8]. Static power reduction by these methods is, however, rather limited, since used logic blocks, which are source of unnecessarily large static power, are left unchanged.
0-7803-9729-0/06/$20.00 2006 IEEE
High threshold voltage: Low threshold Drain current (log scale) voltage: Small leakage Ion current, but Large On Small On current, but current. Large leakage Ioff (Powercurrent as well. Oriented) (SpeedThreshold voltage Vth Oriented)
Voff
Von
Gate voltage
Voltage swing Fig. 1. Comparison of Id-Vg characteristics of MOS transistors with different threshold voltages
Flex Power FPGA has been proposed as an FPGA with the electrical adjustment method of threshold voltage by appling the bias voltage to the body of transistor to control the subthreshold leakage current [9]. Raising the threshold voltage of the transistor results in exponential reduction in the subthreshold leakage current at the expense of transistor operating speed in a trade-off relationship. It is expected that configuring the trade-off between speed and power in the circuit blocks makes it possible to control the static power flexibly, resulting in further reduction in power consumption. Many design issues should be discussed for the optimal Flex Power FPGA, such as: • The implementation of threshold voltage control (body bias, double-gate transistor...). • The granularity of the circuit for which independent threshold voltage control is applied. • Selection of the threshold voltage values. • The number of threshold voltage control steps. • The power-mapping algorithm. This paper reports the investigation and evaluation of the second item, granularity of the circuit within which identical threshold voltage is assinged. II. Flex Power FPGA Figure 1 shows the Id-Vg characteristics for MOS transistors with various threshold voltages. An on-state current of a
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FPT 2006
Routing channel
Circuit configuration register
Logic block
Power configuration register
Power configuration registers are added.
Control line to well
Threshold voltage control circuit
Power configuration register Control line to second gate
(a)
Threshold voltage control circuit
(b)
Fig. 4. Threshold voltage control configuration in (a)Bulk MOS transistor and (b)XMOS transistor Power configuration register
Power configuration register
Power configuration register
Power configuration register
Margin between transistor area and well
Fig. 2.
Margin between wells
Flex Power FPGA
Low Vt
Flex Power FPGA
Well bias voltage selector switch
Power configuration register
Fig. 5. Area overhead based on electrical threshold voltage control
High Vt
Critical path
Fig. 3. Assignments of low and high threshold voltage values in the Flex Power FPGA
transistor is increased by reducing its threshold voltage so that the transistor operates at high speed, but its static power consumption increases. Conversely, static power consumption can be reduced by increasing threshold voltage, but this causes the operating speed to drop. Flex Power FPGA has a threshold voltage adjustment function for each configuration circuit in order to flexibly adjust this trade-off relationship. As shown in Fig. 2, in addition to the configuration register for circuit configuration found in conventional FPGAs, the Flex Power FPGA has power configuration registers that records the threshold voltage setting information. This allows Flex Power FPGA to reconfigure the circuit itself, as well as the power consumption and operating speed. Flex Power FPGA assigns low- and high-threshold voltage to transistors through threshold voltage configuration circuits by setting appropriate values to the power configuration registers based on the analysis of the circuit (Fig. 3). A lowthreshold voltage is assigned to transistors on critical paths, which determine the operating speed of the circuit. Using a low threshold value increases the drive capability and operating speed of the transistor, thereby reducing critical path delay and improving the operating frequency. A high threshold value is set for transistors on paths except critical paths. the transistors
don’t have a influence on the operating frequency of the chip though operating speed of the transistors becomes slow. On the other hand, assignment of high threshold value for the transistors decreases subthreshold leakage current of the transistors because of the trade-off relatinship as shown in Fig. 1. Since such paths except critical paths comprise nearly 90% of the total signal paths, this makes it possible to reduce unnecessary static power consumption without reducing the operating speed. An evaluation tool called Flex Power VPR was developed [10]. The effectiveness of Flex Power FPGA in reducing static power consumption and controlling the operating speed were reported previously [9], [10], [11].
LUT
IBUF IMUX LBUF
DFF OMUX
BLE BLE BLE BLE CMUX
CLB Fig. 6.
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CLB: CMUX: CBUF: IBUF: IMUX: LBUF: BLE: LUT: DFF: OMUX:
Configurable logic block Multiplexer for CLB input Tri-state buffer for CLB output Buffer for CLB input Multiplexer for BLE input Local routing buffer Basic logic element Lookup table D flip flop Multiplexer for BLE output
CBUF The schematic of configurable logic block
III. Trade-off in threshold voltage control granularity
IV. Evaluation on the threshold voltage Control Granularity As indicated in Section 3, there is a trade-off in threshold voltage control granularity between the area overhead and the static power consumption, and appropriate selections must be made. The static power consumption and area overhead in various threshold voltage control granularity are therefore evaluated based on specific settings in CLB of Flex Power FPGA. The procedure for evaluation is as follows. 1) Several division patterns for threshold voltage controlled transistor area are considered. 2) A representative critical path is set. 3) Static power consumption and area overhead are evaluated. Specific division patterns for the threshold voltage controlled transistor area in a CLB are set according to the policies described in Section 4. In the present evaluation, six division
Inner area of CLB
Input area
CLB CMUX
IBUF
Output area CBUF
LBUF
IMUX
LUT
A threshold voltage can be controlled electrically in two way; by applying bias voltage to the wells of the conventional bulk MOS transistors (Fig. 4(a)) [12], and through the use of a double-gate MOS transistor which originates XMOS (Fig. 4(b)). The XMOS has been proposed by one of the present authors in 1980, and has received much worldwide attention as a next-generation semiconductor device [13], [14], [15]. Flex Power FPGA is one of the candidates of the application for the XMOS transistor [16]. In this paper, to demonstrate effectiveness of granular control for the threshold voltages, the way of applying bias voltage to the wells of bulk MOS transistors is employed, which can be achieved with current technology. When the threshold voltage is adjusted electrically by applying well bias voltage, transistors to which the same bodybias is applied are arranged on a single well to separate ohter transistors. Therefore, the threshold voltage control granularity determines its area overhead. The area overhead occurs primarily as a result of the following factors: • Margin between a transistor area and an well • Margin between wells • Switches to select well bias voltage • Power configuration registers As shown in Fig. 5, with coarse control granularity, the area overhead stays small because many circuits can be arranged in a single well. However, it possibly happens that the threshold voltage is reduced even in the circuit resources which don’t need high-speed operation, and static power reduction is not satisfactory. Conversely, the threshold voltage can be adjusted independently for the various circuit resources with fine control granularity, achieving thorough reduction of the static power. However, the fine control granularity requires the separation of circuits with many wells, and a lot of selector switches and power configuration registers. These factors increase the area overhead.
Policy 3: Separately controlled
Policy 2: Separately controlled
OMUX DFF
BLE
Fig. 7.
Fig. 8. CLB
Policy 1: Collectively controlled
Policies for division of controlled transistor area
No control
1 division
5 divisions
25 divisions
30 divisions
84 divisions
Division patterns for threshold voltage controlled transistor areas in
patterns of the CLB for threshold voltage controlled transistor area are examined, as shown in Fig. 8. Areas in which the threshold voltage is controlled simultaneously are outlined. In the block marked "No control", no threshold voltage control is carried out. In the block showing one division, the threshold voltage is controlled for the entire CLB as a whole. In the block showing five divisions, the BLE inside the CLB and the IMUX, LBUF and CBUF connected to BLE are split off as one area, and the elements on the input side are treated as one area. In the block showing 25 divisions, the five divisions are broken down further, where the CMUX and IBUF on the input side and output side are divided into smaller areas. In the block showing 30 divisions, the divisions are even smaller than those of the 25-division block, with the CMUX and IBUF on the input side divided further into smaller areas. Finally, in the block showing 84 divisions, all of the elements configuring the CLB are divided into individual areas.
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Sqrt(xy)
y
Power config. memory Config. memory CBUF LBUF DFF OMUX LUT IMUX IBUF CMUX
1.2 x
1 Static power
Sqrt(xy) Area defined by VPR area model Additional area by the margins among diffusions and wells (a) Area increase by well separation
(b) Layout estimated to square of the same area as (a)
0.8 0.6 0.4 0.2
Fig. 9.
Extended area model
0 No 1 5 25 30 84 control division divisions divisions divisions divisions
A. Configurable Logic Block Figure 10 shows the results of the static power consumption evaluation. Without threshold voltage control, as in the blocks
Fig. 10.
Area overhead
A critical path considered to be representative is then set to pass through this CLB. We assume that the critical path passes through CMUX, IBUF, IMUX, LUT, OMUX and CBUF in order as indicated by the solid-line arrow in Fig. 8. It is thought that a very simple, straightforward assumption such as this would be adequate for the present evaluation because the preliminary evaluations have shown that the critical path comprises only a portion of all of the signal paths. Based on the above, the static power consumption is evaluated by combining the critical path and the division patterns for the threshold voltage controlled transistor areas. Threshold voltage control steps are two, low threshold value and a high threshold value. Well bias voltages Vbias nmos = 0V, −VDD and Vbias pmos = +VDD , +2VDD are applied to the wells for nmos and pmos, respetively to set the low- and high- threshold voltages. In Fig. 8, the low threshold voltage is assigned to circuits with areas through which the critical path passes, and these are indicated by a solid outline. The high threshold voltage is assigned to circuits areas through which the critical path does’t pass, and these are indicated by dotted outlines. A simulation of the static power consumption for various circuit components, such as CMUX, IBUF, etc, with two levels of threshold voltage is conducted using the SPICE [17] with a BPTM 70 nm transistor model [18] (UC Berkeley). The results of the SPICE simulation are used to evaluate the static power consumption of the CLB. To evaluate the area for the division patterns of the various threshold voltage controlled transistor areas, the extended area model reported in [19] is used (Fig. 9). This is generally performed as follows. The extended area model is a simple model in which the VPR area model [20] has been extended by adding margins between the wells and transistors, which are necessary in order to implement threshold voltage control by applying a well bias voltage. The margins between the wells themselves are also included. A square approximation is then applied to the area calculated by the conventional VPR area model to determine the length of one side. The increases resulting from the addition of well margins are then added and the result is squared to determine the area in which the well margins are included.
2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0
Static power reduction for CLB
Well bias voltage selector switch Power config. Memory Amount of increase in well Config. Memory Logic
No 1 5 25 30 84 control division divisions divisions divisions divisions
Fig. 11. Area overhead for CLB
labeled "No control", a low threshold value is assigned to all of the transistors. In the one-division block, the threshold voltage of all transistors in the CLB is collectively controlled. Static power consumption is very much the same as that with no control because a low threshold voltage is assigned to all of the transistors in the CLB. However, when the FPGA as a whole is considered, the static power consumption of CLBs that are not used or are not within a critical path can be reduced. In comparison with the no-control block, the power consumption in the five-division block has been reduced by more than 60%. Treating each BLE inside the CLB and the elements connected to the BLE, that is IMUX, LBUF and CBUF, as an area for threshold voltage control is expected effective. The input and output buffer sections are further subdivided, as in the 25-division and 30-division blocks, the power consumption can be reduced by 80% from that with no control. If the threshold voltage controlled transistor areas are broken down even further, as in the 84-division block, into the minimum circuit units configuring the FPGA, the static power consumption can be reduced by more than 90%, but the area overhead will be extremely large, as discussed below. Figure 11 shows the results of area overhead evaluation. The area is expressed as the minimum number of transistors, and is standardized against the result for no control. As is indicated by the one-division block, when threshold control is
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FPGA Routing channel
Detailed circuit of routing switch
Switch block I/O pad
Power config. Memory Config. Memory Switch
1.2 1 Static power
Logic block
0.8 0.6 0.4 0.2
Fig. 12.
The schematic of switch block
0 No control 1 division
Fig. 14.
No control
1 division
96 divisions
Static power reduction for switch block
3
8 divisions
Area overhead
2.5
32 divisions
32 divisions
8 divisions
96 divisions
B. Switch Block The policies discussed in Section 4 for splitting the threshold voltage controlled transistor areas can also be applied to the FPGA switch blocks. In this section, the area and static power consumption of the switch blocks are evaluated for the five types of area divisions indicated in Fig. 13. In the switch blocks as shown in Fig. 12, the wires are connected by means of groups of switches in each of 12 tri-state buffers serve as routing switches, and signals propagate bidirectionally to any of wires. The switch blocks are composed of 8 switch groups, and there are a total of 96 tri-state buffers. In Fig.13, "No control" indicates that no threshold voltage control is applied, "1 division" indicates that threshold voltage control is carried out for all of the tri-state buffers in the switch block as a whole, "8 divisions" indicates threshold voltage control for each of the 8 switch groups, "32 divisions" indicates that threshold voltage control is carried out for three tri-state buffers with the common input wire as a group, and "96 divisions" indicates that the threshold voltage is controlled individually for the 96 tri-state buffers in the switch block. A simple critical path, just as in the CLB evaluation, is assumed as indicated by the solid arrow in Fig. 13.
1.5 1 0.5
Fig. 13. Division patterns for threshold voltage controlled transistor areas in switch blocks
implemented for the entire CLB as a whole, the area overhead is only 10%. As the threshold voltage controlled transistor areas are further broken down into 5, 25, and 30 divisions, the overhead increases to 20%, 35%, and 45%, respectively, and finally exceeds 80% when broken down to the smallest subdivision level of 84 divisions.
2
Well bias voltage selector switch Power config. Memory Amount of increase in well Config. Memory Switch
0 No control 1 division 8 divisions
32 divisions
96 divisions
Fig. 15. Area overhead for switch block
Figure 14 shows the results of the static power consumption evaluation. In the one-division block, no reduction is seen in static power consumption, similar to the case for CLB. However, this becomes important when evaluating the static power consumption in unused switch blocks and in used switch blocks outside of the critical path. If a switch block is divided into 8 segments, the static power consumption of the switch block can be reduced to 1/8 of the original level. This is because the threshold voltage of the 7 switch groups outside of the critical path can be set higher. Further subdividing into 32 divisions makes it possible to assign a high threshold value to the tri-state buffers (more efficiently than with 8 divisions), and the static power consumption can be reduced to 1/32. Breaking the switch block down even further into 96 divisions makes it possible to reduce the static power consumption to a level equivalent to that for a single tri-state buffer, but caution is required because this causes a dramatic increase in the area overhead. Figure 15 shows the results of the area overhead evaluation. The area increase in one division to no control is only 10%. Increasing the number of divisions to 8 and then to 32 increases the area overhead by 40% and 70%, respectively. With 96 divisions, where each tri-state buffer is controlled individually, the area is 2.5 times larger than when no threshold voltage control is applied.
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CLB
Critical path
1.2
0.8 0.6 0.4
Static power
1
0.2 No control 1 division 8 divisions 32 divisions Switch 96 divisions block
84
l ro nt co o n N io vis di s n 1 io vis s di on 5 si vi di s 25 on si vi di s 30 on si vi di
Finest granularity
Fig. 17. Fig. 16.
Logic block CLB
Static power reduction for FPGA tile
The schematic of FPGA tile and critical path
C. FPGA Tile
Finest granularity
s on si vi di s 84 on si vi di s 30 on si vi di 25 ns io vis di 5 n io vis di l ro nt co 1
o
96 divisions 32 divisions 8 divisions 1 division Switch No control block
N
The evaluation results for CLBs and switch blocks described in Sections 5.1 and 5.2 are used to evaluate the area overhead and static power consumption of the FPGA tile. Figure 16 shows the FPGA tile and the assumed critical path. The FPGA tile combines one CLB and one switch block considered in Sections 5.1 and 5.2. It is assumed that one critical path passes through a single tri-state buffer in the switch block and then passes through a CMUX, IBUF, IMUX, LUT, OMUX and OBUF in the CLB before exiting to external routing. This is a combination of the critical paths assumed in the CLB and switch block described in Sections 5.1 and 5.2. Figure 17 shows the results of the static power consumption evaluation. The horizontal axis indicates the number of divisions of the CLB and switch block. Whereas the maximum reduction in static power consumption is 40% when only the CLB is divided, it is possible to reduce the static power consumption by up to 60% when only the switch block is divided. The static power consumption can be effectively reduced by breaking down the threshold voltage controlled transistor area into even finer divisions and by applying the methodology to the switch block. Figure 18 shows the results for area overhead. The horizontal axis indicates the number of divisions of the CLB and switch block. For simplification, the position of the origin point is shifted from that shown in Fig. 17. For the FPGA tile as a whole, a 50% increase in area is incurred when the threshold voltage controlled transistor area of the CLB is broken down to the smallest possible level, or when the switch block is broken down to the smallest possible level. When both blocks are broken down to the smallest possible level, the area of the FPGA tile is doubled. Summarizing the results presented in Figs. 17 and 18, breaking down the CLB into 25 divisions and the switch block into 8 divisions reduces the static power consumption
2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0
Area overhead
Switch block
0
Logic block CLB
Fig. 18. Area overhead for FPGA tile
to less than 1/5 of the original level, while incurring an area overhead of less than 40%, as indicated by the black circle in the illustration. If an area increase of 50% is allowed, then breaking down the switch block into 32 divisions, as indicated by the white circle in the illustration, leads to a reduction in static power consumption to 1/10 or less. V. Conclusion Flex Power FPGA, which is capable of flexibly controlling operating speed and power consumption through threshold voltage control, is investigated with respect to the granularity of the FPGA circuit block on which threshold voltage control is applied. It is found that the application of threshold voltage control by applying well bias voltage to the bulk MOS transistors produces a trade-off relationship between the area overhead and the reduction in static power consumption. The static power consumption could be reduced effectively by dividing the areas for threshold voltage control along the critical path of the circuit. The static power consumption and area overhead of the CLB, switch block and FPGA tile are evaluated, and it is found to be possible to reduce the static
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power consumption of the CLB by 90% by breaking down into the area into 84 divisions, although this is achieved at the expense of an area overhead of 80%. It is also shown to be possible to reduce the static power consumption of the switch block to the level of a single tri-state buffer by splitting the block into 96 divisions, but with a 2.5-fold increase in area. In an evaluation of the FPGA tile incorporating both CLB and switch block, dividing the CLB into 25 divisions and the switch block into 8 divisions is found to realize a reduction in static power consumption to 1/5 of the original level with an area overhead of 40% or less. If an area increase of 50% are allowed, the switch block can be broken down into 32 divisions, providing a reduction in static power consumption to 1/10 or less. A prototype chip is currently being designed using these results as a reference. Although bulk MOS transistors are employed in the present evaluation, XMOS has advantages over bulk MOS transistors in terms of threshold voltage controllability and exclusive occupation of area. Future evaluations are planned for Flex Power FPGAs based on the XMOS architecture.
[15] H. Koike, T. Nakagawa, T. Sekigawa, T. Tsutsumi, M. Hioki and E. Suzuki, “Xmos 1.0 : A physics-based spice model for the 4-terminal double-gate mosfet,” in IEEE 2004 SNW, pp.69–70, 2004. [16] H. Koike and T. Sekigawa, “Xdxmos : A novel technique for the doublegate mosfets logic circuits - to achieve high drive current and small input capacitance together,” in CICC, 2005. [17] SmartSpice User’s Manual, SILVACO International, 2002. [18] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “New paradigm of predictive mosfet and interconnect modeling for early circuit design,” in CICC, pp.201–204, 2000. [19] T. Kawanami, M. Hioki, T. Tsutsumi, T. Nakagawa,T. Sekigawa and H. Koike, “Area overhead estimation for vth control in flex power fpga,” in IEICE Technical Report, pp.61–66, May 2004. [20] V. Betz J. Rose and A. Marquardt, “Architecture and CAD for DeepSubmicron FPGAs,” Kluwer Academic Publishers, 1999.
Acknowledgement This research is partly supported by CREST, JST. References [1] S. Borkar, “Low power design challenges for the decade,” in ASP-DAC, pp.293–296, 2001. [2] F. Li, Y. Lin, L. He and J. Cong, “Low-power FPGA using predefined dual-Vdd/dual-Vt fabrics,” in ISFPGA, pp.42-50, 2004. [3] A. Rahman and V. Polavarapuv, “Evaluation of low-leakage design techniquesfor field programmable gate arrays,” in ISFPGA, pp.23-30, 2004. [4] A. Gayasen, Y. Tsai, N. Vijaykrishnan, M. Kandemir, M. J. Irwin and T. Tuan, “Reducing leakage energy in FPGAs using region-constrained placement,” in ISFPGA, pp.51-58, 2004. [5] J. H. Anderson and F. N. Najim, “Low-power programmable routing circuitry for FPGAs,” in ICCAD, pp.602-609, 2004. [6] Y. Lin, F. Li and L. He, “Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction,” in ASP-DAC, pp.645-650, 2005. [7] C. Q. Tran, H. Kawaguchi and T. Sakurai, “95% leakage-reduced FPGA using zigzag power-gating dual-Vth/Vdd and macro-Vdd-hopping,” in A-SSCC, pp.149-152, 2005. [8] T. Tuan, S. Kao, A. Rahman, S. Das and S. Trimberger, “A 90nm lowpower FPGA for battery-powered applications,” in ISFPGA, pp.3-11, 2006. [9] T.Kawanami, M.Hioki, H.Nagase, T.Tsutsumi, T.Nakagawa, T.Sekigawa and H.Koike, “Preliminary performance analysis of flex power fpga, a power reconfigurable device with fine granularity,” in ISFPGA, page 257, 2004. [10] T.Kawanami, M.Hioki, H.Nagase, T.Tsutsumi, T.Nakagawa, T.Sekigawa and H.Koike, “Preliminary evaluation of flex power fpga: A power reconfigurable architecture with fine granularity,” IEICE Trans. Information and Systems, E87-D(8):2004–2010, August 2004. [11] M.Hioki, T.Kawanami, T.Tsutsumi, T.Nakagawa, T.Sekigawa and H.Koike, “Can a cool chip be hot? yes, flex power fpga can,” in COOL Chips VII, pp.49–57, 2004. [12] T. Kuroda, T. Fujita, S. Mita, T. Nagamatu and T. Sakurai, “A 0.9v 150mhz 10mw 4mm 2-d discrete cosine transform core processor with variable-threshold-voltage scheme,” in ISSCC Dig. of Tech. Papers, pp.166–167, 1996. [13] T. Sekigawa and Y. Hayashi, “Caluculated threshold-voltage characteristics of and xmos transistor having an additional bottom gate,” Solid State Electron, 27(8/9):827–828, 1984. [14] T. Nakagawa, T. Sekigawa, T. Tsutsumi, E. Suzuki and H. Koike, “Primary consideration on compact modeling of dg mosfets with fourterminal operation mode,” in WCM, pp.330–333, 2003.
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