Experiences Teaching Physical Synthesis of FPGAs and ASICs
Don Bouldin and Pradeep Chimakurthy Electrical & Computer Engineering University of Tennessee Knoxville, TN 37996-2100
[email protected] Abstract Interconnect delays dominate gate delays in integrated circuits fabricated using 180-nm feature sizes or below. Hence, no longer can designers separate the logic synthesis function from physical placement and routing but instead must perform physical synthesis to achieve timing closure with a minimum of design cycle iterations. Experiences teaching students to design competitive FPGAs and ASICs using physical synthesis are described in this paper.
In this paper we describe the use of EDA tools for both FPGAs and ASICs to expose students to physical synthesis.
1. Introduction Project-oriented courses at the University of Tennessee have been taught for over two decades to afford students the opportunity to design state-of-the-art FPGAs and ASICs. Until this past year, these courses have informed students that synthesis and placement could be performed as separate steps in the development cycle. However, statistical wireload models traditionally used to estimate interconnect delays during synthesis are no longer sufficiently accurate. As illustrated in Figure 1, the progression to smaller feature sizes in the fabrication process has led to the situation in which interconnect delays now dominate gate delays. Integrated circuits fabricated using a feature size of 1-micron had gate delays which contributed 70% to the clock cycle while interconnect delays comprised only 30%. This situation has now reversed at 180-nm with gate delays consuming only 15% while interconnect delays contribute a total of 85% [1]. Physical synthesis has been developed during the past few years by multiple electronic design automation (EDA) vendors to integrate the logic synthesis and placement steps to achieve a better estimation of the interconnect delays. By combining these two operations, the interconnect estimation is performed after placement and has been shown to have values closer to the final routing values since the placement of the cells is known and the appropriate drive strength can be selected. Thus timing sign-off can be achieved using fewer iterations of the design cycle [2].
Fig. 1. Delays for Integrated Circuits [1]
2. Physical Synthesis of FPGAs For FPGA synthesis, the market leader for the past several years has been Synplicity’s synplify_pro which performs logic synthesis only. The company has now introduced (www.synplicity.com) synplify_premiere which performs physical synthesis. Internally, the EDA tool employs a graph-based representation of the pre-existing and pre-placed logic components as well as the interconnect wires and switches. This resource graph uses metrics for delay and availability of resources to achieve timing improvements 20% better than those obtained by using separate logic synthesis and placement. The task of providing synplify_premiere to students was very straightforward since the EDA tool is packaged with the necessary models to target a variety of FPGA devices. Furthermore, the tutorials provided by Synplicity were of immediate use since they were tailored to the same level as the students in the course.
3. Physical Synthesis of ASICs For ASIC synthesis, the market leader for the past several years has been Synopsys’s DesignCompiler which performs logic synthesis only [4]. The company (www.synopsys.com) has now introduced psyn which performs physical synthesis. The task of providing psyn and other associated EDA tools for a complete ASIC flow from RTL to GDS, however, is really quite complex. This situation is hampered by the fact that Synopsys generally cannot provide a complete package with the target libraries already installed. Instead, the user must obtain these libraries from another source and then integrate them. In our case, we obtained the IBM7RF standard-cell library files developed by Artisan from the MOSIS secure website (www.mosis.org) after signing multiple non-disclosure agreements. We then had to follow instructions provided by Synopsys to merge the library information into the toolset. Fortunately, the Synopsys University Program coordinator was able to obtain permission for us to access the Galaxy Reference Flow (GRF) which provided us with example scripts on how to setup and run each tool in the ASIC flow. Although this set of examples can no longer be provided to others because of changes in business units within Synopsys, efforts are being made to provide another reference flow to the university community. The steps involved in the physical synthesis of ASICs are: logic synthesis, (2) floorplanning (as shown in Fig. 2), (3) physical synthesis, (4) clock tree synthesis (as shown in Fig. 3) and final routing.
Fig. 3. Clock Tree Synthesis.
4. Student Experiences For FPGAs and for ASICs, physical synthesis tutorials [3] were provided to the students. However, this was done only after the students had first experienced the traditional separate steps of logic synthesis followed by physical placement and routing in their introductory courses on small designs of a few thousand gates with a few hundred components and nets. Physical synthesis was used in the advanced courses for large designs exceeding 100K gates comprised of thousands of components and nets. This twostep approach allowed the students to grasp fully the traditional procedure and then to appreciate the value of physical synthesis on the larger designs. We plan to continue using this two-step approach to enhance the learning experiences of students while preparing them to produce state-of-the-art solutions.
5. References [1] S. Hojat and P. Villarrubia, “An integrated placement and synthesis approach for timing closure for the PowerPC microprocessor”, Proceedings of the 1997 International Conference on Computer Design, p. 206. [2] K. Keutzer, R Newton and N. Shenoy, “The future of logic synthesis and physical design in deep-submicron process geometries”, Proceedings of the 1997 International Symposium on Physical Design, pp. 218-224.
Fig. 2. ASIC Floorplan.
[3[ D. Bouldin, “Microelectronic System Courses at the University of Tennessee,” Online: http://vlsi1.engr.utk.edu/ece/bouldin_courses/