Experimental and numerical analysis of BGA lead-free solder joint ...
Microelectronics Reliability 49 (2009) 79–85
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact Fang Liu a,*, Guang Meng a, Mei Zhao a, Jun feng Zhao b a b
State Key Laboratory of Mechanical System and Vibration, Shanghai Jiao Tong University, 800 Dongchuan Road, Shanghai 200240, PR China Intel Technology Development Shanghai Ltd., 999 Yinglun Road, Shanghai 200131, PR China
a r t i c l e
i n f o
Article history: Received 20 June 2007 Received in revised form 21 August 2008 Available online 12 December 2008
a b s t r a c t Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability. Crown Copyright Ó 2008 Published by Elsevier Ltd. All rights reserved.
1. Introduction With the popularity of portable telecommunication devices such as mobile phones and PDAs, reliability of handheld electronic products has become a major concern recently. These handheld electronic products are more prone to being accidentally dropped during their useful service life, and drop impact can cause not only housing crack, but also package to board interconnect failures. In the past several years, a lot of drop tests have been conducted for board-level [1–6] and product level drop tests [7,8]. On one hand, board-level tests simplify real drop impact conditions, on the other hand, they are more controllable than product level tests, and are more convenient to characterize the solder joint performance. So a JEDEC working group developed a standard board-level drop test for handheld electronic products in 2003. However, comparing with actual drop test, which is expensive, time-consuming, and requires much more manpower in measurement and failure analysis, finite element (FE) modeling is proven to be a very efficient tool and has been applied widely for the modeling * Corresponding author. Tel.: +86 21 34206664x319; fax: +86 21 34206006. E-mail address: [email protected] (F. Liu).
and simulation for board-level drop tests in order to reveal the structural responses and failure mechanisms of the board-level PCBA subjected to drop impact [9,10]. In recent years, numerous studies have been devoted to the understanding of structural responses and failure mechanisms of board-level test vehicle subjected to drop impact, but currently there is less comprehensive work on dynamic responses of PCBA by both drop experiment and drop simulations [11]. Generally, drop tests were conducted to investigate the effects of different factors on solder joint reliability, such as package types, pad structures, solder bumps, solder compositions [2,12,13]. For board-level drop simulation, Luan and his co-authors developed a novel inputG method to simplify drop simulation [14]. So FEM has been used widely for the simulation of electronic packaging problems. However, most papers [15–18] focused on how to choose a good simulation methodology and discussing the affecting factors of simulation results, such as mesh density, element types and material models. In fact, if drop tests were combined with drop simulation, more excellent results would be obtained. As we all know, the dynamic strains and stresses of solder joints directly affect the solder joint reliability during drop impact, but there is no suitable sensor to measure them directly. Alternatively, the dynamic re-
0026-2714/$ - see front matter Crown Copyright Ó 2008 Published by Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.10.014
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F. Liu et al. / Microelectronics Reliability 49 (2009) 79–85
sponses of printed circuit board (PCB) are good measurable indicators which are closely related to solder joint strains and stresses. If a FE model could be proved to be effective by test results, dynamic responses of critical solder joint would be obtained by FE simulation, which can help to reveal the mechanical behaviors or the failure mechanisms of solder joints. Thus, testing and simulating, based on drop test and FEM, will be effective to analyze dynamic responses of PCBA. This paper aims to investigate the dynamic behaviors of PCBA in the round shape under drop impact loading and study the root cause of lead-free solder joint failure. A new round test board with eight BGA packages is designed. Firstly, the round test board is dropped from a specified height (0.34 m), and subjected to a half-sine acceleration pulse (1500 Gs, 0.55 ms). At the same time, strain and acceleration histories of the test board are measured. Secondly, ABAQUS software is used to simulate dynamic responses of the test board and model strains and stresses of solder joints. Based on experiment and FE results, board-level drop impact performance of BGA lead-free solder joint for handheld electronic product is studied. Finally, dye penetration test and microscopic test are chosen to examine the failure locations and failure mechanisms of lead-free solder joints. 2. Drop test 2.1. Test vehicle BGA packages can meet with the increasing demands on miniaturization and high performance of portable electronic products. So in this study, eight BGA packages are selected for drop test. These BGA packages numbered from 1 to 8 were mounted centrosymmetrically on a round PCB (160 mm diameter, 1 mm thickness), shown in Fig. 1. The detailed design process has been demonstrated in another paper [19]. Thus, eight packages will be exposed to a uniform test condition. The diameter of solder ball is 0.35 mm and ball pitch is 0.8 mm. Via-in-pad structure is adopted. In the surface mount process, the Sn–3Ag–0.5 Cu solder paste is employed for lead-free solders.
2.2. Drop test system A drop test setup used in the drop test is similar to drop setup of JEDEC standard [20] (see Fig. 2). The PCBA is fixed on base plate (165 mm 165 mm 32 mm) of the drop test setup with eight standoffs. Between the test board and surface of the base plate, 20 mm standoff is added to allow PCB bending freely. Ideally, the standoffs should be rigid and move simultaneously with the drop table during the drop impact process. In the drop impact tests, the PCB is always positioned in horizontal direction with packages facing downwards. The drop height and impact pulse are controlled. The drop table is released and dropped freely at a certain height to hit on the strike surface, and a high G acceleration pulse is created. In the course of drop test, the dynamic responses of PCB are crucial because they reflect the mechanical behaviors of PCB, which are closely related to solder joint failure during drop impact. Test instruments, which form a drop test system, can carry out testing, and some correlative data are acquired. The block diagram for drop test system is schematically shown in Fig. 3. It can be seen from Fig. 3 that all test instruments are utilized during the drop test. Firstly, two accelerometers are used in the test to determine the acceleration responses of the round test board subjected to drop impact. One accelerometer is attached to the base plate close to one of the support locations to monitor peak acceleration (Gm) and duration (T) of the half-sine impact pulse (input acceleration applied to the PCB), the other is mounted at the center of the PCBA (non-component) to characterize the output acceleration responses of the PCBA. Two acceleration signals via charge amplifiers are sent to LMS Test Lab that records down the input and output accelerations of the PCB. Secondly, dynamic strain meter is setup to measure in-plane strains of the PCB. Two strain gauges connected to dynamic strain meter, are located on the back of the critical solder joint (non-component side of the PCB) to measure the dynamic strains induced in circumferential and radial directions of the PCB. Finally, a digital oscilloscope is adopted in order to measure dynamic voltage of dynamic resistance of daisy chain of solder joints. There are two daisy chain loops for each BGA package with outer and inner loops. The principal circuit is shown in Fig. 4. A resistor, R0, is placed in series to the outer/inner daisy chain loop of solder joints and connected to a DC power supply. The dynamic resistance of the outer/inner loop, Rx, can be given by
Rx ¼
R0 V R0 ¼ E V E=V 1
ð1Þ
where E is the voltage (5.0 V) of the DC power supply, and V is the dynamic voltage of outer/inner daisy chain loop, which changes with dynamic resistance of outer/inner loop, Rx. For convenience, V is monitored instead of resistance using a digital oscilloscope. When V approaches to E, Rx will be close to 1 (open circuit), which suggests that the critical solder joint has failed. 2.3. Repeatability of drop test
Fig. 1. Round test board.
Good repeatability of dynamic responses is very important for the life-expectancy prediction of solder joints under impact load, so a trial and error process is required to calibrate and characterize a drop tester to achieve the required impact pulse before actual drop testing can be performed. Continual eight drops are conducted to check the repeatability of testing results, and impact pulse is measured. In Fig. 5 the input acceleration pulses of eight drops display excellent repeatability. It implies that the drop test system is under good control. For instance, the round PCB mounted by eight screws is dropped from 0.34 m height (Gm = 1500 G and T = 0.55 m) in total eight times. The tolerances of acceleration peak 1500 G and pulse duration 0.55 ms are within ±6%, respectively.
F. Liu et al. / Microelectronics Reliability 49 (2009) 79–85
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Fig. 2. Typical drop test setup.
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Fig. 3. Block diagram for drop test system.
sured strain values and acceleration responses can also be used for verification of FE results. 3. Drop simulation 3.1. FE model
Fig. 4. Dynamic resistance monitoring system.
Thus, drop test can be conducted repeatedly. During drop test, some relative data can be gained, such as in-plane strains of the PCB, input/output acceleration, and cracked solder joints. The mea-
In order to understand transient dynamic responses of the round test board under high G acceleration pulse, commercial software ABAQUS is used to do drop simulation. The geometry model of the PCBA is very simple, and material parameters, boundary condition and damping ratio may be determined by some modal tests. Based on modal tests and simulation, how to establish a valid FE model have been demonstrated in the other paper [21]. Thus, it is easy to use input-G method to do FE analysis very well. Due to centrosymmetric structure of the PCBA, a FE model with one eighth of the round test board (shown in Fig. 6) is used in drop simulation
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Fig. 7. Comparison of strain (radial) curves.
Modeling vs. Experiment Modeling
Fig. 5. Acceleration pulse of eight drops.
in order to reduce computing cost. Mesh of the model is coarse and element type is C3D8R. The FE model includes 22659 elements and 31405 nodes. Input acceleration is the same as the acceleration of our drop test, and the initial velocity of simulation is
v0 ¼
pffiffiffiffiffiffiffiffi 2gh
Microstrains (µε)
Experiment
ð2Þ
where, h is drop height, g is gravity acceleration. So it is easy to perform FE analysis if algorithms and solvers are chosen properly.
Fig. 8. Comparison of strain (circumferential) curves.
3.2. Algorithms and solvers Three solvers in ABAQUS can be used in dynamics simulation. These solvers are explicit solver, modal dynamic solver and implicit solver, respectively. Which solver should be chosen? The explicit solver is conditionally stable and stability limit is closely related to the time required for a stress wave to cross the smallest element dimension [22]
Dt ¼
Lmin Cd
Time (ms)
ð3Þ
where Lmin is the smallest element dimension, and Cd is a material constant. This stability limit is automatically calculated by ABAQUS by default and therefore ABAQUS can produce very accurate results in explicit solver. Since the Lmin is generally very small (generally dominated by the solder ball mesh), the computing time is very long. The damping effects will greatly increase the computing time, so the explicit solver is not recommended to do the simulation. In modal dynamics solver, the accuracy depends on how many modes are used in superposition. Since the computing cost is low,
Fig. 6. FE model of one eighth of the round test board.
F. Liu et al. / Microelectronics Reliability 49 (2009) 79–85
we can consider tens of modes in the modeling to increase the accuracy. Nevertheless, one has to keep in mind that modal superposition is only valid when the test vehicle is linearly elastic. Test board is subjected to high G acceleration pulse (1500 G, 0.55 ms half-sine pulse). The center displacement of test board is larger than the board thickness (1 mm), thus modal dynamics solver is not recommended either. Though the implicit solver is unconditionally stable, its accuracy is dependent on the half-step residual tolerance, Rt+Dt/2, which is specified by the user. If only the Rt+Dt/2 is determined well, the accuracy of simulating results will be high. Based on computing time and geometric nonlinearity, the implicit solver in ABAQUS is chose to do drop simulation analysis.
the maximum peeling stress of lead-free solder joint is the dominant stress component, which affects the solder joint reliability during drop impact [1,4], thus the peeling stress of solder joints (S33) is employed to estimate which solder joint will be vulnerable to fail at first. The mesh of the solder joint is very coarse and theoretically the stress value is singular at the corner of solder joint/ copper pad, so the output stress is centroidal stress of the element. In the modeling, the peeling stress in the direction of drop is selected as an indicator which determines the initial crack of solder
4. Results and discussions 4.1. Dynamic responses Drop test results could be used to check the model quality and increase the confidence on the numerical results. It can be shown in Figs. 7 and 8 that the time-dependent dynamic strains in radial and circumferential directions predicted by FE simulation agree well with the measured strains at package corner, especially the circumferential strain. In Fig. 8, the dynamic strain of the PCB in circumferential direction predicted by modeling correlates very well with that measured by the drop test, and the amplitudes of the PCB strains decrease gradually with time. Furthermore, a good agreement between measured and computed acceleration profiles can be seen from Fig. 9. The output acceleration history of the PCB center by FE simulation is similar to the result of actual drop test. In one word, FE simulation results are well consistent with that measured by actual drop tests, which means that the FE model can be used to predict reliability and life of solder joints under board-level drop impact condition. Good correlation in dynamic responses of the PCBA will contribute to study solder joint reliability and impact life, and the effective model can be used to optimize design of PCBA for drop impact loading and enhance reliability of solder joints.
Fig. 10. Maximum peeling stress of the solder ball at different l.
4.2. Failure analysis Since PCB bending vibration is the major failure cause of leadfree solder joints under drop impact, and the peeling stress is induced mainly by PCB bending vibration and mechanical shock,
Modeling Vs. Experiment Modeling
Fig. 11. Maximum peeling stress of the critical solder ball.
Acceleration (G)
Experiment
Time (ms) Fig. 9. Center acceleration response of round PCBA.
83
Fig. 12. Peeling stress time-history of the critical solder ball.
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F. Liu et al. / Microelectronics Reliability 49 (2009) 79–85
Fig. 13. Center displacement of round PCBA. Fig. 14. Dye stain photo.
joints. That is to say, the bigger the peeling stress of a location is, the more vulnerable the location is. It can be seen from Fig. 10 that the maximum peeling stress of the critical functional ball is 190.92 MPa, and there is larger peeling stress at the solder joints which locate at the outermost corner of packages. These solder balls at the outermost corner are critical solder joints, and would be very vulnerable to crack. From Fig. 11, it can be estimated that the maximum peeling stress appears in the region between package and the solder joint, and it can be also inferred that the initial
crack would occur near the region. Fig. 12 depicts peeling stress time-history of the critical solder joint. Center displacement of round PCBA is given in Fig. 13. Due to drop impact, the PCBA is firstly subjected to a huge mechanical shock, and then the center displacement and the peeling stress both arrive at the maximum value immediately. After that, the PCBA is suffered from a cyclic bending vibration. From Figs. 12 and 13, it can be seen that the
Fig. 15. Optical cross section photos of failed solder joint.
F. Liu et al. / Microelectronics Reliability 49 (2009) 79–85
peeling stress and the center displacement decrease gradually with time. Since BGA packages mounted on the PCB are generally not as flexible as the board, the bending of the board and relatively higher rigidity of the BGA package exerts tensile forces on solder joints. The solder joints will endure cyclic peeling stress and compressive stress. This ultimately causes failures in solder joints. Thus, it can be concluded that the combined effect of great mechanical shock and bending vibration is the major failure cause of solder joint when PCB is subjected to drop impact. In addition, the failure location, failure interface, and failure mode are all verified by dye penetration test photo and cross section photos. The critical solder balls occur at the outermost corner, and fail along the solder and package pad interface. It can be seen from Fig. 14 that three solder balls at outermost corner have failed, and it is shown from Fig. 15 that the failure interface of critical solder ball is at IMC interface on the package side. So the location of the maximum peeling stress predicted by modeling agrees well with actual failure location observed in drop test, and it is also proven that the maximum peeling stress could be used as a failure indicator to determine the first failure location. 5. Conclusions In order to investigate the cause of lead-free solder joint failure under drop impact, the dynamic behaviors of the PCBA under board-level drop impact loading are studied and analyzed by both drop test and drop simulation in detail. The following conclusions are drawn. (1) The established FE model is enormously simple and effective, the dynamic responses, such as output acceleration, strains are well correlated between testing and simulating. This will help to establish a more accurate impact life prediction model of solder joint. (2) The peeling stress of the critical solder joint in FE simulation could be considered to be the dominant failure factor, which correlates well with the observations by experiment. When the maximum peeling stress is used as a failure indicator to determine initial failure location of solder joints, numerically predicted failure locations of the solder joints accord with those observed from drop impact tests. (3) It can be concluded that the combined effect of mechanical shock and PCB bending vibration is the root cause of solder joint failure under drop impact. Acknowledgements This work was supported by NSFC (No. 50775138) and a research collaboration project between Intel and SJTU.
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References [1] Tee TY, Luan JE, et al. Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact. In: Proceedings of 54th electronic components and technology conference, Las Vegas, NV; 2004. p. 1088–94. [2] Lai YS, Yang PF, Yeh CL. Experimental studies of board-level reliability of chipscale packages subjected to JEDEC drop test condition. Microelect Reliab 2006;46(2–4):645–50. [3] Tee TY, Hun SN, et al. Impact life prediction modeling of TFBGA packages under board level drop test. Microelect Reliab 2004;44(7):1131–42. [4] Luan JE, Tee TY, et al. Solder joint failure modes, mechanisms and life prediction models of IC packages under board level drop impact. In: Proceedings of sixth international conference on electronic packaging technology; 2005. [5] Varghese J, Dasgupta A. Test methodology for durability estimation of surface mount interconnects under drop testing conditions. Microelect Reliab 2007;47(1):93–103. [6] Varghese J, Dasgupta A. An experimental approach to characterize ratedependent failure envelopes and failure site transitions in surface mount assemblies. Microelect Reliab 2007;47(7):1095–102. [7] Zhu LP. Modeling technique for reliability assessment of portable electronic product subjected to drop impact loads. In: Proceedings of 53rd electronic components and technology conference, New Orleans, LA; 2003. p. 100–104. [8] Lim CT, Ang CW. Drop impact survey of portable electronic products. In: Proceedings of 53rd electronic components and technology conference, New Orleans, LA, 2003. p. 113–120. [9] Tee TY, Luan J, Ng HS. Development and application of innovational drop impact modeling techniques. In: Proceedings of 55th electronic components and technology conference, Orlando, FL; 2005. p. 504–12. [10] Tan VBC, Tong MX, et al. Finite element modeling of electronic packages subjected to drop impact. IEEE Trans Components Packag Technol 2005;28(3):555–60. [11] Luan JE, Tee TY, et al. Dynamic responses and solder joint reliability under board level drop test. Microelect Reliab 2007;47(2–3):450–60. [12] Alajoki M, Nguyen L, Kivilahti J. Drop test reliability of wafer level chip scale packages. In: Proceedings of 55th electronic components and technology conference. Orlando, FL; 2005. p. 637–44. [13] Chong DYR, Che FX, et al. Drop impact reliability testing for lead-free and leadbased soldered IC packages. Microelect Reliab 2006;46(7):1160–71. [14] Luan JE, Tee TY. Normal board level drop test simulation using implicit transient analysis with input-G method. In: Proceedings 5th international conference on electronic packaging technology, Singapore; 2004. p. 671–7. [15] Wang YY, Wang F, Chai TC. Finite element modeling of CSP package subjected to board level drop test. In: Proceedings of 5th international conference on electronic packaging technology, Singapore; 2004. p. 684–8. [16] Zhao JF, Garner LJ. Mechanical modeling and analysis of board level drop test of electronic package. In: Proceedings of 56th electronic components and technology conference, San Diego, CA; 2006. p. 436–42. [17] Lall P, Gupte S, et al. Solder joint reliability in electronics under shock and vibration using explicit finite-element submodeling. In: Proceedings of 56th electronic components and technology conference. San Diego, CA; 2006. p. 428–35. [18] Syed A, Kim SM, et al. A methodology for drop performance prediction and application for design optimization of chip scale packages. IEEE Trans Elect Packag Manuf 2007;30(1):42–8. [19] Zhao JF, Liu F, et al. Improvement of JEDEC drop test in SJR qualification through alternative test board design. In: Proceedings of 57th electronic components and technology conference, Reno, NV; 2007. p. 946–50. [20] JEDEC Standard JESD22-B111, Board level drop test method of components for handheld electronic products; 2003. [21] Liu F, Meng G, et al. Board level drop test analysis based on modal test and simulation. ASME J Elect Packag 2008;130(2):021007 (6 pages). [22] ABAQUS User Manual (version 6.5), ABAQUS, Inc.; 2005.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Experimental and numerical analysis of BGA lead-free solder joint reliability under board-level drop impact Fang Liu a,*, Guang Meng a, Mei Zhao a, Jun feng Zhao b a b
State Key Laboratory of Mechanical System and Vibration, Shanghai Jiao Tong University, 800 Dongchuan Road, Shanghai 200240, PR China Intel Technology Development Shanghai Ltd., 999 Yinglun Road, Shanghai 200131, PR China
a r t i c l e
i n f o
Article history: Received 20 June 2007 Received in revised form 21 August 2008 Available online 12 December 2008
a b s t r a c t Board-level solder joint reliability is very critical for handheld electronic products during drop impact. In this study, board-level drop test and finite element method (FEM) are adopted to investigate failure modes and failure mechanisms of lead-free solder joint under drop impact. In order to make all ball grid array (BGA) packages on the same test board subject to the uniform stress and strain level during drop impact, a test board in round shape is designed to conduct drop tests. During these drop tests, the round printed circuit board assembly (PCBA) is suffered from a specified half-sine acceleration pulse. The dynamic responses of the PCBA under drop impact loading are measured by strain gauges and accelerometers. Locations of the failed solder joints and failure modes are examined by the dye penetration test and cross section test. While in simulation, FEM in ABAQUS software is used to study transient dynamic responses. The peeling stress which is considered as the dominant factor affecting the solder joint reliability is used to identify location of the failed solder joints. Simulation results show very good correlation with experiment measurement in terms of acceleration response and strain histories in actual drop test. Solder joint failure mechanisms are analyzed based on observation of cross section of packages and dye and pry as well. Crack occurred at intermetallic composite (IMC) interface on the package side with some brittle features. The position of maximum peeling stress in finite element analysis (FEA) coincides with the crack position in the cross section of a failed package, which validated our FEA. The analysis approach combining experiment with simulation is helpful to understand and improve solder joint reliability. Crown Copyright Ó 2008 Published by Elsevier Ltd. All rights reserved.
1. Introduction With the popularity of portable telecommunication devices such as mobile phones and PDAs, reliability of handheld electronic products has become a major concern recently. These handheld electronic products are more prone to being accidentally dropped during their useful service life, and drop impact can cause not only housing crack, but also package to board interconnect failures. In the past several years, a lot of drop tests have been conducted for board-level [1–6] and product level drop tests [7,8]. On one hand, board-level tests simplify real drop impact conditions, on the other hand, they are more controllable than product level tests, and are more convenient to characterize the solder joint performance. So a JEDEC working group developed a standard board-level drop test for handheld electronic products in 2003. However, comparing with actual drop test, which is expensive, time-consuming, and requires much more manpower in measurement and failure analysis, finite element (FE) modeling is proven to be a very efficient tool and has been applied widely for the modeling * Corresponding author. Tel.: +86 21 34206664x319; fax: +86 21 34206006. E-mail address: [email protected] (F. Liu).
and simulation for board-level drop tests in order to reveal the structural responses and failure mechanisms of the board-level PCBA subjected to drop impact [9,10]. In recent years, numerous studies have been devoted to the understanding of structural responses and failure mechanisms of board-level test vehicle subjected to drop impact, but currently there is less comprehensive work on dynamic responses of PCBA by both drop experiment and drop simulations [11]. Generally, drop tests were conducted to investigate the effects of different factors on solder joint reliability, such as package types, pad structures, solder bumps, solder compositions [2,12,13]. For board-level drop simulation, Luan and his co-authors developed a novel inputG method to simplify drop simulation [14]. So FEM has been used widely for the simulation of electronic packaging problems. However, most papers [15–18] focused on how to choose a good simulation methodology and discussing the affecting factors of simulation results, such as mesh density, element types and material models. In fact, if drop tests were combined with drop simulation, more excellent results would be obtained. As we all know, the dynamic strains and stresses of solder joints directly affect the solder joint reliability during drop impact, but there is no suitable sensor to measure them directly. Alternatively, the dynamic re-
0026-2714/$ - see front matter Crown Copyright Ó 2008 Published by Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.10.014
80
F. Liu et al. / Microelectronics Reliability 49 (2009) 79–85
sponses of printed circuit board (PCB) are good measurable indicators which are closely related to solder joint strains and stresses. If a FE model could be proved to be effective by test results, dynamic responses of critical solder joint would be obtained by FE simulation, which can help to reveal the mechanical behaviors or the failure mechanisms of solder joints. Thus, testing and simulating, based on drop test and FEM, will be effective to analyze dynamic responses of PCBA. This paper aims to investigate the dynamic behaviors of PCBA in the round shape under drop impact loading and study the root cause of lead-free solder joint failure. A new round test board with eight BGA packages is designed. Firstly, the round test board is dropped from a specified height (0.34 m), and subjected to a half-sine acceleration pulse (1500 Gs, 0.55 ms). At the same time, strain and acceleration histories of the test board are measured. Secondly, ABAQUS software is used to simulate dynamic responses of the test board and model strains and stresses of solder joints. Based on experiment and FE results, board-level drop impact performance of BGA lead-free solder joint for handheld electronic product is studied. Finally, dye penetration test and microscopic test are chosen to examine the failure locations and failure mechanisms of lead-free solder joints. 2. Drop test 2.1. Test vehicle BGA packages can meet with the increasing demands on miniaturization and high performance of portable electronic products. So in this study, eight BGA packages are selected for drop test. These BGA packages numbered from 1 to 8 were mounted centrosymmetrically on a round PCB (160 mm diameter, 1 mm thickness), shown in Fig. 1. The detailed design process has been demonstrated in another paper [19]. Thus, eight packages will be exposed to a uniform test condition. The diameter of solder ball is 0.35 mm and ball pitch is 0.8 mm. Via-in-pad structure is adopted. In the surface mount process, the Sn–3Ag–0.5 Cu solder paste is employed for lead-free solders.
2.2. Drop test system A drop test setup used in the drop test is similar to drop setup of JEDEC standard [20] (see Fig. 2). The PCBA is fixed on base plate (165 mm 165 mm 32 mm) of the drop test setup with eight standoffs. Between the test board and surface of the base plate, 20 mm standoff is added to allow PCB bending freely. Ideally, the standoffs should be rigid and move simultaneously with the drop table during the drop impact process. In the drop impact tests, the PCB is always positioned in horizontal direction with packages facing downwards. The drop height and impact pulse are controlled. The drop table is released and dropped freely at a certain height to hit on the strike surface, and a high G acceleration pulse is created. In the course of drop test, the dynamic responses of PCB are crucial because they reflect the mechanical behaviors of PCB, which are closely related to solder joint failure during drop impact. Test instruments, which form a drop test system, can carry out testing, and some correlative data are acquired. The block diagram for drop test system is schematically shown in Fig. 3. It can be seen from Fig. 3 that all test instruments are utilized during the drop test. Firstly, two accelerometers are used in the test to determine the acceleration responses of the round test board subjected to drop impact. One accelerometer is attached to the base plate close to one of the support locations to monitor peak acceleration (Gm) and duration (T) of the half-sine impact pulse (input acceleration applied to the PCB), the other is mounted at the center of the PCBA (non-component) to characterize the output acceleration responses of the PCBA. Two acceleration signals via charge amplifiers are sent to LMS Test Lab that records down the input and output accelerations of the PCB. Secondly, dynamic strain meter is setup to measure in-plane strains of the PCB. Two strain gauges connected to dynamic strain meter, are located on the back of the critical solder joint (non-component side of the PCB) to measure the dynamic strains induced in circumferential and radial directions of the PCB. Finally, a digital oscilloscope is adopted in order to measure dynamic voltage of dynamic resistance of daisy chain of solder joints. There are two daisy chain loops for each BGA package with outer and inner loops. The principal circuit is shown in Fig. 4. A resistor, R0, is placed in series to the outer/inner daisy chain loop of solder joints and connected to a DC power supply. The dynamic resistance of the outer/inner loop, Rx, can be given by
Rx ¼
R0 V R0 ¼ E V E=V 1
ð1Þ
where E is the voltage (5.0 V) of the DC power supply, and V is the dynamic voltage of outer/inner daisy chain loop, which changes with dynamic resistance of outer/inner loop, Rx. For convenience, V is monitored instead of resistance using a digital oscilloscope. When V approaches to E, Rx will be close to 1 (open circuit), which suggests that the critical solder joint has failed. 2.3. Repeatability of drop test
Fig. 1. Round test board.
Good repeatability of dynamic responses is very important for the life-expectancy prediction of solder joints under impact load, so a trial and error process is required to calibrate and characterize a drop tester to achieve the required impact pulse before actual drop testing can be performed. Continual eight drops are conducted to check the repeatability of testing results, and impact pulse is measured. In Fig. 5 the input acceleration pulses of eight drops display excellent repeatability. It implies that the drop test system is under good control. For instance, the round PCB mounted by eight screws is dropped from 0.34 m height (Gm = 1500 G and T = 0.55 m) in total eight times. The tolerances of acceleration peak 1500 G and pulse duration 0.55 ms are within ±6%, respectively.
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Fig. 2. Typical drop test setup.
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44
53
24
9
10
27
40
25
26
43
56
41
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39 23 7
28 12 13
29 46
6
30
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14 15
16
31 47 57
5
32 48
1 17 33
2
3
22 21 20
38
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19 18 34
35 51
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Fig. 3. Block diagram for drop test system.
sured strain values and acceleration responses can also be used for verification of FE results. 3. Drop simulation 3.1. FE model
Fig. 4. Dynamic resistance monitoring system.
Thus, drop test can be conducted repeatedly. During drop test, some relative data can be gained, such as in-plane strains of the PCB, input/output acceleration, and cracked solder joints. The mea-
In order to understand transient dynamic responses of the round test board under high G acceleration pulse, commercial software ABAQUS is used to do drop simulation. The geometry model of the PCBA is very simple, and material parameters, boundary condition and damping ratio may be determined by some modal tests. Based on modal tests and simulation, how to establish a valid FE model have been demonstrated in the other paper [21]. Thus, it is easy to use input-G method to do FE analysis very well. Due to centrosymmetric structure of the PCBA, a FE model with one eighth of the round test board (shown in Fig. 6) is used in drop simulation
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Fig. 7. Comparison of strain (radial) curves.
Modeling vs. Experiment Modeling
Fig. 5. Acceleration pulse of eight drops.
in order to reduce computing cost. Mesh of the model is coarse and element type is C3D8R. The FE model includes 22659 elements and 31405 nodes. Input acceleration is the same as the acceleration of our drop test, and the initial velocity of simulation is
v0 ¼
pffiffiffiffiffiffiffiffi 2gh
Microstrains (µε)
Experiment
ð2Þ
where, h is drop height, g is gravity acceleration. So it is easy to perform FE analysis if algorithms and solvers are chosen properly.
Fig. 8. Comparison of strain (circumferential) curves.
3.2. Algorithms and solvers Three solvers in ABAQUS can be used in dynamics simulation. These solvers are explicit solver, modal dynamic solver and implicit solver, respectively. Which solver should be chosen? The explicit solver is conditionally stable and stability limit is closely related to the time required for a stress wave to cross the smallest element dimension [22]
Dt ¼
Lmin Cd
Time (ms)
ð3Þ
where Lmin is the smallest element dimension, and Cd is a material constant. This stability limit is automatically calculated by ABAQUS by default and therefore ABAQUS can produce very accurate results in explicit solver. Since the Lmin is generally very small (generally dominated by the solder ball mesh), the computing time is very long. The damping effects will greatly increase the computing time, so the explicit solver is not recommended to do the simulation. In modal dynamics solver, the accuracy depends on how many modes are used in superposition. Since the computing cost is low,
Fig. 6. FE model of one eighth of the round test board.
F. Liu et al. / Microelectronics Reliability 49 (2009) 79–85
we can consider tens of modes in the modeling to increase the accuracy. Nevertheless, one has to keep in mind that modal superposition is only valid when the test vehicle is linearly elastic. Test board is subjected to high G acceleration pulse (1500 G, 0.55 ms half-sine pulse). The center displacement of test board is larger than the board thickness (1 mm), thus modal dynamics solver is not recommended either. Though the implicit solver is unconditionally stable, its accuracy is dependent on the half-step residual tolerance, Rt+Dt/2, which is specified by the user. If only the Rt+Dt/2 is determined well, the accuracy of simulating results will be high. Based on computing time and geometric nonlinearity, the implicit solver in ABAQUS is chose to do drop simulation analysis.
the maximum peeling stress of lead-free solder joint is the dominant stress component, which affects the solder joint reliability during drop impact [1,4], thus the peeling stress of solder joints (S33) is employed to estimate which solder joint will be vulnerable to fail at first. The mesh of the solder joint is very coarse and theoretically the stress value is singular at the corner of solder joint/ copper pad, so the output stress is centroidal stress of the element. In the modeling, the peeling stress in the direction of drop is selected as an indicator which determines the initial crack of solder
4. Results and discussions 4.1. Dynamic responses Drop test results could be used to check the model quality and increase the confidence on the numerical results. It can be shown in Figs. 7 and 8 that the time-dependent dynamic strains in radial and circumferential directions predicted by FE simulation agree well with the measured strains at package corner, especially the circumferential strain. In Fig. 8, the dynamic strain of the PCB in circumferential direction predicted by modeling correlates very well with that measured by the drop test, and the amplitudes of the PCB strains decrease gradually with time. Furthermore, a good agreement between measured and computed acceleration profiles can be seen from Fig. 9. The output acceleration history of the PCB center by FE simulation is similar to the result of actual drop test. In one word, FE simulation results are well consistent with that measured by actual drop tests, which means that the FE model can be used to predict reliability and life of solder joints under board-level drop impact condition. Good correlation in dynamic responses of the PCBA will contribute to study solder joint reliability and impact life, and the effective model can be used to optimize design of PCBA for drop impact loading and enhance reliability of solder joints.
Fig. 10. Maximum peeling stress of the solder ball at different l.
4.2. Failure analysis Since PCB bending vibration is the major failure cause of leadfree solder joints under drop impact, and the peeling stress is induced mainly by PCB bending vibration and mechanical shock,
Modeling Vs. Experiment Modeling
Fig. 11. Maximum peeling stress of the critical solder ball.
Acceleration (G)
Experiment
Time (ms) Fig. 9. Center acceleration response of round PCBA.
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Fig. 12. Peeling stress time-history of the critical solder ball.
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F. Liu et al. / Microelectronics Reliability 49 (2009) 79–85
Fig. 13. Center displacement of round PCBA. Fig. 14. Dye stain photo.
joints. That is to say, the bigger the peeling stress of a location is, the more vulnerable the location is. It can be seen from Fig. 10 that the maximum peeling stress of the critical functional ball is 190.92 MPa, and there is larger peeling stress at the solder joints which locate at the outermost corner of packages. These solder balls at the outermost corner are critical solder joints, and would be very vulnerable to crack. From Fig. 11, it can be estimated that the maximum peeling stress appears in the region between package and the solder joint, and it can be also inferred that the initial
crack would occur near the region. Fig. 12 depicts peeling stress time-history of the critical solder joint. Center displacement of round PCBA is given in Fig. 13. Due to drop impact, the PCBA is firstly subjected to a huge mechanical shock, and then the center displacement and the peeling stress both arrive at the maximum value immediately. After that, the PCBA is suffered from a cyclic bending vibration. From Figs. 12 and 13, it can be seen that the
Fig. 15. Optical cross section photos of failed solder joint.
F. Liu et al. / Microelectronics Reliability 49 (2009) 79–85
peeling stress and the center displacement decrease gradually with time. Since BGA packages mounted on the PCB are generally not as flexible as the board, the bending of the board and relatively higher rigidity of the BGA package exerts tensile forces on solder joints. The solder joints will endure cyclic peeling stress and compressive stress. This ultimately causes failures in solder joints. Thus, it can be concluded that the combined effect of great mechanical shock and bending vibration is the major failure cause of solder joint when PCB is subjected to drop impact. In addition, the failure location, failure interface, and failure mode are all verified by dye penetration test photo and cross section photos. The critical solder balls occur at the outermost corner, and fail along the solder and package pad interface. It can be seen from Fig. 14 that three solder balls at outermost corner have failed, and it is shown from Fig. 15 that the failure interface of critical solder ball is at IMC interface on the package side. So the location of the maximum peeling stress predicted by modeling agrees well with actual failure location observed in drop test, and it is also proven that the maximum peeling stress could be used as a failure indicator to determine the first failure location. 5. Conclusions In order to investigate the cause of lead-free solder joint failure under drop impact, the dynamic behaviors of the PCBA under board-level drop impact loading are studied and analyzed by both drop test and drop simulation in detail. The following conclusions are drawn. (1) The established FE model is enormously simple and effective, the dynamic responses, such as output acceleration, strains are well correlated between testing and simulating. This will help to establish a more accurate impact life prediction model of solder joint. (2) The peeling stress of the critical solder joint in FE simulation could be considered to be the dominant failure factor, which correlates well with the observations by experiment. When the maximum peeling stress is used as a failure indicator to determine initial failure location of solder joints, numerically predicted failure locations of the solder joints accord with those observed from drop impact tests. (3) It can be concluded that the combined effect of mechanical shock and PCB bending vibration is the root cause of solder joint failure under drop impact. Acknowledgements This work was supported by NSFC (No. 50775138) and a research collaboration project between Intel and SJTU.
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