Experimental observation of gate geometry ... - Semantic Scholar
Microelectronics Reliability 52 (2012) 1936–1939
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Experimental observation of gate geometry dependent characteristic degradations of the multi-finger MOSFETs Mingu Kang, Ilgu Yun ⇑ Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Republic of Korea
a r t i c l e
i n f o
Article history: Received 29 May 2012 Received in revised form 12 June 2012 Accepted 13 June 2012 Available online 6 July 2012
a b s t r a c t In this paper, the characteristic degradations of multi-finger MOSFETs with different gate structures are experimentally investigated when the gate voltage stress is applied. Here, the degradations of threshold voltage (Vth), subthreshold swing (Ssub), and mobility are analyzed depending on the gate geometry. In addition, the correlation between the gate structure considering the effective channel length and the charge trapping effect due to line edge roughness is also investigated using the charge trap density and the off current. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction As the down scaling has been progressed in recent years, the size of the MOSFET is reduced drastically. Down scaling depending on the gate structure variation affects the device electrical characteristics. Several problems are magnified as an inevitable phenomenon, such as random dopant fluctuation (RDF) and line edge roughness (LER) due to the patterning. Especially, the LER causes serious problems and effects on the device parameter and performance. Thus, LER is an important factor that must be considered, so many studies are ongoing to determine the impact of LER [1,2]. This paper shows how different gate structures affect the device characteristics when voltage stress is applied to the gate. This focuses how it responses to the gate voltage stress and how the degradation progresses. From the stress experiments, we can understand the effects of the gate structural variation according to the applied voltage stress. Shapes of the gate structures are artificially made with embossed and engraved gate structures considering LER to see the gate structural effects. According to the test results, reliability of the MOSFET can be analyzed and geometric variation effects can be estimated. Also through this, the causes of characteristic variation and device degradation can be explained. The gate structural variation which is based on the change of gate length and shape affects the reliability of the devices. 2. Methodology 2.1. Test structure fabrication In this paper, the three groups of multi-finger MOSFET test structures are fabricated using Samsung 0.13 lm process and the ⇑ Corresponding author. Tel.: +82 2 2123 4619; fax: +82 2 313 2879. E-mail address: [email protected] (I. Yun). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.06.022
schematic diagram of the test structures is shown in Fig. 1. The fabricated test structures are only the 4-finger n-MOSFETs and the gate oxide thickness is to be 7.2 nm. The group A is composed of the three engraved structures. These middle portions of the gate structure are reduced from 260 nm to 140 nm with a 45° angle. The middle width for the three test structures are increased 1, 3, and 5 lm, respectively. The group B is consisted of the three embossed structures. These middle lengths of the gate structure are increase from 140 nm to 260 nm with a 45° angle as opposed to group A. Here, the lengths of middle width for the three test structures are also increased 1, 3, and 5 lm, respectively. Finally, group C is composed of the two test structures with the rectangular gate structure where the lengths are 140 nm and 260 nm, respectively, as a reference test sets. The test structure information used in this work is summarized in Table 1. 2.2. Test conditions and measurements In this paper, the test patterned structures are manufactured in a common-source configuration. The tested devices are stressed by applying the gate voltage. The gate bias is applied with value of 0.5 V for 1800 s (30 min). The measurement of the test patterned structures is performed for an interval of 300 s. In order to confirm the reproducibility, 3 tested devices for each test structure are measured. For the current–voltage (I–V) characteristics, HP 4145B semiconductor parameter analyzer is used. To obtain the output characteristics (ID–VDS), the drain voltage is measured from 0 V to 1.2 V while the gate voltage is increased from 0.3 V to 1.2 V with a step of 0.3 V. In addition, the transfer characteristics (ID-VG) is derived by sweeping the gate voltage from 0.0 V to 1.2 V while the drain voltage is increased from 0.1 V to 0.7 V with a step of 0.2 V. Based on the measurement, the electrical characteristics of the test structures, such as the transfer and output characteristics, are obtained
1937
M. Kang, I. Yun / Microelectronics Reliability 52 (2012) 1936–1939
Fig. 1. Schematic information of the test structures: (a) Group A, (b) Group B, and (c) Group C. Fig. 2. Normalized Vth variations versus stress time.
and the MOSFET characteristics, such as threshold voltage (Vth), subthreshold swing (Ssub), and field effect mobility (lFEmax) are extracted. Here, Vth is extracted using the extrapolation in the linear region method and lFEmax is extracted from the transfer characteristic when VDS = 0.1 V, which is operated in a linear mode [3]. For the stress effect on the different gate structured MOSFETs, the variations of the Vth, Ssub, and lFEmax are analyzed. In addition, the density of trap states (Ntrap), and off current are also calculated to analyze the effects. 3. Results and discussion 3.1. Threshold voltage (Vth) variation Fig. 2 shows the variations of Vth when the voltage applied to the gate. As the stressing time is increased, the changes of Vth are increased. It is also noted that when the length of the device is reduced, variation of Vth is increased. As the shorter length devices, the device receives a lot of the gate voltage stress over an area since the applied stress voltage creates the defect state and increases density of traps in the near mid gap, it leads Vth shift [4]. Changing in mid gap interface trap density affects the electrical characteristic. Vth shift is explained by a process for electron capture by hole trapping [5]. The loss of electron is gradually increased. Thus, Vth degradation is generated by defect state. Defect states impact also the off current which is very important for the MOSFET device performance. Another reason is that Vth variations can be closely associated with the non-uniform electric field problems by gate geometry considering LER [2]. Depending on the difference between gate geometries, the e-field is formed differently. In particular, e-field difference is very large at the corner in the structure of gate finger. Also, it is affected by the engraved shape and the embossed shape of the gate geometry. Non-uniform e-field can modulate the cur-
rent flow and charge mobility. So, gate geometry considering LER effects influence the variations on Vth in the short channel. 3.2. Subthreshold swing (Ssub) variation Ssub variation results are shown in Fig. 3. It is observed that the degradation is dependent on the stressing time which is the same trend of the threshold voltage shift case. As the stress time is increased, Ssub variation is increased since Ssub is associated with the trap density in the mid gap area [6]. It is observed that the engraved and the embossed shape of the gate geometries affect differently Ssub variation. Fig. 3 shows that the embossed structures (group B) have larger variations than the engraved structure about the same effective length. As Ssub variation is increased, the slope of the transfer characteristics (ID–VG) is reduced. It means that the operating device characteristics are degraded due to the gate stress voltage. Thus, it can be concluded that the different effective length and the structural shape impact the variations of Ssub. 3.3. Field effect mobility (lFEmax) variation In general, lFEmax is one of the device characteristics that can track degradation of the device. Fig. 4 is the results of the calculated of lFEmax which is also affected by the stress time. The degradation of lFEmax is attributed to the trap density induced by the stress voltages. It is found that the mobility is the most affected parameter by the stress due to the gate structure difference. It is indicated that the embossed structures (group B) have larger variations than the engraved structure (group A) with about the same effective length. The charge trapping affects the flow of current so that it accelerates the degradation of the mobility [7].
Table 1 Summary of the test structure information. Group
Name
X (lm)
Y (lm)
Z (lm)
Gate width (lm)
Gate dimension (lm2)
A
A1 A2 A3
1 3 5
– – –
– – –
6
5.76 4.8 3.84
B
B1 B2 B3
– – –
1 3 5
– – –
6
3.84 4.8 5.76
C
C1 C2
– –
– –
0.14 0.26
6
3.36 6.24
1938
M. Kang, I. Yun / Microelectronics Reliability 52 (2012) 1936–1939
Fig. 5. The density of trap states of each test structures. Fig. 3. Normalized Ssub variations versus stress time.
Fig. 6. The off currents of the test structures.
Fig. 4. Normalized lFEmax variations versus stress time.
3.4. Charge trap density (Ntrap) and off current (Ioff) We can see variations about the electrical characteristics, namely the Vth, Ssub variation, and lFEmax. Especially, Ssub is associated with the density of trap states at the semiconductor and insulator interface. From the relationship of Ssub and Ntrap is calculated by the following relation [8]:
Ntrap ¼
log e C ins Ssub 1 kT=q q
ð1Þ
Fig. 5 shows the variation of density of trap state through calculation for each test structures. Here, we measured 3 sample devices for each test structure to calculate the mean and the standard deviation for the verification of the statistical significance. Density of trap state is affected by the gate structural geometry. As shown before, the variation rate is dependent on the different structures. The test patterns used in this work have shown that the embossed structures (group B) have larger variations than the engraved structure (group A) even though they have the same effective channel length. That is because location and shape of the devices are affected on characteristic variations. Depending on the structure of the gate, especially folded or bent structure, the electric field is generated differently [9]. The electric field will be different for each test structures at the corner and patterned regions. Non-uniform electric field problem can affect the operating characteristics of the devices. In particular, the current flow and charge mobility can be affected significant by the electric field.
In addition, these results have shown that structural difference considering line edge roughness causes variations of the devices in the short channel [9]. As close to the gate edge, both the fixed oxide charge and interface state density are increased [7]. The embossed structures (group B) have thinner ends than engraved structures (group A). This can increase the trap density at the end of the gate and make different group B and group A. Therefore, the structural differences in the gate region due to the line edge roughness can affect the distribution of generated defects which impact the degradation of the device characteristics. In order to confirm the relationship between the trap density and the electrical characteristics, the off currents of the tested devices are also obtained from the measurement data. Here, the off current (Ioff) is defined as a current between source and drain when the gate voltage is fixed at 0.9 V and drain voltage is set to be zero. In addition, we also measured 3 sample devices for each test structure to calculate the mean and the standard deviation for the verification of the statistical significance. The off currents of different gate structures are shown in Fig. 6. The structural differences in the gate region due to the LER can affect the off currents [10]. As shown in Fig. 6, the shorter effective gate length device shows the higher increment of the off currents. Since the off current of the embossed structures (group B) is larger than that of the engraved structures (group A), the embossed structures (group B) have larger degradation of the electrical characteristics which is in good agreement with the previous results.
M. Kang, I. Yun / Microelectronics Reliability 52 (2012) 1936–1939
1939
4. Conclusion
References
In this paper, the multi-finger MOSFETs with different gate structures were used to investigate the degradation of the electrical characteristics when the gate bias stress is applied. From the experimental results, degradations of Vth, Ssub, and lFEmax were observed. In order to analyze the degradation effects, the charge trap density and the off current were examined to verify the degradation mechanism. Based on these results, it can be concluded that even though the structure have the same effective gate length, the structural differences in the gate region can affect the distribution of generated defects which resulted in different degradation characteristics when the gate voltage is applied at operating condition. This can allow us to provide the design guideline for the gate geometric structure of the multi-finger MOSFETs for electronic device applications.
[1] Leonardus H, Leunissen A, Jonckheere R, Ronse K, Derksen GB. Influence of gate patterning on line edge roughness. J Vac Sci Technol B 2003;21:3140–3. [2] Diaz CH, Hun-Jan T, Ching KY, Yen A, Young K. An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling. IEEE Electron Dev Lett 2001;22:287–9. [3] Conde AO, García Sánchez FJ, Liou JJ, Cerdeira A, Estrada M, Yue Y. A review of recent MOSFET threshold voltage extraction method. Microelectron Reliab 2002;42:583–96. [4] Grasser T, Gos W, Sverdlov V, Kaczer B. The universality of NBTI relaxation and its implications for modeling and characterization. Intl Reliab Phys Symp (IRPS) 2007;40:268–80. [5] Lai SK. Interface trap generation in silicon dioxide when electrons are captured by trapped holes. J Appl Phys 1983;54:2540–6. [6] Kouvatsos DN, Vamvakas VE, Davazoglou D. Electrical stressing induced degradation effects in solid phase crystallized polysilicon thin film transistors. Intl Conf Microelectron (MIEL) 2002;2:713–6. [7] Yamamoto T, Uwasawa K, Mogami T. Bias temperature instability in scaled p+ polysilicon gate p-MOSFET’s. IEEE Trans Electron Dev 1999;46:921–6. [8] Cross RBM, De Souza MM, Young ND. A comparison of the performance and stability of ZnO-TFTs with silicon dioxide and nitride as gate insulators. IEEE Trans Electron Dev 2008;55:1109–15. [9] Giraldo A, Paccagnella A, Minzoni A. Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout. Solid-State Electron 2000;44:981–9. [10] Dong KS, Wada H, Woo JCS. TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling. IEEE Trans Semiconduct Manufact 2004;17:192–200.
Acknowledgement This work has been supported by the IC Design Education Center.
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Experimental observation of gate geometry dependent characteristic degradations of the multi-finger MOSFETs Mingu Kang, Ilgu Yun ⇑ Department of Electrical and Electronic Engineering, Yonsei University, Seoul, Republic of Korea
a r t i c l e
i n f o
Article history: Received 29 May 2012 Received in revised form 12 June 2012 Accepted 13 June 2012 Available online 6 July 2012
a b s t r a c t In this paper, the characteristic degradations of multi-finger MOSFETs with different gate structures are experimentally investigated when the gate voltage stress is applied. Here, the degradations of threshold voltage (Vth), subthreshold swing (Ssub), and mobility are analyzed depending on the gate geometry. In addition, the correlation between the gate structure considering the effective channel length and the charge trapping effect due to line edge roughness is also investigated using the charge trap density and the off current. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction As the down scaling has been progressed in recent years, the size of the MOSFET is reduced drastically. Down scaling depending on the gate structure variation affects the device electrical characteristics. Several problems are magnified as an inevitable phenomenon, such as random dopant fluctuation (RDF) and line edge roughness (LER) due to the patterning. Especially, the LER causes serious problems and effects on the device parameter and performance. Thus, LER is an important factor that must be considered, so many studies are ongoing to determine the impact of LER [1,2]. This paper shows how different gate structures affect the device characteristics when voltage stress is applied to the gate. This focuses how it responses to the gate voltage stress and how the degradation progresses. From the stress experiments, we can understand the effects of the gate structural variation according to the applied voltage stress. Shapes of the gate structures are artificially made with embossed and engraved gate structures considering LER to see the gate structural effects. According to the test results, reliability of the MOSFET can be analyzed and geometric variation effects can be estimated. Also through this, the causes of characteristic variation and device degradation can be explained. The gate structural variation which is based on the change of gate length and shape affects the reliability of the devices. 2. Methodology 2.1. Test structure fabrication In this paper, the three groups of multi-finger MOSFET test structures are fabricated using Samsung 0.13 lm process and the ⇑ Corresponding author. Tel.: +82 2 2123 4619; fax: +82 2 313 2879. E-mail address: [email protected] (I. Yun). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.06.022
schematic diagram of the test structures is shown in Fig. 1. The fabricated test structures are only the 4-finger n-MOSFETs and the gate oxide thickness is to be 7.2 nm. The group A is composed of the three engraved structures. These middle portions of the gate structure are reduced from 260 nm to 140 nm with a 45° angle. The middle width for the three test structures are increased 1, 3, and 5 lm, respectively. The group B is consisted of the three embossed structures. These middle lengths of the gate structure are increase from 140 nm to 260 nm with a 45° angle as opposed to group A. Here, the lengths of middle width for the three test structures are also increased 1, 3, and 5 lm, respectively. Finally, group C is composed of the two test structures with the rectangular gate structure where the lengths are 140 nm and 260 nm, respectively, as a reference test sets. The test structure information used in this work is summarized in Table 1. 2.2. Test conditions and measurements In this paper, the test patterned structures are manufactured in a common-source configuration. The tested devices are stressed by applying the gate voltage. The gate bias is applied with value of 0.5 V for 1800 s (30 min). The measurement of the test patterned structures is performed for an interval of 300 s. In order to confirm the reproducibility, 3 tested devices for each test structure are measured. For the current–voltage (I–V) characteristics, HP 4145B semiconductor parameter analyzer is used. To obtain the output characteristics (ID–VDS), the drain voltage is measured from 0 V to 1.2 V while the gate voltage is increased from 0.3 V to 1.2 V with a step of 0.3 V. In addition, the transfer characteristics (ID-VG) is derived by sweeping the gate voltage from 0.0 V to 1.2 V while the drain voltage is increased from 0.1 V to 0.7 V with a step of 0.2 V. Based on the measurement, the electrical characteristics of the test structures, such as the transfer and output characteristics, are obtained
1937
M. Kang, I. Yun / Microelectronics Reliability 52 (2012) 1936–1939
Fig. 1. Schematic information of the test structures: (a) Group A, (b) Group B, and (c) Group C. Fig. 2. Normalized Vth variations versus stress time.
and the MOSFET characteristics, such as threshold voltage (Vth), subthreshold swing (Ssub), and field effect mobility (lFEmax) are extracted. Here, Vth is extracted using the extrapolation in the linear region method and lFEmax is extracted from the transfer characteristic when VDS = 0.1 V, which is operated in a linear mode [3]. For the stress effect on the different gate structured MOSFETs, the variations of the Vth, Ssub, and lFEmax are analyzed. In addition, the density of trap states (Ntrap), and off current are also calculated to analyze the effects. 3. Results and discussion 3.1. Threshold voltage (Vth) variation Fig. 2 shows the variations of Vth when the voltage applied to the gate. As the stressing time is increased, the changes of Vth are increased. It is also noted that when the length of the device is reduced, variation of Vth is increased. As the shorter length devices, the device receives a lot of the gate voltage stress over an area since the applied stress voltage creates the defect state and increases density of traps in the near mid gap, it leads Vth shift [4]. Changing in mid gap interface trap density affects the electrical characteristic. Vth shift is explained by a process for electron capture by hole trapping [5]. The loss of electron is gradually increased. Thus, Vth degradation is generated by defect state. Defect states impact also the off current which is very important for the MOSFET device performance. Another reason is that Vth variations can be closely associated with the non-uniform electric field problems by gate geometry considering LER [2]. Depending on the difference between gate geometries, the e-field is formed differently. In particular, e-field difference is very large at the corner in the structure of gate finger. Also, it is affected by the engraved shape and the embossed shape of the gate geometry. Non-uniform e-field can modulate the cur-
rent flow and charge mobility. So, gate geometry considering LER effects influence the variations on Vth in the short channel. 3.2. Subthreshold swing (Ssub) variation Ssub variation results are shown in Fig. 3. It is observed that the degradation is dependent on the stressing time which is the same trend of the threshold voltage shift case. As the stress time is increased, Ssub variation is increased since Ssub is associated with the trap density in the mid gap area [6]. It is observed that the engraved and the embossed shape of the gate geometries affect differently Ssub variation. Fig. 3 shows that the embossed structures (group B) have larger variations than the engraved structure about the same effective length. As Ssub variation is increased, the slope of the transfer characteristics (ID–VG) is reduced. It means that the operating device characteristics are degraded due to the gate stress voltage. Thus, it can be concluded that the different effective length and the structural shape impact the variations of Ssub. 3.3. Field effect mobility (lFEmax) variation In general, lFEmax is one of the device characteristics that can track degradation of the device. Fig. 4 is the results of the calculated of lFEmax which is also affected by the stress time. The degradation of lFEmax is attributed to the trap density induced by the stress voltages. It is found that the mobility is the most affected parameter by the stress due to the gate structure difference. It is indicated that the embossed structures (group B) have larger variations than the engraved structure (group A) with about the same effective length. The charge trapping affects the flow of current so that it accelerates the degradation of the mobility [7].
Table 1 Summary of the test structure information. Group
Name
X (lm)
Y (lm)
Z (lm)
Gate width (lm)
Gate dimension (lm2)
A
A1 A2 A3
1 3 5
– – –
– – –
6
5.76 4.8 3.84
B
B1 B2 B3
– – –
1 3 5
– – –
6
3.84 4.8 5.76
C
C1 C2
– –
– –
0.14 0.26
6
3.36 6.24
1938
M. Kang, I. Yun / Microelectronics Reliability 52 (2012) 1936–1939
Fig. 5. The density of trap states of each test structures. Fig. 3. Normalized Ssub variations versus stress time.
Fig. 6. The off currents of the test structures.
Fig. 4. Normalized lFEmax variations versus stress time.
3.4. Charge trap density (Ntrap) and off current (Ioff) We can see variations about the electrical characteristics, namely the Vth, Ssub variation, and lFEmax. Especially, Ssub is associated with the density of trap states at the semiconductor and insulator interface. From the relationship of Ssub and Ntrap is calculated by the following relation [8]:
Ntrap ¼
log e C ins Ssub 1 kT=q q
ð1Þ
Fig. 5 shows the variation of density of trap state through calculation for each test structures. Here, we measured 3 sample devices for each test structure to calculate the mean and the standard deviation for the verification of the statistical significance. Density of trap state is affected by the gate structural geometry. As shown before, the variation rate is dependent on the different structures. The test patterns used in this work have shown that the embossed structures (group B) have larger variations than the engraved structure (group A) even though they have the same effective channel length. That is because location and shape of the devices are affected on characteristic variations. Depending on the structure of the gate, especially folded or bent structure, the electric field is generated differently [9]. The electric field will be different for each test structures at the corner and patterned regions. Non-uniform electric field problem can affect the operating characteristics of the devices. In particular, the current flow and charge mobility can be affected significant by the electric field.
In addition, these results have shown that structural difference considering line edge roughness causes variations of the devices in the short channel [9]. As close to the gate edge, both the fixed oxide charge and interface state density are increased [7]. The embossed structures (group B) have thinner ends than engraved structures (group A). This can increase the trap density at the end of the gate and make different group B and group A. Therefore, the structural differences in the gate region due to the line edge roughness can affect the distribution of generated defects which impact the degradation of the device characteristics. In order to confirm the relationship between the trap density and the electrical characteristics, the off currents of the tested devices are also obtained from the measurement data. Here, the off current (Ioff) is defined as a current between source and drain when the gate voltage is fixed at 0.9 V and drain voltage is set to be zero. In addition, we also measured 3 sample devices for each test structure to calculate the mean and the standard deviation for the verification of the statistical significance. The off currents of different gate structures are shown in Fig. 6. The structural differences in the gate region due to the LER can affect the off currents [10]. As shown in Fig. 6, the shorter effective gate length device shows the higher increment of the off currents. Since the off current of the embossed structures (group B) is larger than that of the engraved structures (group A), the embossed structures (group B) have larger degradation of the electrical characteristics which is in good agreement with the previous results.
M. Kang, I. Yun / Microelectronics Reliability 52 (2012) 1936–1939
1939
4. Conclusion
References
In this paper, the multi-finger MOSFETs with different gate structures were used to investigate the degradation of the electrical characteristics when the gate bias stress is applied. From the experimental results, degradations of Vth, Ssub, and lFEmax were observed. In order to analyze the degradation effects, the charge trap density and the off current were examined to verify the degradation mechanism. Based on these results, it can be concluded that even though the structure have the same effective gate length, the structural differences in the gate region can affect the distribution of generated defects which resulted in different degradation characteristics when the gate voltage is applied at operating condition. This can allow us to provide the design guideline for the gate geometric structure of the multi-finger MOSFETs for electronic device applications.
[1] Leonardus H, Leunissen A, Jonckheere R, Ronse K, Derksen GB. Influence of gate patterning on line edge roughness. J Vac Sci Technol B 2003;21:3140–3. [2] Diaz CH, Hun-Jan T, Ching KY, Yen A, Young K. An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling. IEEE Electron Dev Lett 2001;22:287–9. [3] Conde AO, García Sánchez FJ, Liou JJ, Cerdeira A, Estrada M, Yue Y. A review of recent MOSFET threshold voltage extraction method. Microelectron Reliab 2002;42:583–96. [4] Grasser T, Gos W, Sverdlov V, Kaczer B. The universality of NBTI relaxation and its implications for modeling and characterization. Intl Reliab Phys Symp (IRPS) 2007;40:268–80. [5] Lai SK. Interface trap generation in silicon dioxide when electrons are captured by trapped holes. J Appl Phys 1983;54:2540–6. [6] Kouvatsos DN, Vamvakas VE, Davazoglou D. Electrical stressing induced degradation effects in solid phase crystallized polysilicon thin film transistors. Intl Conf Microelectron (MIEL) 2002;2:713–6. [7] Yamamoto T, Uwasawa K, Mogami T. Bias temperature instability in scaled p+ polysilicon gate p-MOSFET’s. IEEE Trans Electron Dev 1999;46:921–6. [8] Cross RBM, De Souza MM, Young ND. A comparison of the performance and stability of ZnO-TFTs with silicon dioxide and nitride as gate insulators. IEEE Trans Electron Dev 2008;55:1109–15. [9] Giraldo A, Paccagnella A, Minzoni A. Aspect ratio calculation in n-channel MOSFETs with a gate-enclosed layout. Solid-State Electron 2000;44:981–9. [10] Dong KS, Wada H, Woo JCS. TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling. IEEE Trans Semiconduct Manufact 2004;17:192–200.
Acknowledgement This work has been supported by the IC Design Education Center.
