Failure and reliability analysis of STT-MRAM - Semantic Scholar
Microelectronics Reliability 52 (2012) 1848–1852
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Failure and reliability analysis of STT-MRAM W.S. Zhao a,b,⇑, Y. Zhang a,b, T. Devolder a,b, J.O. Klein a,b, D. Ravelosona a,b, C. Chappert a,b, P. Mazoyer c a
IEF, Univ. Paris-Sud 11, Orsay 91405, France UMR8622, CNRS, Orsay 91405, France c STMicroelectronics, 850 Rue Jean Monnet Crolles, Grenoble 38026, France b
a r t i c l e
i n f o
Article history: Received 3 June 2012 Accepted 15 June 2012 Available online 6 July 2012
a b s t r a c t Spin Transfer Torque Magnetic RAM (STT-MRAM) promises low power, great miniaturization prospective (e.g. 22 nm) and easy integration with CMOS process. It becomes actually a strong non-volatile memory candidate for both embedded and standalone applications. However STT-MRAM suffers from important failure and reliability issues compared with the conventional solutions based on magnetic field switching. For example, a read current could write erroneously the stored data, the variability of ultra-thin oxide barrier drives high resistance variation and the injected current in the nanopillar induces lower lifetime etc. This paper classifies firstly all the possible failures of STT-MRAM into ‘‘soft errors’’ and ‘‘hard errors’’, and analyzes their impact on the memory reliability. Based on this work, we can find some efficient design solutions to address respectively these two types of errors and improve the reliability of STTMRAM. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Spin Transfer Torque Magnetic RAM (STT-MRAM) is regarded as a promising non-volatile memory candidate and it features fast speed, infinite endurance and great scalability (e.g. 22 nm) [1,2]. Only a bi-directional low current (
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Failure and reliability analysis of STT-MRAM W.S. Zhao a,b,⇑, Y. Zhang a,b, T. Devolder a,b, J.O. Klein a,b, D. Ravelosona a,b, C. Chappert a,b, P. Mazoyer c a
IEF, Univ. Paris-Sud 11, Orsay 91405, France UMR8622, CNRS, Orsay 91405, France c STMicroelectronics, 850 Rue Jean Monnet Crolles, Grenoble 38026, France b
a r t i c l e
i n f o
Article history: Received 3 June 2012 Accepted 15 June 2012 Available online 6 July 2012
a b s t r a c t Spin Transfer Torque Magnetic RAM (STT-MRAM) promises low power, great miniaturization prospective (e.g. 22 nm) and easy integration with CMOS process. It becomes actually a strong non-volatile memory candidate for both embedded and standalone applications. However STT-MRAM suffers from important failure and reliability issues compared with the conventional solutions based on magnetic field switching. For example, a read current could write erroneously the stored data, the variability of ultra-thin oxide barrier drives high resistance variation and the injected current in the nanopillar induces lower lifetime etc. This paper classifies firstly all the possible failures of STT-MRAM into ‘‘soft errors’’ and ‘‘hard errors’’, and analyzes their impact on the memory reliability. Based on this work, we can find some efficient design solutions to address respectively these two types of errors and improve the reliability of STTMRAM. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Spin Transfer Torque Magnetic RAM (STT-MRAM) is regarded as a promising non-volatile memory candidate and it features fast speed, infinite endurance and great scalability (e.g. 22 nm) [1,2]. Only a bi-directional low current (
