Fault Detection on Multicell Converter Based on Output Voltage ...
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 6, JUNE 2009
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Fault Detection on Multicell Converter Based on Output Voltage Frequency Analysis Pablo Lezana, Member, IEEE, Ricardo Aguilera, Student Member, IEEE, and José Rodríguez, Senior Member, IEEE
Abstract—Multilevel converters use a large amount of semiconductors, allowing the reconfigurate of the converter to work even on internal fault condition. This paper presents a method to detect faulty cells in a cascaded multicell converter requiring just one voltage measurement per output phase. The method is based on high-frequency harmonic analysis, using a dynamic prediction of their behavior, avoiding erroneous detection on transients while keeping the precision under real fault events. Once the faulty cell is detected, it can be bypassed allowing the converter to keep working according to previously reported techniques. Experimental results confirm accurate and fast fault detection, with a good rejection to normal operation transients. Index Terms—Digital control, fault diagnosis, multilevel systems, power electronics.
I. I NTRODUCTION
M
ULTILEVEL converters have emerged as an important technology in high-power applications [1], such as highpower ac motor drives [2]–[4], active filters [5], [6], and connection of renewable energy sources to the grid [7], [8]. Moreover, different topologies have been developed to generate a multilevel voltage, among them the most important, and in continuous development, are the following: neutral point clamped (NPC) [9]–[11], flying capacitor (FC) [12], [13], and cascaded H-bridge converters (MCs) [14]–[16]. The last two converters are built of cells which are interconnected and, for this reason, they are also called multicell converters. The multilevel converters allow one to reach high power levels using medium-voltage devices, improve the quality of output waveforms, and reduce detrimental effects, like common-mode voltage. However, the large amount of semiconductors required increases the probability of faults. Fortunately, these topologies allow one to reconfigure them to work even under internal fault condition [17]–[20]. Some special configurations based on this concept have been developed, in order to improve the reliability of this kind of converters [21]. However, to take advantage of this property, it is necessary to detect the faulty cell as soon as possible, to avoid permanent damage in the overall system.
Fig. 1. (a) Three-phase multicell cascade converter. (b) Cell based on H-bridge inverter.
Detection of faults in motors has been developed based on load voltage and current measurements for several years [22]–[24], the use of this kind of concepts has been presented in [19] and [25], where methods based on output current behavior is used to identify insulated gate bipolar transistor (IGBT) short circuits in an NPC converter, so the detection time depends on time constant of the load. For this reason, the detection can take some milliseconds, a long time for many semiconductors. A different approach is used in [18] and [26], where a frequency analysis of output phase voltage, at cell switching frequency, is used to identify the faulty cell (namely, a short circuit of a cell) of an FC converter. In this way, a fault can be detected in few sample times. This paper presents an adaptation of this technique to MC converters, while an improvement to fault detection algorithm is proposed by enhancing the threshold calculation that allows a better normal operation, transient rejection, and faster fault detection. Simulation and experimental results are provided to validate the proposed detection algorithm under different normal and faulty operation conditions. II. C ASCADE H-B RIDGE C ONVERTER
Manuscript received October 23, 2007; revised January 15, 2009. First published February 6, 2009; current version published June 3, 2009. This work was supported by the Chilean Research Fund (FONDECYT) through Grant 1060427. P. Lezana and J. Rodríguez are with the Departamento de Electricidad, Universidad Técnica Federico Santa María, 239-0123 Valparaíso, Chile (e-mail: [email protected]; [email protected]; [email protected]). R. Aguilera is with the School of Electrical Engineering and Computer Science, The University of Newcastle, Newcastle, NSW 2308, Australia (e-mail: [email protected]). Digital Object Identifier 10.1109/TIE.2009.2013845
As its name indicates, an MC is built of a group of cells connected in series [Fig. 1(a)], where the number of cells depends on the desired output voltage level. A. Topology Each cell is based on an isolated dc-link voltage source Vdc and four switching elements in an H-bridge connection, as shown in Fig. 1(b).
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TABLE I SWITCHING STATE AND OUTPUT VOLTAGES OF AN H-BRIDGE
This configuration can generate three voltage levels +Vdc , 0, −Vdc by connecting the dc-link voltage to the output by different combinations of the switches S1 , S 1 , S2 , and S 2 . Note that Sx and S x must work in a complementary way, otherwise the dc-link voltage will be short circuited. Table I summarizes the switch combinations and the output + − , negative leg vax , and the output voltage of positive leg vax voltage of the cell which correspond to + − vax = vax − vax .
(1)
As the cells on each output phase are connected in series, the total output voltage per phase is vyo =
n
vyx ,
y = a, b, c.
(2) obtaining
x=1
An additional switch ST is included between the two output terminals of the cell, it allows one to short circuit the cell if an internal fault is detected, guaranteeing the power flux to the load [17]. Moreover, the inclusion of this extra switch allows one to remove the faulty cell, without turning off the entire converter. B. Modulation Different modulations techniques have been developed to obtain a multilevel output voltage. Among the most popular modulation schemes space vector pulsewidth modulation (PWM), level-shifted PWM, and phase-shifted PWM (PSPWM) [28], [29] can be mentioned. This paper is focused on PSPWM because of its extensive use, ease of implementation, and spectrum characteristics, which will be used further in the detection algorithm. The modulation of each cell is generated by comparison between a voltage reference v ∗ and a triangular carrier, which + , has a frequency fcr . To obtain the output voltage for vax the carrier is compared with the voltage reference v ∗ , and, − is if unipolar modulation is used, the output voltage for vax obtained by comparing the carrier with the negative voltage reference −v ∗ , as shown in Fig. 2(a) and (b), respectively. The resulting PWM pattern has a fundamental switching frequency at fs = 2fcr = 1/T [Fig. 2(c)], so it can be synthesized using a triangular carrier with this frequency, and comparing it with Vdc − v ∗ , as shown in Fig. 2(d). In a cascade topology, the total output voltage vao is the instantaneous sum of all cell output voltages. To get the maximum number of voltage levels, the new carriers of frequency fs on the different cells are shifted in Δφ =
+ − Fig. 2. PWM modulator and output voltage for: (a) vax and (b) vax . (c) Total output voltage vax . (d) Equivalent PWM modulator.
2π n
(3)
ˆl = 2n + 1
(4)
voltage levels, with n the total number of cells in cascade per phase, and an effective switching frequency of nfs = 2nfcr . If the voltage reference has a sinusoidal waveform with frequency fo and amplitude mVdc , the fundamental of the output voltage can be expressed by vao (t) = m(nVdc ) sin(2πfo t)
(5)
where m = 0, . . . , 1 is the modulation index. III. F AULT D ETECTION B ASED ON F REQUENCY A NALYSIS OF O UTPUT V OLTAGE A multilevel converter can present many types of internal faults, among them are the switches fault. Each switch can have two type of faults, when it holds on closed-state or when it holds on open-state. The proposed fault detection method will be explained assuming a closed-state fault; however, as shown in Section III-B, under some assumptions, it also works with open-state faults, even when most of these faults can be avoided by using a proper gate circuit to control the gate current of the switch during the fault [30]. A. Working Principle In [18], a fault detection method based on frequency analysis for an FC converter is proposed. This method analyzes the magnitude of the switching frequency component vs of output phase voltage vao . Ideally, this component magnitude is zero, due to phase shift between PWM carriers. However, in practical implementations, the harmonic component at fs in vao is not identically zero due to the reference is sampled at T /n,
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LEZANA et al.: FAULT DETECTION ON MULTICELL CONVERTER
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Fig. 3. Effect on the cell references due to phase-shifted carriers. (a) Sampling of the reference. (b) Comparison between the references and the shifted carriers.
Fig. 5. Phasor representation of (thin line) cell output voltages vax and (wide line) output voltage vs . TABLE II OUTPUT VOLTAGES OF AN H-BRIDGE WHEN S1 IS IN FAULT
Fig. 4. Phasor representation. (a) In normal operation. (b) In fault condition on cell 1.
generating slightly different references for each cell, as shown in Fig. 3. These differences in magnitude (Δvx ) yield a small component at fs , which is always present, unless a constant reference is used, as is explained in Section III-C. The amplitude of vs must be considered as a threshold for proper fault detection. The analysis of switching component, in addition to fault detection, allows one to identify the faulty cell. This can be achieved through a phasor analysis of the switching harmonic. To do that, the output voltage of each cell at fs can be represented by a phasor of magnitude |vsx | and phase φx = (x − 1)Δφ
(6)
which corresponds to the carriers phase shift. Fig. 4 shows the phasor representation of an 11-level converter in normal and faulty condition. It can be seen that the magnitude of the resulting switching component vs defined by n jφx (7) |vsx |e |vs | =
increasing the magnitude of the switching component of the complete output phase, then 0
n
vsx = vs ≤ vsi ∠π.
(9)
x=1
The phase of vs , ∠vs ≈ π + ∠vsi , indicates the faulty cell. Note that only magnitude and angle of phasor vs are necessary. Therefore, faults on any cell of the converter output phase can be detected through measurements of total PWM voltage vao . The main difficulty of this strategy is to find a proper amplitude threshold for |vs | to detect a fault condition. A low threshold level can produce false detections, while a high threshold level introduces detection delays that may result in a permanent damage to the converter. The threshold level is determined, in steady-state, by the small differences in the references of each cell, as previously mentioned. However, in transient conditions, these differences are greatly increased producing a significant difference on the vsx phasors what is not due to a fault, but to normal transient operation. The detection algorithm must be able to discriminate between normal transients due to converter operation as reference changes (shown in Fig. 5), and actual fault occurrences.
x=1
is approximately zero in normal conditions, due to symmetry of the switching phasors of the cells n
vsx = vs ≈ 0.
(8)
x=1
However, if a cell i suffers an internal short circuit its output voltage vsi is reduced [as vsi 0 in Fig. 4(b)], significantly
B. Open-State Fault Detection If an open-circuit switch fault occurs, and an inductive load is fed by the inverter, an overvoltage will appear between the terminals of the faulty cell, unless the antiparallel diode of the respective switch keeps working. Only under this condition that the equipment can sustain its operation and Table II is valid. ∗ and the real Table II depicts the expected output voltage vax obtained voltage vax for a closed- and open-state fault in S1 .
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Note that the effect of an open-circuit fault in the output voltage depends on the output current sign. Moreover, if io is negative, the output voltage is not affected because the current flows normally through the diode (which is assumed nonfaulty), on the other side if io is positive, it tends to flow to the IGBT, as this is not possible the path is closed through the antiparallel diode of S2 , changing the applied output voltage. These mismatches affects the output voltage switching component in a similar way than the close-state faults; however, it must be notice that even under open-state fault switches, values (S1∗ , S2∗ ) = (0, 0) and (0, 1) does not affect the output voltage and, hence, does not allow one to detect a fault condition. C. Threshold Calculation The output voltage of each cell on a sample time T is given by 0, 0 < t < t1 vax (t) = Vdc , t1 < t < t2 (10) 0, t2 < t < T as defined in Fig. 2(d) and x = 1, . . . , n. The magnitude of component at fs for each cell, |vsx |, can be determined by Fourier analysis by T T vx∗ vx∗ t1 = t2 = (11) 1− 1+ 2 Vdc 2 Vdc 2 |vsx | = T
T vax (τ ) cos(2πfs τ )dτ 0
=
∗ 2Vdc v sin π x . π Vdc
(12)
As the reference for each cell is known at any time, using (12), the magnitude of the switching voltage, given by (7), can be calculated for each sample time from n ∗ 2Vdc vx ∗ jφx (13) sin π e . |vs | = π Vdc x=1
It can be seen that (13) is different to the theoretical magnitude of vs proposed in [18] ∗ v 2Vdc sin π x |vsf | = (14) π Vdc which actually corresponds to the switching component of the output voltage of a single cell as it was shown in (12), so the use of (13) as a threshold level is more accurate than (14) as is shown in the following section. The final threshold is obtained by addition of a small offset to overcome unmodeled effects as dead-time, dc-link unbalances among others, leading to the following expression: vth = |vs |∗ + kVdc .
(15)
Fig. 6. (a) Sampling at fm of the vs component of vao . (b) Fasorial rotation of vs due to the sampling at fm .
D. Implementation Issues To implement the fault detection strategy, it is necessary to measure the output voltage with a sampling frequency equal to fm = nfs , where n is the number of cells per output phase, so according to the Nyquist criteria, it can be digitally analyzed. The magnitude and angle φvs of vs are obtained using the Discrete Fourier Transform (DFT) algorithm evaluated just at interest frequency, in this case fs 2 vao (t − x/fm )ej2πx/n n x=0 Im(vs ) = arctan . Re(vs ) n−1
vs (t) =
(16)
φvs
(17)
A bandpass filter, centered at fs , is used before the DFT algorithm, in order to improve its resolution, by reducing the effect of other harmonics present in the voltage spectrum. As vs is a signal of frequency fs and is calculated at fm= nfs , it appears as a rotating phasor which advances n/2π rads on each sample time, as shown in Fig. 6. A state machine synchronized with the carrier of cell a1 is implemented to rotate the resulting vs phasor, obtaining its phase angle relative to this carrier. The signal processing scheme used to determine the threshold vth , and to actually detect a fault occurrence is shown in Fig. 7. The analog low-pass filter is mandatory to avoid aliasing in the voltage signal due to its high spectrum content. After sampling of the voltage, a digital bandpass is used for extraction of carrier component as explained before. This filter affects the phase and magnitude of sidebands around fs . This effect is difficult to compensate due to the variable frequency of these sidebands that are related with the fundamental of vao , which is, in essence, a variable quantity. To account for the effect of the bandpass filter, an identical one is applied to the expected value of the switching harmonic vs∗ obtained from (12) and (13) in the signal path of the voltage threshold calculation. This phenomenon is shown in Fig. 8, where the measurement of ∗ vs1 [Fig. 8(a)] is compared with the estimated value vs1 before and after the filter in the estimator path, Fig. 8(b) and (c), respectively. Once the phase has been corrected, the magnitude of vs∗ is calculated through DFT algorithm as well. Finally, the threshold value vth is obtained by addition of the dc offset as previously explained. The fault detection is achieved by comparison of measured |vs | and the threshold value vth . If |vs | > vth a fault is assumed and the angle φvs is calculated to determinate the faulty cell. Once the cell is found, it is bypassed using the corresponding switch STi .
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LEZANA et al.: FAULT DETECTION ON MULTICELL CONVERTER
Fig. 7.
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Block diagram of proposed fault detection system.
Fig. 8. Output voltage component at fs . (a) Measured from output voltage. (b) Estimated from (12). (c) After the bandpass filter centered at fs .
IV. R ESULTS The proposed detection algorithm was simulated and implemented in an 11-level MC prototype converter (five cells per output phase) shown in Fig. 9. Each cell was fed by a noncontrolled three-phase rectifier, a 3-mF dc-link capacitor operating at 50 V, an IGBT H-bridge based on discrete TO-247 packaged IRG4PC30KD IGBTs and a fast thyristor ST (Q6015L5) used for a fast short circuit of the output of the failed cells [31]. The control, modulation, and fault detection algorithm was developed in a digital platform based on a TMS320C6713 DSP and an XC2S150 FPGA. As a 2200-Hz carrier frequency was used, the effective switching frequency fs at the output of each cell was 4400 Hz; hence, the fault detection algorithm is evaluated every 45 μs (equivalent to 5 × 4400 Hz). The left column of Fig. 10 shows the behavior of the proposed threshold level according to (15), the threshold level proposed in [18] and the magnitude of the switching component fs of the output voltage va . It can be seen how |vs | is almost zero most of the time, except when a step in the modulation index from m = 0.6 to m = 0.95 occurs at t = 25 ms. At that time, a spike in |vs | can be seen, due to the effect of the carriers phase shift, as explained in Section III-A. This spike is correctly predicted by (15), and as this condition is not a fault, the threshold level increases its value following the spike
Fig. 9. Eleven-level MC prototype used for the experimental results.
waveform. On the other hand, the threshold level defined by (14), not only determines a comparison level higher than vth , which implies a higher fault detection time, but also induces a false fault detection in the transient operation. The waveforms for close-state faults are shown in the right column of Fig. 10. It can be seen how |vs | rapidly increases its value when the fault occurs at t = 60 ms, growing far beyond the proposed threshold level and, hence, detecting the fault condition. As the threshold level defined in (14) and the value of |vs | under fault have similar shapes, then the detection takes a larger time and it is not too accurate. The fault effects on the output voltage is clear, as two voltage levels are lost [Fig. 10(a)], so the output current decreases its magnitude, as shown in Fig. 10(b). The behavior of the fault detection algorithm for an openstate fault is shown in Fig. 11. Once again, the proposed method gets a faster detection. Moreover, from the magnitude of vs , it is possible to see how the fault cannot be detected if io is negative, and that the fault waveform had some common characteristics with the close-state fault but is not exactly the same, as explained in Section III-B. This can be seen in the output voltage waveform too, Fig. 11(a), which only lost one level in its positive half, then the output current shown in Fig. 11(b) is not symmetrical.
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Fig. 10. Simulated behavior of the previously reported threshold level (vsf ), and the proposed one (vth ) for a change in modulation index at t = 25 ms and a close-state fault at t = 60 ms. (a) Output voltage vao . (b) Output current ia . (c) Magnitude of vs in comparison with |vsf |. (d) Magnitude of vs in comparison with |vth |.
Fig. 11. Simulated behavior under open-state fault condition at t = 60 ms. (a) Output voltage vao . (b) Output current ia . (c) Magnitude of vs in comparison with |vsf |. (d) Magnitude of vs in comparison with |vth |.
The experimental results for a close-state fault, obtained with the prototype of Fig. 9, are shown in Fig. 12. From t = 0 to t = 25 ms a modulation index m = 0.6 is used, then the voltage reference is changed to m = 0.95, causing a transient on output current ioa . A fault condition is caused to the cell a4, at t = 60 ms, by keeping the switch S 1 permanently in ON-state, so a short circuit of its dc-link is caused when S1 commutes to ON . It can be seen how the output voltage loses two levels and the ripple in the output current increases its value. On the other hand, the current across S1 and S 1 rises over 80 A. The magnitude of switching frequency component from total output voltage |vs |, calculated from the measured values, is shown in Fig. 12(c), which has almost the same shape as the simulated waveforms of Fig. 10(d). Although all cells are similar, small differences in the input transformer and the tolerance on the dc-link capacitors affect the experimental magnitude of |vs |, increasing its noise. This value is compared with the estimated magnitude vth . As expected, during the transient due to magnitude step, vth rapidly increases its value; this behavior is correctly estimated by the detection algorithm, avoiding a false fault detection. On the other hand, when a fault occurs at t = 60 ms, both magnitudes are clearly different and the fault is detected correctly with a delay less of Δtd = 3Ts /5, allowing to bypass the faulty cell. The same maneuver is shown in Fig. 13 where the vectorial behavior of vs is shown. Here, vs appears as a rotating vector, whose magnitude change in time, while its angle can take only five values. Fig. 13(a) presents the whole operation behavior,
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Fig. 12. Experimental behavior in normal and fault operation. (a) Output voltage vao . (b) Output current ia . (c) Magnitude of vs and vth for change in modulation index at t = 25 ms and fault at t = 60 ms. (d) Current of failed IGBT.
Fig. 14. Front view of vectorial behavior of vs . (a) Simulated behavior. (b) Experimental behavior.
A frontal view of this behavior, around the fault instant, is shown in Fig. 14. It is possible to see clearly how the rotational vector vs adopt only five angular positions, whose angle φvs slightly moves around five positions, namely, 65◦ , 137◦ , 209◦ , 281◦ , and 353◦ , which are defined by the vectors vsx of each cell. It must be considered that accuracy of fault detection does not decrease for higher number of cells; however, the cell detector can present problems due to oscillations in φvs . Fig. 13. Vectorial behavior of vs . (a) Whole operation. (b) Change in modulation index. (c) Fault condition.
V. C ONCLUSION while Fig. 13(b) and (c) shows a zoom in modulation index change and fault condition, respectively. In both cases, it is possible to note that rotation of vector vs always generates a pentagon, due to five cells are used.
A method to detect faults on MC converters has been proposed. This method is based on an improved threshold level which is able to discriminate between normal transients, like frequency and/or amplitude changes, and real faults. Moreover,
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the algorithm allows one to identify the faulty cell, allowing for the use of corrective modulation algorithms to keep the operation in the load, and improving the reliability of this power multilevel inverter. The detection is not only accurate but also fast, because it is based on voltage switching frequency analysis, so the slow dynamics of the load are not involved. In addition, the method requires a reduced number of sensors (namely, three voltage measurements for the entire converter), reducing the complexity of the detection hardware. Although the apparent complexity of the proposed algorithm, it is possible to implement it in a standard digital signal processor, moreover, due to the constant evolution of the digital devices, in a near future, this kind of algorithms will be easier, faster, and cheaper to implement. R EFERENCES [1] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, “Multilevel voltage-source-converter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 2930–2945, Dec. 2007. [2] J. Rodríguez, J. Pontt, G. Alzamora, N. Becker, O. Einenkel, and A. Weinstein, “Novel 20 MW downhill conveyor system using three-level converters,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1093–1100, Oct. 2002. [3] L. Tolbert, F. Z. Peng, and T. Habetler, “Multilevel converters for large electric drives,” IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 36–44, Jan./Feb. 1999. [4] B. Wu, High-Power Converters and AC Drives. New York: Wiley-IEEE Press, 2006. [5] Y. Cheng, C. Qian, M. L. Crow, S. Pekarek, and S. Atcitty, “A comparison of diode-clamped and cascaded multilevel converters for a statcom with energy storage,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1512–1521, Oct. 2006. [6] Q. Song, W. Liu, and Z. Yuan, “Multilevel optimal modulation and dynamic control strategies for STATCOMs using cascaded multilevel inverters,” IEEE Trans. Power Del., vol. 22, no. 3, pp. 1937–1946, Jun. 2007. [7] S. Alepuz, S. Busquets-Monge, J. Bordonau, J. Gago, D. Gonzalez, and J. Balcells, “Interfacing renewable energy sources to the utility grid using a three-level inverter,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1504–1511, Oct. 2006. [8] R. I. A. Yazdani, “A neutral-point clamped converter system for directdrive variable-speed wind power unit,” IEEE Trans. Energy Convers., vol. 21, no. 2, pp. 596–607, Jun. 2006. [9] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523, Sep. 1981. [10] B. P. McGrath, D. G. Holmes, and T. Meynard, “Reduced PWM harmonic distortion for multilevel inverters operating over a wide modulation range,” IEEE Trans. Power Electron., vol. 21, no. 4, pp. 941–949, Jul. 2006. [11] A. Bendre, G. Venkataramanan, D. Rosene, and V. Srinivasan, “Modeling and design of a neutral-point voltage regulator for a three-level diodeclamped inverter using multiple-carrier modulation,” IEEE Trans. Ind. Electron., vol. 53, no. 3, pp. 718–726, Jun. 2006. [12] T. A. Meynard and H. Foch, “Multi-level choppers for high voltage applications,” J. Eur. Power Electron. Drives, vol. 2, no. 1, pp. 45–50, Mar. 1992. [13] B. P. McGrath, T. Meynard, G. Gateau, and D. G. Holmes, “Optimal modulation of flying capacitor and stacked multicell converters using a state machine decoder,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 508–516, Mar. 2007. [14] P. W. Hammond, “A new approach to enhance power quality for medium voltage drives,” IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 202–208, Jan./Feb. 1997. [15] J. Espinoza, M. Pérez, J. Rodríguez, and P. Lezana, “Regenerative medium-voltage AC drive based on a multi-cell arrangement with minimum energy storage requirements,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 171–180, Feb. 2005.
[16] C. Rech and J. R. Pinheiro, “Hybrid multilevel converters: Unified analysis and design considerations,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 1092–1104, Apr. 2007. [17] J. Rodriguez, P. Hammond, J. Pontt, R. Musalem, P. Lezana, and M. J. Escobar, “Operation of a medium-voltage drive under faulty conditions,” IEEE Trans. Ind. Electron., vol. 52, no. 4, pp. 1080–1085, Aug. 2005. [18] F. Richardeau, P. Baudesson, and T. A. Meynard, “Failures-tolerance and remedial strategies of a PWM multicell inverter,” IEEE Trans. Power Electron., vol. 17, no. 6, pp. 905–912, Nov. 2002. [19] H. Son, T. Kim, D. Kang, and D. Hyun, “Fault diagnosis and neutral point voltage control when the 3-level inverter faults occur,” in Proc. IEEE PESC, Aachen, Germany, Jun. 20–25, 2004, vol. 6, pp. 4558–4563. [20] S. Li and L. Xu, “Strategies of fault tolerant operation for three-level PWM inverters,” IEEE Trans. Power Electron., vol. 21, no. 4, pp. 933– 940, Jul. 2006. [21] A. Chen, L. Hu, L. Chen, Y. Deng, and X. He, “A multilevel converter topology with fault-tolerant ability,” IEEE Trans. Power Electron., vol. 20, no. 2, pp. 405–415, Mar. 2005. [22] S. Rajagopalan, T. G. Habetler, R. G. Harley, T. Sebastian, and B. Lequesne, “Current/voltage-based detection of faults in gears coupled to electric motors,” IEEE Trans. Ind. Appl., vol. 42, no. 6, pp. 1412–1420, Nov./Dec. 2006. [23] W. Zhao, M. Cheng, X. Zhu, W. Hua, and X. Kong, “Analysis of faulttolerant performance of a doubly salient permanent-magnet motor drive using transient cosimulation method,” IEEE Trans. Ind. Electron., vol. 55, no. 4, pp. 1739–1748, Apr. 2008. [24] M. A. S. K. Khan and M. A. Rahman, “Development and implementation of a novel fault diagnostic and protection technique for IPM motor drives,” IEEE Trans. Ind. Electron., vol. 56, no. 1, pp. 85–92, Jan. 2009. [25] F. Zidani, D. Diallo, M. El Hachemi Benbouzid, and R. Nait-Said, “A fuzzy-based approach for the diagnosis of fault modes in a voltage-fed PWM inverter induction motor drive,” IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 586–593, Feb. 2008. [26] C. Turpin, P. Baudesson, F. Richardeau, F. Forest, and T. Meynard, “Fault management of multicell converters,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 988–997, Oct. 2002. [27] N. Celanovic and D. Boroyevich, “A fast space-vector modulation algorithm for multilevel three-phase converters,” IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 637–641, Mar./Apr. 2001. [28] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, “A new multilevel PWM method: A theoretical analysis,” IEEE Trans. Power Electron., vol. 7, no. 3, pp. 497–505, Jul. 1992. [29] Y. Liang and C. O. Nwankpa, “A new type of STATCOM based on cascading voltage-source inverters with phase-shifted unipolar SPWM,” IEEE Trans. Ind. Appl., vol. 35, no. 5, pp. 1118–1123, Sep./Oct. 1999. [30] R. S. Chokhawala, J. Catt, and L. Kiraly, “A discussion on IGBT shortcircuit behavior and fault protection schemes,” IEEE Trans. Ind. Appl., vol. 31, no. 2, pp. 256–263, Mar./Apr. 1995. [31] C. Meyer and R. W. De Doncker, “Solid-state circuit breaker based on active thyristor topologies,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 450–458, Mar. 2006.
Pablo Lezana (S’06–M’07) was born in Temuco, Chile, in 1977. He received the M.Sc. and Doctor degrees in electronic engineering from the Universidad Técnica Federico Santa María (UTFSM), Valparaíso, Chile, in 2005 and 2006, respectively. From 2005 to 2006, he was a Research Assistant with the Departamento de Electrónica, UTFSM. Since 2007, he has been a Researcher with the Departamento de Electricidad, UTFSM. In 2007, he contributed to one chapter in the Power Electronics Handbook (Academic, 2007). His research interests include power converters and modern digital control devices (DSPs and fieldprogrammable gate arrays).
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LEZANA et al.: FAULT DETECTION ON MULTICELL CONVERTER
Ricardo Aguilera (S’02) received the Electrical Engineering degree from the Universidad de Antofagasta, Antofagsta, Chile, in 2002, and the M.Sc. degree in electronic engineering from the Universidad Técnica Federico Santa María (UTFSM), Valparaíso, Chile, in 2007. He is currently working toward the Ph.D. degree in the School of Electrical Engineering and Computer Science, The University of Newcastle, Newcastle, Australia. He was a Research Assistant with the UTFSM during 2007. His main research interests include power electronics, drives, and power quality.
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José Rodríguez (M’81–SM’94) received the Engineer degree from the Universidad Técnica Federico Santa María, Valparaíso, Chile, in 1977, and Dr.Ing. degree from the University of Erlangen, Erlangen, Germany, in 1985, both in electrical engineering. Since 1977, he has been a Professor with the Departamento de Electrónica, Universidad Técnica Federico Santa María. In 2005, he was elected Rector of the same university, a position he currently holds. During his sabbatical leave in 1996, he was responsible for the Mining Division of the Siemens Corporation in Chile. He has coauthored over 250 journal and conference papers, and contributed one book chapter. His main research interests include multilevel inverters, new converter topologies, and adjustable-speed drives.
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Fault Detection on Multicell Converter Based on Output Voltage Frequency Analysis Pablo Lezana, Member, IEEE, Ricardo Aguilera, Student Member, IEEE, and José Rodríguez, Senior Member, IEEE
Abstract—Multilevel converters use a large amount of semiconductors, allowing the reconfigurate of the converter to work even on internal fault condition. This paper presents a method to detect faulty cells in a cascaded multicell converter requiring just one voltage measurement per output phase. The method is based on high-frequency harmonic analysis, using a dynamic prediction of their behavior, avoiding erroneous detection on transients while keeping the precision under real fault events. Once the faulty cell is detected, it can be bypassed allowing the converter to keep working according to previously reported techniques. Experimental results confirm accurate and fast fault detection, with a good rejection to normal operation transients. Index Terms—Digital control, fault diagnosis, multilevel systems, power electronics.
I. I NTRODUCTION
M
ULTILEVEL converters have emerged as an important technology in high-power applications [1], such as highpower ac motor drives [2]–[4], active filters [5], [6], and connection of renewable energy sources to the grid [7], [8]. Moreover, different topologies have been developed to generate a multilevel voltage, among them the most important, and in continuous development, are the following: neutral point clamped (NPC) [9]–[11], flying capacitor (FC) [12], [13], and cascaded H-bridge converters (MCs) [14]–[16]. The last two converters are built of cells which are interconnected and, for this reason, they are also called multicell converters. The multilevel converters allow one to reach high power levels using medium-voltage devices, improve the quality of output waveforms, and reduce detrimental effects, like common-mode voltage. However, the large amount of semiconductors required increases the probability of faults. Fortunately, these topologies allow one to reconfigure them to work even under internal fault condition [17]–[20]. Some special configurations based on this concept have been developed, in order to improve the reliability of this kind of converters [21]. However, to take advantage of this property, it is necessary to detect the faulty cell as soon as possible, to avoid permanent damage in the overall system.
Fig. 1. (a) Three-phase multicell cascade converter. (b) Cell based on H-bridge inverter.
Detection of faults in motors has been developed based on load voltage and current measurements for several years [22]–[24], the use of this kind of concepts has been presented in [19] and [25], where methods based on output current behavior is used to identify insulated gate bipolar transistor (IGBT) short circuits in an NPC converter, so the detection time depends on time constant of the load. For this reason, the detection can take some milliseconds, a long time for many semiconductors. A different approach is used in [18] and [26], where a frequency analysis of output phase voltage, at cell switching frequency, is used to identify the faulty cell (namely, a short circuit of a cell) of an FC converter. In this way, a fault can be detected in few sample times. This paper presents an adaptation of this technique to MC converters, while an improvement to fault detection algorithm is proposed by enhancing the threshold calculation that allows a better normal operation, transient rejection, and faster fault detection. Simulation and experimental results are provided to validate the proposed detection algorithm under different normal and faulty operation conditions. II. C ASCADE H-B RIDGE C ONVERTER
Manuscript received October 23, 2007; revised January 15, 2009. First published February 6, 2009; current version published June 3, 2009. This work was supported by the Chilean Research Fund (FONDECYT) through Grant 1060427. P. Lezana and J. Rodríguez are with the Departamento de Electricidad, Universidad Técnica Federico Santa María, 239-0123 Valparaíso, Chile (e-mail: [email protected]; [email protected]; [email protected]). R. Aguilera is with the School of Electrical Engineering and Computer Science, The University of Newcastle, Newcastle, NSW 2308, Australia (e-mail: [email protected]). Digital Object Identifier 10.1109/TIE.2009.2013845
As its name indicates, an MC is built of a group of cells connected in series [Fig. 1(a)], where the number of cells depends on the desired output voltage level. A. Topology Each cell is based on an isolated dc-link voltage source Vdc and four switching elements in an H-bridge connection, as shown in Fig. 1(b).
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TABLE I SWITCHING STATE AND OUTPUT VOLTAGES OF AN H-BRIDGE
This configuration can generate three voltage levels +Vdc , 0, −Vdc by connecting the dc-link voltage to the output by different combinations of the switches S1 , S 1 , S2 , and S 2 . Note that Sx and S x must work in a complementary way, otherwise the dc-link voltage will be short circuited. Table I summarizes the switch combinations and the output + − , negative leg vax , and the output voltage of positive leg vax voltage of the cell which correspond to + − vax = vax − vax .
(1)
As the cells on each output phase are connected in series, the total output voltage per phase is vyo =
n
vyx ,
y = a, b, c.
(2) obtaining
x=1
An additional switch ST is included between the two output terminals of the cell, it allows one to short circuit the cell if an internal fault is detected, guaranteeing the power flux to the load [17]. Moreover, the inclusion of this extra switch allows one to remove the faulty cell, without turning off the entire converter. B. Modulation Different modulations techniques have been developed to obtain a multilevel output voltage. Among the most popular modulation schemes space vector pulsewidth modulation (PWM), level-shifted PWM, and phase-shifted PWM (PSPWM) [28], [29] can be mentioned. This paper is focused on PSPWM because of its extensive use, ease of implementation, and spectrum characteristics, which will be used further in the detection algorithm. The modulation of each cell is generated by comparison between a voltage reference v ∗ and a triangular carrier, which + , has a frequency fcr . To obtain the output voltage for vax the carrier is compared with the voltage reference v ∗ , and, − is if unipolar modulation is used, the output voltage for vax obtained by comparing the carrier with the negative voltage reference −v ∗ , as shown in Fig. 2(a) and (b), respectively. The resulting PWM pattern has a fundamental switching frequency at fs = 2fcr = 1/T [Fig. 2(c)], so it can be synthesized using a triangular carrier with this frequency, and comparing it with Vdc − v ∗ , as shown in Fig. 2(d). In a cascade topology, the total output voltage vao is the instantaneous sum of all cell output voltages. To get the maximum number of voltage levels, the new carriers of frequency fs on the different cells are shifted in Δφ =
+ − Fig. 2. PWM modulator and output voltage for: (a) vax and (b) vax . (c) Total output voltage vax . (d) Equivalent PWM modulator.
2π n
(3)
ˆl = 2n + 1
(4)
voltage levels, with n the total number of cells in cascade per phase, and an effective switching frequency of nfs = 2nfcr . If the voltage reference has a sinusoidal waveform with frequency fo and amplitude mVdc , the fundamental of the output voltage can be expressed by vao (t) = m(nVdc ) sin(2πfo t)
(5)
where m = 0, . . . , 1 is the modulation index. III. F AULT D ETECTION B ASED ON F REQUENCY A NALYSIS OF O UTPUT V OLTAGE A multilevel converter can present many types of internal faults, among them are the switches fault. Each switch can have two type of faults, when it holds on closed-state or when it holds on open-state. The proposed fault detection method will be explained assuming a closed-state fault; however, as shown in Section III-B, under some assumptions, it also works with open-state faults, even when most of these faults can be avoided by using a proper gate circuit to control the gate current of the switch during the fault [30]. A. Working Principle In [18], a fault detection method based on frequency analysis for an FC converter is proposed. This method analyzes the magnitude of the switching frequency component vs of output phase voltage vao . Ideally, this component magnitude is zero, due to phase shift between PWM carriers. However, in practical implementations, the harmonic component at fs in vao is not identically zero due to the reference is sampled at T /n,
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Fig. 3. Effect on the cell references due to phase-shifted carriers. (a) Sampling of the reference. (b) Comparison between the references and the shifted carriers.
Fig. 5. Phasor representation of (thin line) cell output voltages vax and (wide line) output voltage vs . TABLE II OUTPUT VOLTAGES OF AN H-BRIDGE WHEN S1 IS IN FAULT
Fig. 4. Phasor representation. (a) In normal operation. (b) In fault condition on cell 1.
generating slightly different references for each cell, as shown in Fig. 3. These differences in magnitude (Δvx ) yield a small component at fs , which is always present, unless a constant reference is used, as is explained in Section III-C. The amplitude of vs must be considered as a threshold for proper fault detection. The analysis of switching component, in addition to fault detection, allows one to identify the faulty cell. This can be achieved through a phasor analysis of the switching harmonic. To do that, the output voltage of each cell at fs can be represented by a phasor of magnitude |vsx | and phase φx = (x − 1)Δφ
(6)
which corresponds to the carriers phase shift. Fig. 4 shows the phasor representation of an 11-level converter in normal and faulty condition. It can be seen that the magnitude of the resulting switching component vs defined by n jφx (7) |vsx |e |vs | =
increasing the magnitude of the switching component of the complete output phase, then 0
n
vsx = vs ≤ vsi ∠π.
(9)
x=1
The phase of vs , ∠vs ≈ π + ∠vsi , indicates the faulty cell. Note that only magnitude and angle of phasor vs are necessary. Therefore, faults on any cell of the converter output phase can be detected through measurements of total PWM voltage vao . The main difficulty of this strategy is to find a proper amplitude threshold for |vs | to detect a fault condition. A low threshold level can produce false detections, while a high threshold level introduces detection delays that may result in a permanent damage to the converter. The threshold level is determined, in steady-state, by the small differences in the references of each cell, as previously mentioned. However, in transient conditions, these differences are greatly increased producing a significant difference on the vsx phasors what is not due to a fault, but to normal transient operation. The detection algorithm must be able to discriminate between normal transients due to converter operation as reference changes (shown in Fig. 5), and actual fault occurrences.
x=1
is approximately zero in normal conditions, due to symmetry of the switching phasors of the cells n
vsx = vs ≈ 0.
(8)
x=1
However, if a cell i suffers an internal short circuit its output voltage vsi is reduced [as vsi 0 in Fig. 4(b)], significantly
B. Open-State Fault Detection If an open-circuit switch fault occurs, and an inductive load is fed by the inverter, an overvoltage will appear between the terminals of the faulty cell, unless the antiparallel diode of the respective switch keeps working. Only under this condition that the equipment can sustain its operation and Table II is valid. ∗ and the real Table II depicts the expected output voltage vax obtained voltage vax for a closed- and open-state fault in S1 .
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Note that the effect of an open-circuit fault in the output voltage depends on the output current sign. Moreover, if io is negative, the output voltage is not affected because the current flows normally through the diode (which is assumed nonfaulty), on the other side if io is positive, it tends to flow to the IGBT, as this is not possible the path is closed through the antiparallel diode of S2 , changing the applied output voltage. These mismatches affects the output voltage switching component in a similar way than the close-state faults; however, it must be notice that even under open-state fault switches, values (S1∗ , S2∗ ) = (0, 0) and (0, 1) does not affect the output voltage and, hence, does not allow one to detect a fault condition. C. Threshold Calculation The output voltage of each cell on a sample time T is given by 0, 0 < t < t1 vax (t) = Vdc , t1 < t < t2 (10) 0, t2 < t < T as defined in Fig. 2(d) and x = 1, . . . , n. The magnitude of component at fs for each cell, |vsx |, can be determined by Fourier analysis by T T vx∗ vx∗ t1 = t2 = (11) 1− 1+ 2 Vdc 2 Vdc 2 |vsx | = T
T vax (τ ) cos(2πfs τ )dτ 0
=
∗ 2Vdc v sin π x . π Vdc
(12)
As the reference for each cell is known at any time, using (12), the magnitude of the switching voltage, given by (7), can be calculated for each sample time from n ∗ 2Vdc vx ∗ jφx (13) sin π e . |vs | = π Vdc x=1
It can be seen that (13) is different to the theoretical magnitude of vs proposed in [18] ∗ v 2Vdc sin π x |vsf | = (14) π Vdc which actually corresponds to the switching component of the output voltage of a single cell as it was shown in (12), so the use of (13) as a threshold level is more accurate than (14) as is shown in the following section. The final threshold is obtained by addition of a small offset to overcome unmodeled effects as dead-time, dc-link unbalances among others, leading to the following expression: vth = |vs |∗ + kVdc .
(15)
Fig. 6. (a) Sampling at fm of the vs component of vao . (b) Fasorial rotation of vs due to the sampling at fm .
D. Implementation Issues To implement the fault detection strategy, it is necessary to measure the output voltage with a sampling frequency equal to fm = nfs , where n is the number of cells per output phase, so according to the Nyquist criteria, it can be digitally analyzed. The magnitude and angle φvs of vs are obtained using the Discrete Fourier Transform (DFT) algorithm evaluated just at interest frequency, in this case fs 2 vao (t − x/fm )ej2πx/n n x=0 Im(vs ) = arctan . Re(vs ) n−1
vs (t) =
(16)
φvs
(17)
A bandpass filter, centered at fs , is used before the DFT algorithm, in order to improve its resolution, by reducing the effect of other harmonics present in the voltage spectrum. As vs is a signal of frequency fs and is calculated at fm= nfs , it appears as a rotating phasor which advances n/2π rads on each sample time, as shown in Fig. 6. A state machine synchronized with the carrier of cell a1 is implemented to rotate the resulting vs phasor, obtaining its phase angle relative to this carrier. The signal processing scheme used to determine the threshold vth , and to actually detect a fault occurrence is shown in Fig. 7. The analog low-pass filter is mandatory to avoid aliasing in the voltage signal due to its high spectrum content. After sampling of the voltage, a digital bandpass is used for extraction of carrier component as explained before. This filter affects the phase and magnitude of sidebands around fs . This effect is difficult to compensate due to the variable frequency of these sidebands that are related with the fundamental of vao , which is, in essence, a variable quantity. To account for the effect of the bandpass filter, an identical one is applied to the expected value of the switching harmonic vs∗ obtained from (12) and (13) in the signal path of the voltage threshold calculation. This phenomenon is shown in Fig. 8, where the measurement of ∗ vs1 [Fig. 8(a)] is compared with the estimated value vs1 before and after the filter in the estimator path, Fig. 8(b) and (c), respectively. Once the phase has been corrected, the magnitude of vs∗ is calculated through DFT algorithm as well. Finally, the threshold value vth is obtained by addition of the dc offset as previously explained. The fault detection is achieved by comparison of measured |vs | and the threshold value vth . If |vs | > vth a fault is assumed and the angle φvs is calculated to determinate the faulty cell. Once the cell is found, it is bypassed using the corresponding switch STi .
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LEZANA et al.: FAULT DETECTION ON MULTICELL CONVERTER
Fig. 7.
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Block diagram of proposed fault detection system.
Fig. 8. Output voltage component at fs . (a) Measured from output voltage. (b) Estimated from (12). (c) After the bandpass filter centered at fs .
IV. R ESULTS The proposed detection algorithm was simulated and implemented in an 11-level MC prototype converter (five cells per output phase) shown in Fig. 9. Each cell was fed by a noncontrolled three-phase rectifier, a 3-mF dc-link capacitor operating at 50 V, an IGBT H-bridge based on discrete TO-247 packaged IRG4PC30KD IGBTs and a fast thyristor ST (Q6015L5) used for a fast short circuit of the output of the failed cells [31]. The control, modulation, and fault detection algorithm was developed in a digital platform based on a TMS320C6713 DSP and an XC2S150 FPGA. As a 2200-Hz carrier frequency was used, the effective switching frequency fs at the output of each cell was 4400 Hz; hence, the fault detection algorithm is evaluated every 45 μs (equivalent to 5 × 4400 Hz). The left column of Fig. 10 shows the behavior of the proposed threshold level according to (15), the threshold level proposed in [18] and the magnitude of the switching component fs of the output voltage va . It can be seen how |vs | is almost zero most of the time, except when a step in the modulation index from m = 0.6 to m = 0.95 occurs at t = 25 ms. At that time, a spike in |vs | can be seen, due to the effect of the carriers phase shift, as explained in Section III-A. This spike is correctly predicted by (15), and as this condition is not a fault, the threshold level increases its value following the spike
Fig. 9. Eleven-level MC prototype used for the experimental results.
waveform. On the other hand, the threshold level defined by (14), not only determines a comparison level higher than vth , which implies a higher fault detection time, but also induces a false fault detection in the transient operation. The waveforms for close-state faults are shown in the right column of Fig. 10. It can be seen how |vs | rapidly increases its value when the fault occurs at t = 60 ms, growing far beyond the proposed threshold level and, hence, detecting the fault condition. As the threshold level defined in (14) and the value of |vs | under fault have similar shapes, then the detection takes a larger time and it is not too accurate. The fault effects on the output voltage is clear, as two voltage levels are lost [Fig. 10(a)], so the output current decreases its magnitude, as shown in Fig. 10(b). The behavior of the fault detection algorithm for an openstate fault is shown in Fig. 11. Once again, the proposed method gets a faster detection. Moreover, from the magnitude of vs , it is possible to see how the fault cannot be detected if io is negative, and that the fault waveform had some common characteristics with the close-state fault but is not exactly the same, as explained in Section III-B. This can be seen in the output voltage waveform too, Fig. 11(a), which only lost one level in its positive half, then the output current shown in Fig. 11(b) is not symmetrical.
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Fig. 10. Simulated behavior of the previously reported threshold level (vsf ), and the proposed one (vth ) for a change in modulation index at t = 25 ms and a close-state fault at t = 60 ms. (a) Output voltage vao . (b) Output current ia . (c) Magnitude of vs in comparison with |vsf |. (d) Magnitude of vs in comparison with |vth |.
Fig. 11. Simulated behavior under open-state fault condition at t = 60 ms. (a) Output voltage vao . (b) Output current ia . (c) Magnitude of vs in comparison with |vsf |. (d) Magnitude of vs in comparison with |vth |.
The experimental results for a close-state fault, obtained with the prototype of Fig. 9, are shown in Fig. 12. From t = 0 to t = 25 ms a modulation index m = 0.6 is used, then the voltage reference is changed to m = 0.95, causing a transient on output current ioa . A fault condition is caused to the cell a4, at t = 60 ms, by keeping the switch S 1 permanently in ON-state, so a short circuit of its dc-link is caused when S1 commutes to ON . It can be seen how the output voltage loses two levels and the ripple in the output current increases its value. On the other hand, the current across S1 and S 1 rises over 80 A. The magnitude of switching frequency component from total output voltage |vs |, calculated from the measured values, is shown in Fig. 12(c), which has almost the same shape as the simulated waveforms of Fig. 10(d). Although all cells are similar, small differences in the input transformer and the tolerance on the dc-link capacitors affect the experimental magnitude of |vs |, increasing its noise. This value is compared with the estimated magnitude vth . As expected, during the transient due to magnitude step, vth rapidly increases its value; this behavior is correctly estimated by the detection algorithm, avoiding a false fault detection. On the other hand, when a fault occurs at t = 60 ms, both magnitudes are clearly different and the fault is detected correctly with a delay less of Δtd = 3Ts /5, allowing to bypass the faulty cell. The same maneuver is shown in Fig. 13 where the vectorial behavior of vs is shown. Here, vs appears as a rotating vector, whose magnitude change in time, while its angle can take only five values. Fig. 13(a) presents the whole operation behavior,
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Fig. 12. Experimental behavior in normal and fault operation. (a) Output voltage vao . (b) Output current ia . (c) Magnitude of vs and vth for change in modulation index at t = 25 ms and fault at t = 60 ms. (d) Current of failed IGBT.
Fig. 14. Front view of vectorial behavior of vs . (a) Simulated behavior. (b) Experimental behavior.
A frontal view of this behavior, around the fault instant, is shown in Fig. 14. It is possible to see clearly how the rotational vector vs adopt only five angular positions, whose angle φvs slightly moves around five positions, namely, 65◦ , 137◦ , 209◦ , 281◦ , and 353◦ , which are defined by the vectors vsx of each cell. It must be considered that accuracy of fault detection does not decrease for higher number of cells; however, the cell detector can present problems due to oscillations in φvs . Fig. 13. Vectorial behavior of vs . (a) Whole operation. (b) Change in modulation index. (c) Fault condition.
V. C ONCLUSION while Fig. 13(b) and (c) shows a zoom in modulation index change and fault condition, respectively. In both cases, it is possible to note that rotation of vector vs always generates a pentagon, due to five cells are used.
A method to detect faults on MC converters has been proposed. This method is based on an improved threshold level which is able to discriminate between normal transients, like frequency and/or amplitude changes, and real faults. Moreover,
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 6, JUNE 2009
the algorithm allows one to identify the faulty cell, allowing for the use of corrective modulation algorithms to keep the operation in the load, and improving the reliability of this power multilevel inverter. The detection is not only accurate but also fast, because it is based on voltage switching frequency analysis, so the slow dynamics of the load are not involved. In addition, the method requires a reduced number of sensors (namely, three voltage measurements for the entire converter), reducing the complexity of the detection hardware. Although the apparent complexity of the proposed algorithm, it is possible to implement it in a standard digital signal processor, moreover, due to the constant evolution of the digital devices, in a near future, this kind of algorithms will be easier, faster, and cheaper to implement. R EFERENCES [1] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, “Multilevel voltage-source-converter topologies for industrial medium-voltage drives,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 2930–2945, Dec. 2007. [2] J. Rodríguez, J. Pontt, G. Alzamora, N. Becker, O. Einenkel, and A. Weinstein, “Novel 20 MW downhill conveyor system using three-level converters,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 1093–1100, Oct. 2002. [3] L. Tolbert, F. Z. Peng, and T. Habetler, “Multilevel converters for large electric drives,” IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 36–44, Jan./Feb. 1999. [4] B. Wu, High-Power Converters and AC Drives. New York: Wiley-IEEE Press, 2006. [5] Y. Cheng, C. Qian, M. L. Crow, S. Pekarek, and S. Atcitty, “A comparison of diode-clamped and cascaded multilevel converters for a statcom with energy storage,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1512–1521, Oct. 2006. [6] Q. Song, W. Liu, and Z. Yuan, “Multilevel optimal modulation and dynamic control strategies for STATCOMs using cascaded multilevel inverters,” IEEE Trans. Power Del., vol. 22, no. 3, pp. 1937–1946, Jun. 2007. [7] S. Alepuz, S. Busquets-Monge, J. Bordonau, J. Gago, D. Gonzalez, and J. Balcells, “Interfacing renewable energy sources to the utility grid using a three-level inverter,” IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1504–1511, Oct. 2006. [8] R. I. A. Yazdani, “A neutral-point clamped converter system for directdrive variable-speed wind power unit,” IEEE Trans. Energy Convers., vol. 21, no. 2, pp. 596–607, Jun. 2006. [9] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point-clamped PWM inverter,” IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518–523, Sep. 1981. [10] B. P. McGrath, D. G. Holmes, and T. Meynard, “Reduced PWM harmonic distortion for multilevel inverters operating over a wide modulation range,” IEEE Trans. Power Electron., vol. 21, no. 4, pp. 941–949, Jul. 2006. [11] A. Bendre, G. Venkataramanan, D. Rosene, and V. Srinivasan, “Modeling and design of a neutral-point voltage regulator for a three-level diodeclamped inverter using multiple-carrier modulation,” IEEE Trans. Ind. Electron., vol. 53, no. 3, pp. 718–726, Jun. 2006. [12] T. A. Meynard and H. Foch, “Multi-level choppers for high voltage applications,” J. Eur. Power Electron. Drives, vol. 2, no. 1, pp. 45–50, Mar. 1992. [13] B. P. McGrath, T. Meynard, G. Gateau, and D. G. Holmes, “Optimal modulation of flying capacitor and stacked multicell converters using a state machine decoder,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 508–516, Mar. 2007. [14] P. W. Hammond, “A new approach to enhance power quality for medium voltage drives,” IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 202–208, Jan./Feb. 1997. [15] J. Espinoza, M. Pérez, J. Rodríguez, and P. Lezana, “Regenerative medium-voltage AC drive based on a multi-cell arrangement with minimum energy storage requirements,” IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 171–180, Feb. 2005.
[16] C. Rech and J. R. Pinheiro, “Hybrid multilevel converters: Unified analysis and design considerations,” IEEE Trans. Ind. Electron., vol. 54, no. 2, pp. 1092–1104, Apr. 2007. [17] J. Rodriguez, P. Hammond, J. Pontt, R. Musalem, P. Lezana, and M. J. Escobar, “Operation of a medium-voltage drive under faulty conditions,” IEEE Trans. Ind. Electron., vol. 52, no. 4, pp. 1080–1085, Aug. 2005. [18] F. Richardeau, P. Baudesson, and T. A. Meynard, “Failures-tolerance and remedial strategies of a PWM multicell inverter,” IEEE Trans. Power Electron., vol. 17, no. 6, pp. 905–912, Nov. 2002. [19] H. Son, T. Kim, D. Kang, and D. Hyun, “Fault diagnosis and neutral point voltage control when the 3-level inverter faults occur,” in Proc. IEEE PESC, Aachen, Germany, Jun. 20–25, 2004, vol. 6, pp. 4558–4563. [20] S. Li and L. Xu, “Strategies of fault tolerant operation for three-level PWM inverters,” IEEE Trans. Power Electron., vol. 21, no. 4, pp. 933– 940, Jul. 2006. [21] A. Chen, L. Hu, L. Chen, Y. Deng, and X. He, “A multilevel converter topology with fault-tolerant ability,” IEEE Trans. Power Electron., vol. 20, no. 2, pp. 405–415, Mar. 2005. [22] S. Rajagopalan, T. G. Habetler, R. G. Harley, T. Sebastian, and B. Lequesne, “Current/voltage-based detection of faults in gears coupled to electric motors,” IEEE Trans. Ind. Appl., vol. 42, no. 6, pp. 1412–1420, Nov./Dec. 2006. [23] W. Zhao, M. Cheng, X. Zhu, W. Hua, and X. Kong, “Analysis of faulttolerant performance of a doubly salient permanent-magnet motor drive using transient cosimulation method,” IEEE Trans. Ind. Electron., vol. 55, no. 4, pp. 1739–1748, Apr. 2008. [24] M. A. S. K. Khan and M. A. Rahman, “Development and implementation of a novel fault diagnostic and protection technique for IPM motor drives,” IEEE Trans. Ind. Electron., vol. 56, no. 1, pp. 85–92, Jan. 2009. [25] F. Zidani, D. Diallo, M. El Hachemi Benbouzid, and R. Nait-Said, “A fuzzy-based approach for the diagnosis of fault modes in a voltage-fed PWM inverter induction motor drive,” IEEE Trans. Ind. Electron., vol. 55, no. 2, pp. 586–593, Feb. 2008. [26] C. Turpin, P. Baudesson, F. Richardeau, F. Forest, and T. Meynard, “Fault management of multicell converters,” IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 988–997, Oct. 2002. [27] N. Celanovic and D. Boroyevich, “A fast space-vector modulation algorithm for multilevel three-phase converters,” IEEE Trans. Ind. Appl., vol. 37, no. 2, pp. 637–641, Mar./Apr. 2001. [28] G. Carrara, S. Gardella, M. Marchesoni, R. Salutari, and G. Sciutto, “A new multilevel PWM method: A theoretical analysis,” IEEE Trans. Power Electron., vol. 7, no. 3, pp. 497–505, Jul. 1992. [29] Y. Liang and C. O. Nwankpa, “A new type of STATCOM based on cascading voltage-source inverters with phase-shifted unipolar SPWM,” IEEE Trans. Ind. Appl., vol. 35, no. 5, pp. 1118–1123, Sep./Oct. 1999. [30] R. S. Chokhawala, J. Catt, and L. Kiraly, “A discussion on IGBT shortcircuit behavior and fault protection schemes,” IEEE Trans. Ind. Appl., vol. 31, no. 2, pp. 256–263, Mar./Apr. 1995. [31] C. Meyer and R. W. De Doncker, “Solid-state circuit breaker based on active thyristor topologies,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 450–458, Mar. 2006.
Pablo Lezana (S’06–M’07) was born in Temuco, Chile, in 1977. He received the M.Sc. and Doctor degrees in electronic engineering from the Universidad Técnica Federico Santa María (UTFSM), Valparaíso, Chile, in 2005 and 2006, respectively. From 2005 to 2006, he was a Research Assistant with the Departamento de Electrónica, UTFSM. Since 2007, he has been a Researcher with the Departamento de Electricidad, UTFSM. In 2007, he contributed to one chapter in the Power Electronics Handbook (Academic, 2007). His research interests include power converters and modern digital control devices (DSPs and fieldprogrammable gate arrays).
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LEZANA et al.: FAULT DETECTION ON MULTICELL CONVERTER
Ricardo Aguilera (S’02) received the Electrical Engineering degree from the Universidad de Antofagasta, Antofagsta, Chile, in 2002, and the M.Sc. degree in electronic engineering from the Universidad Técnica Federico Santa María (UTFSM), Valparaíso, Chile, in 2007. He is currently working toward the Ph.D. degree in the School of Electrical Engineering and Computer Science, The University of Newcastle, Newcastle, Australia. He was a Research Assistant with the UTFSM during 2007. His main research interests include power electronics, drives, and power quality.
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José Rodríguez (M’81–SM’94) received the Engineer degree from the Universidad Técnica Federico Santa María, Valparaíso, Chile, in 1977, and Dr.Ing. degree from the University of Erlangen, Erlangen, Germany, in 1985, both in electrical engineering. Since 1977, he has been a Professor with the Departamento de Electrónica, Universidad Técnica Federico Santa María. In 2005, he was elected Rector of the same university, a position he currently holds. During his sabbatical leave in 1996, he was responsible for the Mining Division of the Siemens Corporation in Chile. He has coauthored over 250 journal and conference papers, and contributed one book chapter. His main research interests include multilevel inverters, new converter topologies, and adjustable-speed drives.
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