Flash analog-to-digital converter using resonant-tunneling multiple ...
Flash Analog-to-Digital Converter Using Resonant-Tunneling Multiple-valued Circuits Takao Waho, Kazufumi Hattori, and Yuuji Takamatsu Department of Electrical and Electronics Engineering Sophia University 7-1 Kioicho, Chiyoda-ku, Tokyo 102-8554, Japan waho @sscd.ee.sophia.ac.jp
(MML) circuits using RTDs [6] [7], and applied them to such ultrahigh-speed ADCs. The negative differential resistance of RTDs reduces the circuit complexity. RTD-based flash ADCs with sampling frequencies more than 5 GHz have been demonstrated by simulations and experiments [8] [9]. ADCs mentioned above, however, used RTDs only to quantize the input signal. For encoding from the quantizer output to the binary code, we used conventional source-coupled FET logic (SCFL) circuits, which required a relatively large number of transistors and consumed a considerable amount of power. In this paper, we propose an ADC that employs RTD-based complex gates not only as quantizers but also as encoder circuits. To convert multiple-valued thermometer code, the output of the quantizer, into the binary Gray code, we develop a new scheme consisting of temary-signal subtraction. This is obtained by combining the MML quantizer with another RTD-based circuit, or a monostable-to-bistable transition logic element (MOBILE) [lo]. In particular, we have developed a new operation mode of the MOBILE gate, i. e., the multiple-valued multiple-input mode. We call gate M2-MOBILE. Consisting of MML and M2-MOBILE, the complex gate is proved to be suitable to obtain a compact flash ADC. The structure of this paper is as follows. First, we explain the background and basic idea behind the new encoding scheme. Next, circuit configuration and operation principle of M2-MOBILE are presented. Then, a 4-bit ADC using the complex gates is described. Finally, SPICE simulation results that show a possible 4-bit 5-GS/s flash ADC with a reduced device count and power dissipation are presented.
Abstract We have proposed a flash analog-to-digital converter (ADC) that uses resonant-tunneling complex gates not only as ternary quantizers but also as ternary-to-binary encoder circuits. The ternary quantizers, consisting of monostable-to-multistable transition logic (MML) circuits, convert the analog input signal into the ternary thermometer code. This code is then converted into the binary Gray-code output by a multiple-valued, multiple-input monostable-to-bistable transition logic element (M2-MOBILE). By assuming InP-based resonant-tunneling diodes and heterojunction field-effect transistors, we have carried out SPICE simulation that demonstrates ultrahigh-speed ADC operation at a clock frequency of 5 GHz. Compact circuit conjiguration, which is due to the combination of MML and M2-MOBILE, reduces the device count and power dissipation by a factor of two compared with previous RTD-based ADCs.
1. Introduction Analog-to-digital converters (ADCs) with sampling frequencies over a few GHz have been required in the field of ultrahigh-speed instrumentation. Recently, they are also expected to play a crucial role in future wireless communications, particularly in realizing next-generation software-defined radio with a digital RFAF architecture [ 11. There have been several attempts to fabricate ultrahigh-speed ADCs by using SiGe [2] or InP [3] heterojunction bipolar transistors. As an altemative approach, we have proposed the use of InP-based resonant-tunneling diodes (RTDs) [4], which are known as the fastest semiconductor devices among others [5]. We have developed monostable-to-multistable transition logic
2. Background and basic idea The ADC operation
94
0-7695-1083-3/01 $10.00 0 2001 IEEE
comprises quantization
and
encoding. In this section, we explain the basic idea behind the new scheme for encoding, that is, how to convert the multiple-valued output of MML quantizers into the binary Gray-code output. The fastest analog-to-digital converter is the flash ADC. The number of comparators in flash ADCs, however, increases exponentially (2”-1) as the bit resolution n Increases. This means that the chip area and power dissipation also increase exponentially. To solve this problem, we previously proposed to introduce multiple-valued circuits between the analog input and the binary output, which makes a flash ADC quite compact [4]. Figure 1 shows such an ADC with ternary quantizers followed by a ternary-to-binary encoder. MSB stands for the most significant bit, while LSB is the least significant bit. Figure 2 shows typical transfer characteristics of an ADC, the output of which is called the Gray code, where “0” and “1” repeat periodically as the analog input increases. Although we were able to reduce the number of comparators, the encoder circuit remained unchanged and dissipated more power than comparators in the previous ADC design [4]. This IS because conventional source-coupled FET logic (SCFL) circuits were used in the encoder. Therefore, a challenge is to reduce encoder circuit
Ternaryto-Binary Encoder
Ternary Quantizer
MSB MSB-1
-
Figure 1. Flash ADC with ternary quantizers
Analog Input
Figure 2. Quantization and encoding
I
complexrtty.
The encodmg scheme we previously usedl is shown in Fig. 3. This is €OF the MS-B-2bit in Fig. 2’. First, two 2-1-0 ternary input signals are obtained by two temay quanheers. They are then converted into two binary 0-1-0 si finally by tahng “OR” of these signals we obtaln the 0- I-@-1-0)MSB-2 QLLQXI~To do this, we used conventional SCFL threshold detectors with the wired-OR function, which made the circuit configuration rather complicated Figure 4 shows the new encoding scheme we have proposed in this paper. We subtract one ternary signal from the other to obtain the 0-1-0-1-0 MSB-2 output at one time. We are able to do this by a complex gate, which consists of MML ternary quantizers and an M2-MOBILE gate.
L
OR Operation
Ternaly-to-Binary Conversion
Figure 3. Conventional encoder
-5
%
_ni-L
l--LG Subtraction
Figure 4. Present encoder
3. Multiple-valued multiple-input MOBILE gate (M~-MOBILE)
“CLK
?
We will explain the circuit configuration of M2-MOBILE and its operation used for implementing the new encoding scheme shown in Fig. 4.
* Figure 5. M2-MOBILEgate
95
To obtain the subtraction of two ternary signals, we used the MOBLE gate consisting of two RTDs- connected in series and two heterojunction field-effect-transistors (HFETs), as shown in Fig. 5(a). Two ternary input, x I and x2, are fed from two MML ternary quantizers, whose threshold voltages are (Val,Va2)and ( v b l , vb2). When the analog input voltage to the quantizers, xi,, is xi, 5 Val,Val < x,, 5 V,,, or Va2< xi,, the ternary signal to M I , x I , is "2", "l", or "O",respectively, as shown in Fig. 6. Similarly, x, is "2", "l", or "0," when xi, is xi, 2 vb1, vb1 < xi, 5 v b z , or vb2 < xi,,, respectively. The differences between Val and v b l and between Va2 and v b 2 can be controlled by the method described in the next section. These threshold voltages are designed so that they occur alternatively. In other words, v b l < Val < v b , < Va2.As described below, the gate operates as a subtracter, and the output, x I - x2, is "high" when vb1 < xi, 2 Val or vb, < xi, 5 va2, and it is "low" otherwise. Since this MOBILE gate operates in the multiple-valued multiple-input mode, we call it M2-MOBILE. Now the operation principle of M*-MOBILE is described. The basic idea of the gate operation is the same as the usual MOBILE and MML logic. When two RTDs are connected in series and the applied voltage across the terminals VcLKincreases, the RTD having a smaller peak current switches earlier than the other. During the switch, the RTD state changes from the peak-current branch of lower resistance to the valley-current branch of higher resistance. If the pulse height of the clock signal, VCLK,is designed such that only one RTD switches when VcLKis high, then the output is "high" when the RTD "b" switches, and it is "low" when the RTD "a" switches. For the circuit shown in Fig. 5, if the RTD current mentioned above is replaced with the sum of the RTD current and the HFET drain current, the same criteria holds in determining which RTD switches, or whether the output is "high" or "low." The operation will be explained in detail by using Fig, 7. Two planes denoted as "a + M," and "b + M2" show the sum of RTD and HFET currents, and the cross -section corresponds to the border between the high and low outputs. For example, if x I = " 1 " and x2= "0", the peak current of "b + M2" is smaller than that of "a + M,," and RTD "b" switches when VcLKis high. This results in the "high" output, which corresponds to the subtraction: x I - x2= "1" - "0" = " 1" . The subtraction for two ternary variables explained above can be extended to that for four variables. This is obtained by adding two HFETs, as described in Fig. 8. In this case, the thresholds are determined such that VbI < Val < v d l < v,, < vb2 < va,< v d 2 < This is designed by setting the controlled voltages in the quantizers, which will be mentioned in the next section. By considering Kirchhoffs current law, we can analyze the transfer characteristics of the gate by substituting a + M I and b + M2
X I -x2
A
" 'bl
XIN
"b2
Figure 6. Transfer characteristics (a)
(b)
Figure 7. M2-MOBILEOperation
pv,,
1-
1i1 1I111H1
v,, C X I N < Val 12 11 12 12 v,, < X I N < v,, 1 1 2 2 v,, t x , < v,, 1 1 2 1 v,, cx,< v,
1 1 1 1
.
0 1 1 0 0 1 1
V b 2 4 X I N s V s1 Z
v,
v@cx/N5
v,~.
Figure 8. Extended M2-MOBILE
96
in Fig. 7 with a + M, + M3 and b + M2 + M4, respectively. Thus the output is high when V,, < x,, < V,, or V,, < x,, < V,,, and it is ‘‘low’’ otherwise, where i = 1, 2. In this way, we can obtain RTD-based compact encoding circuits, the output of which consists of the 0-1-0-1-... signal.
(a)
(b)
I
MSB
......................... C
4.4-bit ADC with MML/M2-MOBILE gates Now we will explain a 4-bit flash ADC using MML/M2-MOBILE complex gates. The output waveforms for the 4-bit ADC, MSB, MSB-I, LSB+I, and LSB, are shown in Fig. 9. M2-MOBILE is applied to LSB and LSB+I, while a modified one is used for MSB-1, which will be described shortly. We used a simple inverter for MSB. Figure 10(a) shows an MML ternary quantizer that has an additional HFET with the control voltage V, to vary threshold voltages. As shown in Fig. lO(b), two threshold voltages, V , and V,, decreases as V, increases, because of the linear summation of the drain current flowing into the two HFETs. We represent this quantizer with a symbol shown in Fig. lO(c). For LSB+1, an MML/M2-MOBILE gate shown in Fig. 11 was used. Two buffers were emitter followers consisting of HFETs, and were used as level shifters. The control voltage V‘, was smaller than V t so that the two threshold voltages in “c” were larger than the corresponding ones in “d”. This should results in the output waveform as expected for the LSB+l . For LSB, we used an MML/M2-MOBILE complex gate as shown in Fig. 12. This consists of four MML ternary quantizers shown in Fig. 10 followed by buffers and an M2-MOBILE subtraction gate shown in Fig. 8. Four controlling voltages were designed such that V: < V,h < V,‘ < V!. TO obtain the output waveforms shown in Fig. 9, these voltages also satisfied the following conditions: V: < V,“ < V,h, and V‘, < V p < V!.
(e - d
+ (g - h)
b xIN
xIN
Figure 9. Threshold design for 4-bit ADC
Figure 10. MML ternary quantizer with variable thresholds I
Figure 11. LSB+l
v,h
Figure 12. LSB Figure 13. MSB-1
97
VCLK
-5
For MSB-1, we used the complex gate similar to that for LSB+l, as shown in Fig. 13. To obtain the output waveforms shown in Fig. 9, the control voltage V t was designed to satisfy the following condition: V,h < V t < V t . It should be noted that we obtained “2 - 1 - 0” for the node A and “1 - 0 - 0” for the node B. We arranged the gate widths of HFETs, as shown in Fig. 13. By this arrangement, we were able to amplify the “1” signal at B to be comparable to the “2” signal at A, and obtained the “low high - low” output waveform for MSB-1 by the subtraction.
0.4
Q)
2 0.2 - 0 2 c
c 0
g -0.2 L
c I- -0.4
-0.3 -0.2 -0.1
0 0.1 Control Voltage, Vc (V)
Figure 14. Threshold control
5. Simulation results
(a)
...........................................................
Now SPICE simulation results will be described for the present 4-bit flash ADC. We assumed InP-based RTD and 0.15-pm HFET technology [8]. The peak current density of the RTD was 2 x IO5 A/cm2 and the peak-to-valley current ratio was 10. The HFET unity-current-gain cutoff frequency fr and the maximum oscillation frequencyfMM are 120 GHz and 200 GHz, respectively. Figure 14 shows threshold voltages of the MML temary quantizer shown in Fig. 10 as a function of the control voltage. As explained in the previous chapter, the threshold voltages decrease as the control voltage increases. This figure shows we can actually design 15 threshold voltages that are necessary to obtain 4-bit resolution. In the present circuit, both MML quantizers and M2-MOBILE subtraction circuits need clocked supply voltages. In this simulation the clock for the quantizer, I$,, increased with the rise time of 100 ps, as shown in Fig. 15(a). The quantizer output started increasing immediately after the clock rose, and the three levels evolved depending on the input voltage (Fig. 15(b)). After the clock for the quantizer was settled, that for the M2-MOBILE, q2, started increasing with the same rise time. The M2-MOBILE output increased and eventually resulted in one of the two levels as reached the stable state. Total time for conversion was 200 ps. Therefore, we can operate this ADC at a frequency of 5 GHz. It should be noted that we can use @, and @* as the two-phase clock in a pipeline structure. Then we might obtain sampling frequencies as high as 10 GHz. Figure 16 shows simulated transfer characteristics for LSB+l. Plotted values were sampled at 20 ps after the clocks stopped rising. Note that the quantizer outputs shown in Fig. 16(a) agree well with c and d in Fig. 9(a). Furthermore, the output shown in Fig. 16(b) corresponds to c-d in Fig. 9(b). Figure 17 shows the output waveforms for LSB. The quantizer outputs shown in Fig. 17(a) agree well with e, f, g, and h in Fig. 9(a), while the output waveform in Fig. 17(b) is compared to (e - 0 + (g - h) in Fig. 9(b). All these plots show that the present ADC operates successfully.
............................. 0
50
100
200
150
250
Quantizer
LSB + 1
..............
I
0
50
100
150
200
250
Time [ps] Figure 15. MMUM2-MOBILEcomplex gate (Simulation) (a)
0.6
0 0 -0.6 -0.4
-0.2
0
0.2
0.4
-0.4
-0.2
0
0.2
0.4
Input Voltage [VI
Figure 16. LSB+I (simulation) (a)
0.6
WE o :2 5 2 -0.6 L -
._ c
-0.4
-0.2
0.2
0.4
4.4
4.2 0 0.2 Input Voltage [VI
0.4
0
Figure 17. LSB (simulation)
98
6.‘Discussion Table 1 compares device counts in present ADC with those in a previous one. Although the numbers for the quantizers are the same, those for the encoder are much reduced by introducing RTDs into the encoder circuits. This reduces the number of current path from 36 to 25. Our preliminary study on power dissipation reveals that it has been reduced by a factor of two compared with the previous RTD-based ADC. This is mainly attributed to the reduction in the number of SCFL current paths from 28 to 13, where the static power dissipation dominates. Estimated power dissipation for the present 4-bit ADC was 0.3 W, which is considerably lower than 0.5 W obtained by using SiGe bipolar technology [2].
input signal into the binary Gray-code output, where “high” and “low” levels are repeated periodically. Using InP-based device models, we carried out SPICE simulation that demonstrated a possible 4-bit flash ADC with an operation frequency more than 5 GHz. The device counts and power dissipation were reduced by a factor of two as compared to RTD-based ADCs demonstrated previously.
Table 1. Device Counts (4-bit ADCs)
I
I
Encoder
7. Conclusion
Total
We proposed an ultrahigh-speed ADC that uses the RTD-based MML and M2-MOBILE complex gate. By subtracting ternary signals, the gate converts the analog
Present
I Conventional I
I Quantizer 1 30RTDs I I 24 HFETs I
I
Current Path
I
8RTDs 17 HFETs 38 RTDs I 4 1 HFETs 12 (RTD) 13(HFET)
1
I
30 24
I
0
1 1 1
53 30 77 8 28
I
I
References multiple-valued logic circuits,” Proc. 25th Int. Symp. Multiple-Valued Logic, pp. 130 - 138, 1995. [7] T. Waho, K. J. Chen and M. Yamamoto, “Resonant-Tunneling Diode and HEMT Logic Circuits with Multiple Thresholds and Multi-Level Output,” IEEE J. Solid-state Circuits, Vol. 33, No. 2, pp. 268 - 274, February 1998. [SI T. Waho, T. Itoh, K. Maezawa, and M. Yamamoto, “Multi-GHz AID converter using resonant-tunneling multiple-valued logic circuits,” ISSCC Digest of Technical Papers, pp. 258 - 259, February 1998. 191 T. Itoh, T. Waho, J. Osaka, H. Yokoyama, and M. Yamamoto, “Ultrafast analog-to-digital converter using resonant-tunneling ternary quantizers,” Digest of IEEE MTT-S Int. Microwave Symp., Baltimore MD, June 1998, pp. 197 - 200. [IO] K. Maezawa and T. Mizutani, “A new resonant-tunneling logic gate employing monostable-bistable transition,” Jpn J. Appl. Phys. Pt. 2, vol. 32, no. IA-B, pp. L42 - L44, January 1993.
[ I ] J. Mitola 111, “Software Radio Architecture: Object-Oriented Approaches to Wireless Systems Engineering,” p. 289, John Wiley & Sons, New York, 2000. [2] Xiao, P., et al., “A 4b 8GSampleh A D Converter in SiGe Bipolar Technology,” ISSCC Digest of Technical Papers, pp. 124 - 125, February 1997. [3] G. Raghavan, M. Sokolich, and W. E. Stanchina, “Indium phosphide ICs unleash the high-frequency spectrum,” IEEE Spectrum, pp. 47 - 52, October 2000. [4] T. Waho and M. Yamamoto, “Application of resonant-tunneling quaternary quantizer to ultrahigh-speed A/D converter”, Proc. 27th IEEE International Symposium on Multiple-valued Logic, pp. 35 - 40, May 1997. [ 5 ] N. Shimizu, T. Nagatsuma, T. Waho, M. Shinagawa, M. Yaita and M. Yamamoto, ‘‘ InGaAs/AlAs resonant tunneling diodes with switching time of 1.5 ps,” Electron. Lett., vol. 3 1, no. 19, pp. 1695 - 1697, 1995. [6] T. Waho, “Resonant tunneling transistor and its application to
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(MML) circuits using RTDs [6] [7], and applied them to such ultrahigh-speed ADCs. The negative differential resistance of RTDs reduces the circuit complexity. RTD-based flash ADCs with sampling frequencies more than 5 GHz have been demonstrated by simulations and experiments [8] [9]. ADCs mentioned above, however, used RTDs only to quantize the input signal. For encoding from the quantizer output to the binary code, we used conventional source-coupled FET logic (SCFL) circuits, which required a relatively large number of transistors and consumed a considerable amount of power. In this paper, we propose an ADC that employs RTD-based complex gates not only as quantizers but also as encoder circuits. To convert multiple-valued thermometer code, the output of the quantizer, into the binary Gray code, we develop a new scheme consisting of temary-signal subtraction. This is obtained by combining the MML quantizer with another RTD-based circuit, or a monostable-to-bistable transition logic element (MOBILE) [lo]. In particular, we have developed a new operation mode of the MOBILE gate, i. e., the multiple-valued multiple-input mode. We call gate M2-MOBILE. Consisting of MML and M2-MOBILE, the complex gate is proved to be suitable to obtain a compact flash ADC. The structure of this paper is as follows. First, we explain the background and basic idea behind the new encoding scheme. Next, circuit configuration and operation principle of M2-MOBILE are presented. Then, a 4-bit ADC using the complex gates is described. Finally, SPICE simulation results that show a possible 4-bit 5-GS/s flash ADC with a reduced device count and power dissipation are presented.
Abstract We have proposed a flash analog-to-digital converter (ADC) that uses resonant-tunneling complex gates not only as ternary quantizers but also as ternary-to-binary encoder circuits. The ternary quantizers, consisting of monostable-to-multistable transition logic (MML) circuits, convert the analog input signal into the ternary thermometer code. This code is then converted into the binary Gray-code output by a multiple-valued, multiple-input monostable-to-bistable transition logic element (M2-MOBILE). By assuming InP-based resonant-tunneling diodes and heterojunction field-effect transistors, we have carried out SPICE simulation that demonstrates ultrahigh-speed ADC operation at a clock frequency of 5 GHz. Compact circuit conjiguration, which is due to the combination of MML and M2-MOBILE, reduces the device count and power dissipation by a factor of two compared with previous RTD-based ADCs.
1. Introduction Analog-to-digital converters (ADCs) with sampling frequencies over a few GHz have been required in the field of ultrahigh-speed instrumentation. Recently, they are also expected to play a crucial role in future wireless communications, particularly in realizing next-generation software-defined radio with a digital RFAF architecture [ 11. There have been several attempts to fabricate ultrahigh-speed ADCs by using SiGe [2] or InP [3] heterojunction bipolar transistors. As an altemative approach, we have proposed the use of InP-based resonant-tunneling diodes (RTDs) [4], which are known as the fastest semiconductor devices among others [5]. We have developed monostable-to-multistable transition logic
2. Background and basic idea The ADC operation
94
0-7695-1083-3/01 $10.00 0 2001 IEEE
comprises quantization
and
encoding. In this section, we explain the basic idea behind the new scheme for encoding, that is, how to convert the multiple-valued output of MML quantizers into the binary Gray-code output. The fastest analog-to-digital converter is the flash ADC. The number of comparators in flash ADCs, however, increases exponentially (2”-1) as the bit resolution n Increases. This means that the chip area and power dissipation also increase exponentially. To solve this problem, we previously proposed to introduce multiple-valued circuits between the analog input and the binary output, which makes a flash ADC quite compact [4]. Figure 1 shows such an ADC with ternary quantizers followed by a ternary-to-binary encoder. MSB stands for the most significant bit, while LSB is the least significant bit. Figure 2 shows typical transfer characteristics of an ADC, the output of which is called the Gray code, where “0” and “1” repeat periodically as the analog input increases. Although we were able to reduce the number of comparators, the encoder circuit remained unchanged and dissipated more power than comparators in the previous ADC design [4]. This IS because conventional source-coupled FET logic (SCFL) circuits were used in the encoder. Therefore, a challenge is to reduce encoder circuit
Ternaryto-Binary Encoder
Ternary Quantizer
MSB MSB-1
-
Figure 1. Flash ADC with ternary quantizers
Analog Input
Figure 2. Quantization and encoding
I
complexrtty.
The encodmg scheme we previously usedl is shown in Fig. 3. This is €OF the MS-B-2bit in Fig. 2’. First, two 2-1-0 ternary input signals are obtained by two temay quanheers. They are then converted into two binary 0-1-0 si finally by tahng “OR” of these signals we obtaln the 0- I-@-1-0)MSB-2 QLLQXI~To do this, we used conventional SCFL threshold detectors with the wired-OR function, which made the circuit configuration rather complicated Figure 4 shows the new encoding scheme we have proposed in this paper. We subtract one ternary signal from the other to obtain the 0-1-0-1-0 MSB-2 output at one time. We are able to do this by a complex gate, which consists of MML ternary quantizers and an M2-MOBILE gate.
L
OR Operation
Ternaly-to-Binary Conversion
Figure 3. Conventional encoder
-5
%
_ni-L
l--LG Subtraction
Figure 4. Present encoder
3. Multiple-valued multiple-input MOBILE gate (M~-MOBILE)
“CLK
?
We will explain the circuit configuration of M2-MOBILE and its operation used for implementing the new encoding scheme shown in Fig. 4.
* Figure 5. M2-MOBILEgate
95
To obtain the subtraction of two ternary signals, we used the MOBLE gate consisting of two RTDs- connected in series and two heterojunction field-effect-transistors (HFETs), as shown in Fig. 5(a). Two ternary input, x I and x2, are fed from two MML ternary quantizers, whose threshold voltages are (Val,Va2)and ( v b l , vb2). When the analog input voltage to the quantizers, xi,, is xi, 5 Val,Val < x,, 5 V,,, or Va2< xi,, the ternary signal to M I , x I , is "2", "l", or "O",respectively, as shown in Fig. 6. Similarly, x, is "2", "l", or "0," when xi, is xi, 2 vb1, vb1 < xi, 5 v b z , or vb2 < xi,,, respectively. The differences between Val and v b l and between Va2 and v b 2 can be controlled by the method described in the next section. These threshold voltages are designed so that they occur alternatively. In other words, v b l < Val < v b , < Va2.As described below, the gate operates as a subtracter, and the output, x I - x2, is "high" when vb1 < xi, 2 Val or vb, < xi, 5 va2, and it is "low" otherwise. Since this MOBILE gate operates in the multiple-valued multiple-input mode, we call it M2-MOBILE. Now the operation principle of M*-MOBILE is described. The basic idea of the gate operation is the same as the usual MOBILE and MML logic. When two RTDs are connected in series and the applied voltage across the terminals VcLKincreases, the RTD having a smaller peak current switches earlier than the other. During the switch, the RTD state changes from the peak-current branch of lower resistance to the valley-current branch of higher resistance. If the pulse height of the clock signal, VCLK,is designed such that only one RTD switches when VcLKis high, then the output is "high" when the RTD "b" switches, and it is "low" when the RTD "a" switches. For the circuit shown in Fig. 5, if the RTD current mentioned above is replaced with the sum of the RTD current and the HFET drain current, the same criteria holds in determining which RTD switches, or whether the output is "high" or "low." The operation will be explained in detail by using Fig, 7. Two planes denoted as "a + M," and "b + M2" show the sum of RTD and HFET currents, and the cross -section corresponds to the border between the high and low outputs. For example, if x I = " 1 " and x2= "0", the peak current of "b + M2" is smaller than that of "a + M,," and RTD "b" switches when VcLKis high. This results in the "high" output, which corresponds to the subtraction: x I - x2= "1" - "0" = " 1" . The subtraction for two ternary variables explained above can be extended to that for four variables. This is obtained by adding two HFETs, as described in Fig. 8. In this case, the thresholds are determined such that VbI < Val < v d l < v,, < vb2 < va,< v d 2 < This is designed by setting the controlled voltages in the quantizers, which will be mentioned in the next section. By considering Kirchhoffs current law, we can analyze the transfer characteristics of the gate by substituting a + M I and b + M2
X I -x2
A
" 'bl
XIN
"b2
Figure 6. Transfer characteristics (a)
(b)
Figure 7. M2-MOBILEOperation
pv,,
1-
1i1 1I111H1
v,, C X I N < Val 12 11 12 12 v,, < X I N < v,, 1 1 2 2 v,, t x , < v,, 1 1 2 1 v,, cx,< v,
1 1 1 1
.
0 1 1 0 0 1 1
V b 2 4 X I N s V s1 Z
v,
v@cx/N5
v,~.
Figure 8. Extended M2-MOBILE
96
in Fig. 7 with a + M, + M3 and b + M2 + M4, respectively. Thus the output is high when V,, < x,, < V,, or V,, < x,, < V,,, and it is ‘‘low’’ otherwise, where i = 1, 2. In this way, we can obtain RTD-based compact encoding circuits, the output of which consists of the 0-1-0-1-... signal.
(a)
(b)
I
MSB
......................... C
4.4-bit ADC with MML/M2-MOBILE gates Now we will explain a 4-bit flash ADC using MML/M2-MOBILE complex gates. The output waveforms for the 4-bit ADC, MSB, MSB-I, LSB+I, and LSB, are shown in Fig. 9. M2-MOBILE is applied to LSB and LSB+I, while a modified one is used for MSB-1, which will be described shortly. We used a simple inverter for MSB. Figure 10(a) shows an MML ternary quantizer that has an additional HFET with the control voltage V, to vary threshold voltages. As shown in Fig. lO(b), two threshold voltages, V , and V,, decreases as V, increases, because of the linear summation of the drain current flowing into the two HFETs. We represent this quantizer with a symbol shown in Fig. lO(c). For LSB+1, an MML/M2-MOBILE gate shown in Fig. 11 was used. Two buffers were emitter followers consisting of HFETs, and were used as level shifters. The control voltage V‘, was smaller than V t so that the two threshold voltages in “c” were larger than the corresponding ones in “d”. This should results in the output waveform as expected for the LSB+l . For LSB, we used an MML/M2-MOBILE complex gate as shown in Fig. 12. This consists of four MML ternary quantizers shown in Fig. 10 followed by buffers and an M2-MOBILE subtraction gate shown in Fig. 8. Four controlling voltages were designed such that V: < V,h < V,‘ < V!. TO obtain the output waveforms shown in Fig. 9, these voltages also satisfied the following conditions: V: < V,“ < V,h, and V‘, < V p < V!.
(e - d
+ (g - h)
b xIN
xIN
Figure 9. Threshold design for 4-bit ADC
Figure 10. MML ternary quantizer with variable thresholds I
Figure 11. LSB+l
v,h
Figure 12. LSB Figure 13. MSB-1
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VCLK
-5
For MSB-1, we used the complex gate similar to that for LSB+l, as shown in Fig. 13. To obtain the output waveforms shown in Fig. 9, the control voltage V t was designed to satisfy the following condition: V,h < V t < V t . It should be noted that we obtained “2 - 1 - 0” for the node A and “1 - 0 - 0” for the node B. We arranged the gate widths of HFETs, as shown in Fig. 13. By this arrangement, we were able to amplify the “1” signal at B to be comparable to the “2” signal at A, and obtained the “low high - low” output waveform for MSB-1 by the subtraction.
0.4
Q)
2 0.2 - 0 2 c
c 0
g -0.2 L
c I- -0.4
-0.3 -0.2 -0.1
0 0.1 Control Voltage, Vc (V)
Figure 14. Threshold control
5. Simulation results
(a)
...........................................................
Now SPICE simulation results will be described for the present 4-bit flash ADC. We assumed InP-based RTD and 0.15-pm HFET technology [8]. The peak current density of the RTD was 2 x IO5 A/cm2 and the peak-to-valley current ratio was 10. The HFET unity-current-gain cutoff frequency fr and the maximum oscillation frequencyfMM are 120 GHz and 200 GHz, respectively. Figure 14 shows threshold voltages of the MML temary quantizer shown in Fig. 10 as a function of the control voltage. As explained in the previous chapter, the threshold voltages decrease as the control voltage increases. This figure shows we can actually design 15 threshold voltages that are necessary to obtain 4-bit resolution. In the present circuit, both MML quantizers and M2-MOBILE subtraction circuits need clocked supply voltages. In this simulation the clock for the quantizer, I$,, increased with the rise time of 100 ps, as shown in Fig. 15(a). The quantizer output started increasing immediately after the clock rose, and the three levels evolved depending on the input voltage (Fig. 15(b)). After the clock for the quantizer was settled, that for the M2-MOBILE, q2, started increasing with the same rise time. The M2-MOBILE output increased and eventually resulted in one of the two levels as reached the stable state. Total time for conversion was 200 ps. Therefore, we can operate this ADC at a frequency of 5 GHz. It should be noted that we can use @, and @* as the two-phase clock in a pipeline structure. Then we might obtain sampling frequencies as high as 10 GHz. Figure 16 shows simulated transfer characteristics for LSB+l. Plotted values were sampled at 20 ps after the clocks stopped rising. Note that the quantizer outputs shown in Fig. 16(a) agree well with c and d in Fig. 9(a). Furthermore, the output shown in Fig. 16(b) corresponds to c-d in Fig. 9(b). Figure 17 shows the output waveforms for LSB. The quantizer outputs shown in Fig. 17(a) agree well with e, f, g, and h in Fig. 9(a), while the output waveform in Fig. 17(b) is compared to (e - 0 + (g - h) in Fig. 9(b). All these plots show that the present ADC operates successfully.
............................. 0
50
100
200
150
250
Quantizer
LSB + 1
..............
I
0
50
100
150
200
250
Time [ps] Figure 15. MMUM2-MOBILEcomplex gate (Simulation) (a)
0.6
0 0 -0.6 -0.4
-0.2
0
0.2
0.4
-0.4
-0.2
0
0.2
0.4
Input Voltage [VI
Figure 16. LSB+I (simulation) (a)
0.6
WE o :2 5 2 -0.6 L -
._ c
-0.4
-0.2
0.2
0.4
4.4
4.2 0 0.2 Input Voltage [VI
0.4
0
Figure 17. LSB (simulation)
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6.‘Discussion Table 1 compares device counts in present ADC with those in a previous one. Although the numbers for the quantizers are the same, those for the encoder are much reduced by introducing RTDs into the encoder circuits. This reduces the number of current path from 36 to 25. Our preliminary study on power dissipation reveals that it has been reduced by a factor of two compared with the previous RTD-based ADC. This is mainly attributed to the reduction in the number of SCFL current paths from 28 to 13, where the static power dissipation dominates. Estimated power dissipation for the present 4-bit ADC was 0.3 W, which is considerably lower than 0.5 W obtained by using SiGe bipolar technology [2].
input signal into the binary Gray-code output, where “high” and “low” levels are repeated periodically. Using InP-based device models, we carried out SPICE simulation that demonstrated a possible 4-bit flash ADC with an operation frequency more than 5 GHz. The device counts and power dissipation were reduced by a factor of two as compared to RTD-based ADCs demonstrated previously.
Table 1. Device Counts (4-bit ADCs)
I
I
Encoder
7. Conclusion
Total
We proposed an ultrahigh-speed ADC that uses the RTD-based MML and M2-MOBILE complex gate. By subtracting ternary signals, the gate converts the analog
Present
I Conventional I
I Quantizer 1 30RTDs I I 24 HFETs I
I
Current Path
I
8RTDs 17 HFETs 38 RTDs I 4 1 HFETs 12 (RTD) 13(HFET)
1
I
30 24
I
0
1 1 1
53 30 77 8 28
I
I
References multiple-valued logic circuits,” Proc. 25th Int. Symp. Multiple-Valued Logic, pp. 130 - 138, 1995. [7] T. Waho, K. J. Chen and M. Yamamoto, “Resonant-Tunneling Diode and HEMT Logic Circuits with Multiple Thresholds and Multi-Level Output,” IEEE J. Solid-state Circuits, Vol. 33, No. 2, pp. 268 - 274, February 1998. [SI T. Waho, T. Itoh, K. Maezawa, and M. Yamamoto, “Multi-GHz AID converter using resonant-tunneling multiple-valued logic circuits,” ISSCC Digest of Technical Papers, pp. 258 - 259, February 1998. 191 T. Itoh, T. Waho, J. Osaka, H. Yokoyama, and M. Yamamoto, “Ultrafast analog-to-digital converter using resonant-tunneling ternary quantizers,” Digest of IEEE MTT-S Int. Microwave Symp., Baltimore MD, June 1998, pp. 197 - 200. [IO] K. Maezawa and T. Mizutani, “A new resonant-tunneling logic gate employing monostable-bistable transition,” Jpn J. Appl. Phys. Pt. 2, vol. 32, no. IA-B, pp. L42 - L44, January 1993.
[ I ] J. Mitola 111, “Software Radio Architecture: Object-Oriented Approaches to Wireless Systems Engineering,” p. 289, John Wiley & Sons, New York, 2000. [2] Xiao, P., et al., “A 4b 8GSampleh A D Converter in SiGe Bipolar Technology,” ISSCC Digest of Technical Papers, pp. 124 - 125, February 1997. [3] G. Raghavan, M. Sokolich, and W. E. Stanchina, “Indium phosphide ICs unleash the high-frequency spectrum,” IEEE Spectrum, pp. 47 - 52, October 2000. [4] T. Waho and M. Yamamoto, “Application of resonant-tunneling quaternary quantizer to ultrahigh-speed A/D converter”, Proc. 27th IEEE International Symposium on Multiple-valued Logic, pp. 35 - 40, May 1997. [ 5 ] N. Shimizu, T. Nagatsuma, T. Waho, M. Shinagawa, M. Yaita and M. Yamamoto, ‘‘ InGaAs/AlAs resonant tunneling diodes with switching time of 1.5 ps,” Electron. Lett., vol. 3 1, no. 19, pp. 1695 - 1697, 1995. [6] T. Waho, “Resonant tunneling transistor and its application to
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