Flicker Noise in Advanced CMOS Technology: Effects of Halo Implant
Flicker Noise in Advanced CMOS Technology: Effects of Halo Implant Navid Paydavosi, Sriramkumar Venugopalan, Angada Sachid, Ali Niknejad Ali Niknejad, Chenming Hu Electrical Engineering and Computer Science University of California, Berkeley University of California, Berkeley Berkeley, CA, U.S.A.
Sagnik Dey, Samuel Martin, Xin Zhang Advanced CMOS Technology Development Texas Instruments Dallas, TX, U.S.A
UC Berkeley, ESSDERC 2013
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Outline • • • • • • •
Motivation Flicker Noise and Unified Flicker Noise Model Measurements Model Verification Discussions Conclusions
UC Berkeley, ESSDERC 2013
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Motivation: System On Chip Motivation: System On Chip
UC Berkeley, ESSDERC 2013
digital CMOS
• Short Channel Effects
RF CMOS
• Noise 3
Flicker (1/f) Noise Flicker (1/f) Noise • Flicker noise: the fluctuation of drain current due to Oxide Traps: Oxide Traps: 1. Reduction in channel carrier density 2. Change in mobility due to Coulomb Scattering Gate Acceptor type
Donor type Donor type Oxide
Source
UC Berkeley, ESSDERC 2013
Drain
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Unified Flicker Noise Model Unified Flicker Noise Model
UC Berkeley, ESSDERC 2013
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Halo (Pocket) Implant Halo (Pocket) Implant • non‐uniform doping concentration
• non‐uniform trap distribution [2,5,8,9]
UC Berkeley, ESSDERC 2013
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Approaches Suggested in Literature Approaches Suggested in Literature Assuming only non‐uniform doping concentration:
[11] The equation and the graph have been taken directly from [11]: Pocket implantation effect on drain current flicker noise in analog Pocket implantation effect on drain current flicker noise in analog nMOSFET devices, Wu et al., devices, Wu et al., TED, vol. 51, no. 8, 2004 UC Berkeley, ESSDERC 2013
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Measurement Measurement • Measurements were done on short and long‐channel NMOSs fabricated by CMOS 45‐nm fabricated by CMOS 45 nm node technology node technology • A S300 semi‐auto prober with BTA9812 noise analyzer were used
Drain Current Increasing
UC Berkeley, ESSDERC 2013
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Measurement Measurement Short Channel
Width: Long‐channel: 10 µm Short‐channel: 5 µm
Long Channel
UC Berkeley, ESSDERC 2013
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Measurement Measurement Observations: 1) Comparable Noise in Short and long channels Short Channel 2) Significant bias 2) Significant bias dependence Long Channel Long Channel
UC Berkeley, ESSDERC 2013
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Measurement Measurement Observations: 1) Comparable Noise in Short and long channels 2) Significant bias 2) Significant bias dependence 3) Usual practice of the unified flicker‐noise unified flicker noise model is inadequate
More complex mechanisms are Involved.
UC Berkeley, ESSDERC 2013
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Methodology
Pocket MOSFET Pocket MOSFET
UC Berkeley, ESSDERC 2013
Intrinsic MOSFET Intrinsic MOSFET
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Methodology cont. Methodology cont • Weighted Weighted contributions based on the equivalent contributions based on the equivalent transimpedances
HSPICE, small signal analysis
UC Berkeley, ESSDERC 2013
BSIM6
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BSIM6: Industry Standard bulk model BSIM6: Industry Standard bulk model • BSIM6 – Industry standard bulk MOSFET model – All real device effects (SCE, CLM etc.) from BSIM4 Symmetry • Symmetry – Currents, Caps & derivatives are symmetric @ VDS=0 – Provide accurate results in analog/RF simulations e.g. Provide accurate results in analog/RF simulations e g Harmonic Distortion simulation Physical Capacitance model • Physical Capacitance model • Smooth behavior in all regions of operations – Faster Convergence Faster Convergence UC Berkeley, ESSDERC 2013
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BSIM6: AC Symmetry test (C McAndrew IEEE TED 2006) (C. McAndrew, IEEE TED, 2006) Capacitance & derivatives are symmetric
UC Berkeley, ESSDERC 2013
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Model Validation: Long Channel Model Validation: Long Channel
A B C A, B, C A’, B’, C’, NDEP
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Discussion
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Discussion
0
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Model Validation: Short Channel Model Validation: Short Channel
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Discussion
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Discussion
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Conclusions
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THANKS FOR LISTENING, THANKS FOR LISTENING ANY QUESTION?
UC Berkeley, ESSDERC 2013
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Sagnik Dey, Samuel Martin, Xin Zhang Advanced CMOS Technology Development Texas Instruments Dallas, TX, U.S.A
UC Berkeley, ESSDERC 2013
1
Outline • • • • • • •
Motivation Flicker Noise and Unified Flicker Noise Model Measurements Model Verification Discussions Conclusions
UC Berkeley, ESSDERC 2013
2
Motivation: System On Chip Motivation: System On Chip
UC Berkeley, ESSDERC 2013
digital CMOS
• Short Channel Effects
RF CMOS
• Noise 3
Flicker (1/f) Noise Flicker (1/f) Noise • Flicker noise: the fluctuation of drain current due to Oxide Traps: Oxide Traps: 1. Reduction in channel carrier density 2. Change in mobility due to Coulomb Scattering Gate Acceptor type
Donor type Donor type Oxide
Source
UC Berkeley, ESSDERC 2013
Drain
4
Unified Flicker Noise Model Unified Flicker Noise Model
UC Berkeley, ESSDERC 2013
5
Halo (Pocket) Implant Halo (Pocket) Implant • non‐uniform doping concentration
• non‐uniform trap distribution [2,5,8,9]
UC Berkeley, ESSDERC 2013
6
Approaches Suggested in Literature Approaches Suggested in Literature Assuming only non‐uniform doping concentration:
[11] The equation and the graph have been taken directly from [11]: Pocket implantation effect on drain current flicker noise in analog Pocket implantation effect on drain current flicker noise in analog nMOSFET devices, Wu et al., devices, Wu et al., TED, vol. 51, no. 8, 2004 UC Berkeley, ESSDERC 2013
7
Measurement Measurement • Measurements were done on short and long‐channel NMOSs fabricated by CMOS 45‐nm fabricated by CMOS 45 nm node technology node technology • A S300 semi‐auto prober with BTA9812 noise analyzer were used
Drain Current Increasing
UC Berkeley, ESSDERC 2013
8
Measurement Measurement Short Channel
Width: Long‐channel: 10 µm Short‐channel: 5 µm
Long Channel
UC Berkeley, ESSDERC 2013
9
Measurement Measurement Observations: 1) Comparable Noise in Short and long channels Short Channel 2) Significant bias 2) Significant bias dependence Long Channel Long Channel
UC Berkeley, ESSDERC 2013
10
Measurement Measurement Observations: 1) Comparable Noise in Short and long channels 2) Significant bias 2) Significant bias dependence 3) Usual practice of the unified flicker‐noise unified flicker noise model is inadequate
More complex mechanisms are Involved.
UC Berkeley, ESSDERC 2013
11
Methodology
Pocket MOSFET Pocket MOSFET
UC Berkeley, ESSDERC 2013
Intrinsic MOSFET Intrinsic MOSFET
12
Methodology cont. Methodology cont • Weighted Weighted contributions based on the equivalent contributions based on the equivalent transimpedances
HSPICE, small signal analysis
UC Berkeley, ESSDERC 2013
BSIM6
13
BSIM6: Industry Standard bulk model BSIM6: Industry Standard bulk model • BSIM6 – Industry standard bulk MOSFET model – All real device effects (SCE, CLM etc.) from BSIM4 Symmetry • Symmetry – Currents, Caps & derivatives are symmetric @ VDS=0 – Provide accurate results in analog/RF simulations e.g. Provide accurate results in analog/RF simulations e g Harmonic Distortion simulation Physical Capacitance model • Physical Capacitance model • Smooth behavior in all regions of operations – Faster Convergence Faster Convergence UC Berkeley, ESSDERC 2013
14
BSIM6: AC Symmetry test (C McAndrew IEEE TED 2006) (C. McAndrew, IEEE TED, 2006) Capacitance & derivatives are symmetric
UC Berkeley, ESSDERC 2013
15
Model Validation: Long Channel Model Validation: Long Channel
A B C A, B, C A’, B’, C’, NDEP
UC Berkeley, ESSDERC 2013
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Discussion
1
UC Berkeley, ESSDERC 2013
0
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Discussion
0
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1
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Model Validation: Short Channel Model Validation: Short Channel
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Discussion
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Discussion
UC Berkeley, ESSDERC 2013
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Conclusions
UC Berkeley, ESSDERC 2013
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THANKS FOR LISTENING, THANKS FOR LISTENING ANY QUESTION?
UC Berkeley, ESSDERC 2013
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