for Phase-Change Memories - IEEE Xplore
Set-Sweep Programming Pulse for Phase-Change Memories F.
Bedeschil, C. Boffino2'3, E. Bonizzoni23, C. Restal 3
G. Torelli2, and D. Zella3,*
STMicroelectronics, Memory Product Group, via Olivetti, 2 - 20041 Agrate Brianza (MI) - ITALY 2 Department of Electronics, University of Pavia, via Ferrata, 1 - 27100 Pavia - ITALY 3 Studio di Microelettronica, STMicroelectronics & University of Pavia, via Ferrata, 1 - 27100 Pavia - ITALY now with STMicroelectronics, Automotive Product Group, via Tolomeo, 1 - 20010 Cornaredo (MI) - ITALY
Abstract - This paper presents a non-conventional program pulse approach for Phase-Change Memories (PCMs). The cell programming curve is experimentally evaluated and discussed. The proposed Set-Sweep program pulse allows compensating for spreads in cell physical parameters. This ensures a better SET condition for marginal cells and adequately narrow SET distributions, which results in
improved read margin. Experimental results have been
collected from a 8-Mb BJT-selected PCM demonstrator. The effectiveness of the proposed program pulse has been proved by comparing cell distributions obtained on the whole array by means of a conventional SET box and a Set-Sweep program pulse, respectively. I. INTRODUCTION
Phase-Change Memories (PCMs) [1], [2], also referred to as Ovonic Unified Memories (OUMs), are one of the most promising candidates for the next generation of semiconductor non-volatile memory devices. Indeed, PCMs ensure excellent compatibility with standard CMOS fabrication processes together with very high performance during reading and reprogramming operations as compared to currently dominant Flash memories. In particular, PCMs have the capability of shorter random access time versus NAND-based Flash memories and improved write throughput versus NOR-based Flash memories. High endurance and the potential to be scaled beyond Flash technology limits make PCM technology very attractive for both embedded and stand-alone applications. A further key feature is very fine write granularity, since any bit can be independently reprogrammed with no need for block erasing. In PCMs, the storage device is made of a thin film of chalcogenide alloy (in our case, Ge2Sb2Te5, GST [3]). This material can reversibly change between an amorphous phase (high impedance, RESET state, logic 0) and a polycrystalline phase (low impedance, SET state, logic 1) when thermally stimulated, thus allowing information storage. Memory element programming is obtained by properly heating (by means of electrical pulses applied to a suitable heater element) and then cooling a small, thermally isolated portion of the chalcogenide material. Once the chalcogenide alloy melts, it completely loses its crystalline structure. When rapidly cooled, the chalcogenide material is locked into
0-7803-9390-2/06/$20.00
©C2006 IEEE
its amorphous state (to this end, the cooling operation rate has to be faster than the crystal growth rate). To switch the memory element back to its crystalline state, the chalcogenide material is heated to a temperature between its glass transition temperature and its melting point This way, nucleation and micro-crystal growth occur in tens of nanoseconds, thus leading to a (poly)crystalline state. To limit overall reprogramming time in PCM devices,
temperature.
approach is to perform write and erase operations without resorting to program&verify and erase&verify techniques [4], [5]. The need for a programming technique that allows obtaining very an attractive
narrow distributions of the SET-state cell resistance
(hereinafter referred to as SET distributions) and, hence, an adequately robust read margin, is therefore apparent. Conventionally, SET program operation is achieved by means of a single box pulse of a couple hundreds of nanoseconds. The resulting SET distribution typically turns out to be affected by spreads in cell physical parameters, which can lead to a degraded SET distribution width. In this paper, a non-conventional Set-Sweep programming pulse and its effect on the PCM storage element programming curve are presented and discussed. The proposed programming technique allows compensating for spreads in cell physical parameters. This ensures a better SET condition for marginal cells and adequately narrow SET distributions, which results in improved read margin. To demonstrate the effectiveness of the proposed approach, experimental results have been collected from a 0.18-ptm CMOS 8-Mb PCM test chip in which a Bipolar Junction Transistor (BJT) has been used as a cell selector [6]. I.CL
RGAMN
UV
N
E-WE
US
In our 8-Mb Phase-Change Memory demonstrator, memory elements are arranged in the array as shown in Figure 1, where a pnp Bipolar Junction Transistor is employed as a cell selector in order to minimize silicon area occupation and, hence, improve data storage density. The resulting cell size is 0.32 pim , corresponding to 10 F2 in 0.18-im technology.
967
ISCAS 2006
BLm
WL
n__
L
BLm+1
BLm+2
L
Figure 3 depicts the current drawn in read operation
by a cell in the memory array (hereinafter referred to as cell current) as a function of programming bit-line
voltage and programming time. In read operations, an adequate voltage VREAD is applied to the gate of device Yo (which operates in the saturation region), thereby forcing the required sense voltage to the bit-line and, hence, across the addressed storage element [7]. The ensuing cell current can be easily measured by means of the sense amplifiers integrated in the test-chip [8].
L
WLn_1 WL n+2 rJ
12
1
1t
/
_60_
//
D~~~~~~~~~~~~~~~~~~~~~~~0Z055-60 50 D ~ ~ ~ ~ ~ 0 -5
-
45I'l45
Storage Element
1 40
Figure 1. Detail of the memory array (BL bit-line; WL word-line).
25o p
=
202
50
AI40-45 M35-40 350-3 a 20-25 ~~~~
p
-~~~~~~~~
E~~~M15-20
10-15
U5-10
15-
~~~~~~~~~~~~~~~MO-5
10-
10
WE
D
~~~~~~~~~~~~~~~~~~1-j200
50
ADDX
0
Yo,
~~~~~~~~Figure 3. Current drawn by a cell in the memory array as a ................function of bit-line voltage and programming time.
VR*SEW
VREATDLE
ADDY
orgazVPCX VA
Figures2: Conceptual diagram of thetestchiparray.
The programming curve in Figure 3 has been obtained by applying a single SET box pulse with an amplitude ranging from 1 V to 2.6 V (voltage step 50 mV) and a length from 50 ns tot iIs (time step 50 ns). After each SET box pulse, a suitable program voltage was applied to
the cell so as to switch back the memory element to the RESET state. From Figure 3, it is apparent that the maximum cell current is in the range from 55 to 60 _tA. Furthermore,
A schematic diagram of the test chip array about 55 ~tA organisation is depicted in Figure2. The array is pulse is used. organized in two 4-Mb tiles (2048 word-lines by 2048 is local bit-lines). A two-level hierarchical approach tda adopted for bit-line driving: any main bit-line feeds two local bit-lines (one per each tile) through respective local selectors Yo,, (i= 0 to 7), implemented by natural n-channel devices. The DC voltages required for the different operations of the array are provided through separate pins for better flexibility and observability.
ProgramvoltagesVSETand VRESET, together with read
it
is
programming time
worth
to
as short as
can be
point
50ans,
obtained, when
out
that,
for
a
a cell current of a 2.1-V SET box 1000
800 c DSS5-60 05
60''E gi 500 E
400
450E
[404
[154
305
~~~~~~~~~~~~~~~~~~~~~~~~~~~~P112-3
968~~~~~~~~~~~~~~~~~~~~~~~~5
Figure 4 shows the two-dimensional representation of the cell programming curve depicted in Figure 3. The area in which the cell is programmed to its maximum current value is quite wide. In particular, the bit-line programming voltage window increases for increasing programming time. This can be understood by considering the relation between the bit-line programming voltage and the temperature reached by the storage material. On the one hand, in the case of a very short programming time, the optimum temperature has to be reached so as to allow the chalcogenide material to be adequately crystallized. On the other hand, if the storage element is not heated to its optimum temperature, a longer programming time is required so as to obtain adequate material crystallization. From Figure 4, it is also observed that the cell can be considered to be in the RESET state for any programming time when bit-line voltages higher than 2.55 V are used. This means that, for such voltages, any programming time brings the cell to its high-impedance amorphous state.
non-optimum pair of programming voltage and time for some cells in the considered population. This can affect the width of the obtained SET distributions, thus leading to a reduced read margin. These drawbacks can be overcome by applying a Set-Sweep pulse [9], which consists in a trapezoidal pulse, characterized by a maximum and a minimum SET voltage, VM and Vm, respectively, and a time length Ts (Figure 6). 0
j
E
0
Vm-
Programming Time
Ts]
j~~~~~~~~~~~~~~~~~~~~T
m Lnmia is]
Figure 6. Set-Sweep program pulse. It is worth to point out that the Set-Sweep pulse technique allows different SET voltages to be applied to each cell during programming. For better understanding
0 0tAi i
this programming approach, it has to be considered that, as mentioned above, each cell has a specific optimum T2 --------SET voltage for a determined programming time. By T3 -----|- - using a trapezoidal SET program pulse, different optimum SET voltages can be applied to different cells Programming V1V8V2 V3 n being programmed simultaneously. To be more specific, if the optimum program voltage of a cell is comprised in Figure 5. Programming curves of three cells. the range from VM to Vm, the cell turns out to be with conditions. In addition, it Let Let us now consider a population consisting of cnd more should be pointedoptimum out that the SET process is a ore even though imum than one cell. For simplicity, we will analyze the case of cumulatie one[ even the Therefore, though the three cells. The programming curves (as a function of SEt programming voltage and time) to obtain a given current program pulse, the cumulative SET effect of the applied Ic for three cells are depicted in Figure 5. For each curve, program voltages can make them switch from the RESET m prove their crystallization tallizaT the minimum programming time (Ti, T2, and T3) and the togthe to the SEltate SET state or or improve their opiu rgamngvlae(I corresponding optimum programming voltage ( Vi, V2, condition. It is now easy to understand why the te oweytoueradwh and V3) are shown. The misalignment among Set-Sweep program pulse technique can compensate for thei programmgin curves and theilr dfferent shapes are due to spreads in cell physical parameters, thus obtaining narrow the spread in cell physical parameters. The intersection SET distribution and, hence, improved read margin. area, A, of the three programming curves is highlighted in Figure 5. In order to well crystallize all the cells by means III. MEASUREMENT RESULTS ON A MEMORY ARRAY of a conventional single SET box pulse, a pair of programming voltage and time values in the region A has to be chosen. TB and VB are the minimum programming The Set-Sweep programming approach has been time and the corresponding voltage, respectively, that can experimentally characterized on our 8-Mb BJT-selected be used to bring all cells to a good SET state by means of PCM demonstrator. The test chip was integrated by using a single SET box pulse. When a population with a large a single-poly, single-well, O.18-im CMOS technology. number of cells is considered, the spread in cell physical Figure 7 shows a chip microphotograph. In order to fit in parameters typically increases TB, thus affecting write a standard pad frame configuration, large unused areas throughput. Furthermore, when adopting a single SET are present in the chip periphery. In our demonstrator, the box program technique, the risk exists to use a Set-Sweep program pulse is provided by using an Ts
--------
----
VolPame us
n
aputprogrammed
oltage [s].
corresponding~~~~~
andVgrammingcureeshwn.
th misalignentshapesamonguethecodtn.Iis
969
opltmum
external waveform generator directly connected to the SET voltage pin. In a commercial device, the Set-Sweep program pulse can be easily generated on-chip by means of an adequate programmable voltage regulator. To better prove the effectiveness of the proposed program pulse, the whole 8-Mb array was first programmed by means of a single SET box and then, after a RESET operation, by applying a suitable Set-Sweep pulse (VM = 2.25 V, Vm = 1.95 V). The time length of both program pulses was 150 ns.
that the Set-Sweep pulse programming technique ensures a better SET condition for marginal cells in the distribution. Hence, a robust and improved read margin is achieved. IV. CONCLUSIONS In this paper, a non-conventional Set-Sweep programming pulse and its effect on the Phase-Change Memory storage element programming curve are presented, experimentally evaluated, and discussed. The proposed Set-Sweep program pulse allows compensating for spreads in cell physical parameters. This ensures a better SET condition for marginal cells and adequately narrow SET distributions, which results in improved read margin. Experimental results have been collected from a 8-Mb BJT-selected PCM demonstrator. The effectiveness of the proposed program pulse has been proved by comparing cell distributions obtained on the whole array by means of a conventional SET box and a Set-Sweep program pulse, respectively. REFERENCES [1]
G. Wicker, T. Lowrey, S. Hudgens, and K. Hunt, "Nonvolatile, high density, high performance phase-change memory", Proc. 2000 IEEE Aerospace Conference, vol. 5, march 2000, pp. 385-
[2]
M. Gill, T. Lowrey, and J. Park, 'Ovonic Unified Memory - A high performance nonvolatile memory technology for stand-alone memory and embedded applications", 2002 IEEE Solid-State Circuits Conference Dig. Tech. Pap., vol. 1, Feb. 2002, pp. 458-459.
[3]
F. Pellizzer, A. Pirovano, F. Ottogalli, M. Mangistretti, M. Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, A. Modelli, E. Varesi, T. Lowrey, A. Lacaita, G. Casagrande, P. Cappelletti, and R. Bez, "Novel itrench phase-change memory cell for embedded and standalone non-volatile memory applications", Proc. 2004 Symposium on VLSI Technology, June 2004, pp. 18-19.
S. Tyson,
390.
Figure 7. Chip microphotograph. -Set-Sweep Pulse -Sngle Box Pulse 7000000 6000000_
0
:,
5000000
X[4]
47000000
Bedeschil, C. Boffino2'3, E. Bonizzoni23, C. Restal 3
G. Torelli2, and D. Zella3,*
STMicroelectronics, Memory Product Group, via Olivetti, 2 - 20041 Agrate Brianza (MI) - ITALY 2 Department of Electronics, University of Pavia, via Ferrata, 1 - 27100 Pavia - ITALY 3 Studio di Microelettronica, STMicroelectronics & University of Pavia, via Ferrata, 1 - 27100 Pavia - ITALY now with STMicroelectronics, Automotive Product Group, via Tolomeo, 1 - 20010 Cornaredo (MI) - ITALY
Abstract - This paper presents a non-conventional program pulse approach for Phase-Change Memories (PCMs). The cell programming curve is experimentally evaluated and discussed. The proposed Set-Sweep program pulse allows compensating for spreads in cell physical parameters. This ensures a better SET condition for marginal cells and adequately narrow SET distributions, which results in
improved read margin. Experimental results have been
collected from a 8-Mb BJT-selected PCM demonstrator. The effectiveness of the proposed program pulse has been proved by comparing cell distributions obtained on the whole array by means of a conventional SET box and a Set-Sweep program pulse, respectively. I. INTRODUCTION
Phase-Change Memories (PCMs) [1], [2], also referred to as Ovonic Unified Memories (OUMs), are one of the most promising candidates for the next generation of semiconductor non-volatile memory devices. Indeed, PCMs ensure excellent compatibility with standard CMOS fabrication processes together with very high performance during reading and reprogramming operations as compared to currently dominant Flash memories. In particular, PCMs have the capability of shorter random access time versus NAND-based Flash memories and improved write throughput versus NOR-based Flash memories. High endurance and the potential to be scaled beyond Flash technology limits make PCM technology very attractive for both embedded and stand-alone applications. A further key feature is very fine write granularity, since any bit can be independently reprogrammed with no need for block erasing. In PCMs, the storage device is made of a thin film of chalcogenide alloy (in our case, Ge2Sb2Te5, GST [3]). This material can reversibly change between an amorphous phase (high impedance, RESET state, logic 0) and a polycrystalline phase (low impedance, SET state, logic 1) when thermally stimulated, thus allowing information storage. Memory element programming is obtained by properly heating (by means of electrical pulses applied to a suitable heater element) and then cooling a small, thermally isolated portion of the chalcogenide material. Once the chalcogenide alloy melts, it completely loses its crystalline structure. When rapidly cooled, the chalcogenide material is locked into
0-7803-9390-2/06/$20.00
©C2006 IEEE
its amorphous state (to this end, the cooling operation rate has to be faster than the crystal growth rate). To switch the memory element back to its crystalline state, the chalcogenide material is heated to a temperature between its glass transition temperature and its melting point This way, nucleation and micro-crystal growth occur in tens of nanoseconds, thus leading to a (poly)crystalline state. To limit overall reprogramming time in PCM devices,
temperature.
approach is to perform write and erase operations without resorting to program&verify and erase&verify techniques [4], [5]. The need for a programming technique that allows obtaining very an attractive
narrow distributions of the SET-state cell resistance
(hereinafter referred to as SET distributions) and, hence, an adequately robust read margin, is therefore apparent. Conventionally, SET program operation is achieved by means of a single box pulse of a couple hundreds of nanoseconds. The resulting SET distribution typically turns out to be affected by spreads in cell physical parameters, which can lead to a degraded SET distribution width. In this paper, a non-conventional Set-Sweep programming pulse and its effect on the PCM storage element programming curve are presented and discussed. The proposed programming technique allows compensating for spreads in cell physical parameters. This ensures a better SET condition for marginal cells and adequately narrow SET distributions, which results in improved read margin. To demonstrate the effectiveness of the proposed approach, experimental results have been collected from a 0.18-ptm CMOS 8-Mb PCM test chip in which a Bipolar Junction Transistor (BJT) has been used as a cell selector [6]. I.CL
RGAMN
UV
N
E-WE
US
In our 8-Mb Phase-Change Memory demonstrator, memory elements are arranged in the array as shown in Figure 1, where a pnp Bipolar Junction Transistor is employed as a cell selector in order to minimize silicon area occupation and, hence, improve data storage density. The resulting cell size is 0.32 pim , corresponding to 10 F2 in 0.18-im technology.
967
ISCAS 2006
BLm
WL
n__
L
BLm+1
BLm+2
L
Figure 3 depicts the current drawn in read operation
by a cell in the memory array (hereinafter referred to as cell current) as a function of programming bit-line
voltage and programming time. In read operations, an adequate voltage VREAD is applied to the gate of device Yo (which operates in the saturation region), thereby forcing the required sense voltage to the bit-line and, hence, across the addressed storage element [7]. The ensuing cell current can be easily measured by means of the sense amplifiers integrated in the test-chip [8].
L
WLn_1 WL n+2 rJ
12
1
1t
/
_60_
//
D~~~~~~~~~~~~~~~~~~~~~~~0Z055-60 50 D ~ ~ ~ ~ ~ 0 -5
-
45I'l45
Storage Element
1 40
Figure 1. Detail of the memory array (BL bit-line; WL word-line).
25o p
=
202
50
AI40-45 M35-40 350-3 a 20-25 ~~~~
p
-~~~~~~~~
E~~~M15-20
10-15
U5-10
15-
~~~~~~~~~~~~~~~MO-5
10-
10
WE
D
~~~~~~~~~~~~~~~~~~1-j200
50
ADDX
0
Yo,
~~~~~~~~Figure 3. Current drawn by a cell in the memory array as a ................function of bit-line voltage and programming time.
VR*SEW
VREATDLE
ADDY
orgazVPCX VA
Figures2: Conceptual diagram of thetestchiparray.
The programming curve in Figure 3 has been obtained by applying a single SET box pulse with an amplitude ranging from 1 V to 2.6 V (voltage step 50 mV) and a length from 50 ns tot iIs (time step 50 ns). After each SET box pulse, a suitable program voltage was applied to
the cell so as to switch back the memory element to the RESET state. From Figure 3, it is apparent that the maximum cell current is in the range from 55 to 60 _tA. Furthermore,
A schematic diagram of the test chip array about 55 ~tA organisation is depicted in Figure2. The array is pulse is used. organized in two 4-Mb tiles (2048 word-lines by 2048 is local bit-lines). A two-level hierarchical approach tda adopted for bit-line driving: any main bit-line feeds two local bit-lines (one per each tile) through respective local selectors Yo,, (i= 0 to 7), implemented by natural n-channel devices. The DC voltages required for the different operations of the array are provided through separate pins for better flexibility and observability.
ProgramvoltagesVSETand VRESET, together with read
it
is
programming time
worth
to
as short as
can be
point
50ans,
obtained, when
out
that,
for
a
a cell current of a 2.1-V SET box 1000
800 c DSS5-60 05
60''E gi 500 E
400
450E
[404
[154
305
~~~~~~~~~~~~~~~~~~~~~~~~~~~~P112-3
968~~~~~~~~~~~~~~~~~~~~~~~~5
Figure 4 shows the two-dimensional representation of the cell programming curve depicted in Figure 3. The area in which the cell is programmed to its maximum current value is quite wide. In particular, the bit-line programming voltage window increases for increasing programming time. This can be understood by considering the relation between the bit-line programming voltage and the temperature reached by the storage material. On the one hand, in the case of a very short programming time, the optimum temperature has to be reached so as to allow the chalcogenide material to be adequately crystallized. On the other hand, if the storage element is not heated to its optimum temperature, a longer programming time is required so as to obtain adequate material crystallization. From Figure 4, it is also observed that the cell can be considered to be in the RESET state for any programming time when bit-line voltages higher than 2.55 V are used. This means that, for such voltages, any programming time brings the cell to its high-impedance amorphous state.
non-optimum pair of programming voltage and time for some cells in the considered population. This can affect the width of the obtained SET distributions, thus leading to a reduced read margin. These drawbacks can be overcome by applying a Set-Sweep pulse [9], which consists in a trapezoidal pulse, characterized by a maximum and a minimum SET voltage, VM and Vm, respectively, and a time length Ts (Figure 6). 0
j
E
0
Vm-
Programming Time
Ts]
j~~~~~~~~~~~~~~~~~~~~T
m Lnmia is]
Figure 6. Set-Sweep program pulse. It is worth to point out that the Set-Sweep pulse technique allows different SET voltages to be applied to each cell during programming. For better understanding
0 0tAi i
this programming approach, it has to be considered that, as mentioned above, each cell has a specific optimum T2 --------SET voltage for a determined programming time. By T3 -----|- - using a trapezoidal SET program pulse, different optimum SET voltages can be applied to different cells Programming V1V8V2 V3 n being programmed simultaneously. To be more specific, if the optimum program voltage of a cell is comprised in Figure 5. Programming curves of three cells. the range from VM to Vm, the cell turns out to be with conditions. In addition, it Let Let us now consider a population consisting of cnd more should be pointedoptimum out that the SET process is a ore even though imum than one cell. For simplicity, we will analyze the case of cumulatie one[ even the Therefore, though the three cells. The programming curves (as a function of SEt programming voltage and time) to obtain a given current program pulse, the cumulative SET effect of the applied Ic for three cells are depicted in Figure 5. For each curve, program voltages can make them switch from the RESET m prove their crystallization tallizaT the minimum programming time (Ti, T2, and T3) and the togthe to the SEltate SET state or or improve their opiu rgamngvlae(I corresponding optimum programming voltage ( Vi, V2, condition. It is now easy to understand why the te oweytoueradwh and V3) are shown. The misalignment among Set-Sweep program pulse technique can compensate for thei programmgin curves and theilr dfferent shapes are due to spreads in cell physical parameters, thus obtaining narrow the spread in cell physical parameters. The intersection SET distribution and, hence, improved read margin. area, A, of the three programming curves is highlighted in Figure 5. In order to well crystallize all the cells by means III. MEASUREMENT RESULTS ON A MEMORY ARRAY of a conventional single SET box pulse, a pair of programming voltage and time values in the region A has to be chosen. TB and VB are the minimum programming The Set-Sweep programming approach has been time and the corresponding voltage, respectively, that can experimentally characterized on our 8-Mb BJT-selected be used to bring all cells to a good SET state by means of PCM demonstrator. The test chip was integrated by using a single SET box pulse. When a population with a large a single-poly, single-well, O.18-im CMOS technology. number of cells is considered, the spread in cell physical Figure 7 shows a chip microphotograph. In order to fit in parameters typically increases TB, thus affecting write a standard pad frame configuration, large unused areas throughput. Furthermore, when adopting a single SET are present in the chip periphery. In our demonstrator, the box program technique, the risk exists to use a Set-Sweep program pulse is provided by using an Ts
--------
----
VolPame us
n
aputprogrammed
oltage [s].
corresponding~~~~~
andVgrammingcureeshwn.
th misalignentshapesamonguethecodtn.Iis
969
opltmum
external waveform generator directly connected to the SET voltage pin. In a commercial device, the Set-Sweep program pulse can be easily generated on-chip by means of an adequate programmable voltage regulator. To better prove the effectiveness of the proposed program pulse, the whole 8-Mb array was first programmed by means of a single SET box and then, after a RESET operation, by applying a suitable Set-Sweep pulse (VM = 2.25 V, Vm = 1.95 V). The time length of both program pulses was 150 ns.
that the Set-Sweep pulse programming technique ensures a better SET condition for marginal cells in the distribution. Hence, a robust and improved read margin is achieved. IV. CONCLUSIONS In this paper, a non-conventional Set-Sweep programming pulse and its effect on the Phase-Change Memory storage element programming curve are presented, experimentally evaluated, and discussed. The proposed Set-Sweep program pulse allows compensating for spreads in cell physical parameters. This ensures a better SET condition for marginal cells and adequately narrow SET distributions, which results in improved read margin. Experimental results have been collected from a 8-Mb BJT-selected PCM demonstrator. The effectiveness of the proposed program pulse has been proved by comparing cell distributions obtained on the whole array by means of a conventional SET box and a Set-Sweep program pulse, respectively. REFERENCES [1]
G. Wicker, T. Lowrey, S. Hudgens, and K. Hunt, "Nonvolatile, high density, high performance phase-change memory", Proc. 2000 IEEE Aerospace Conference, vol. 5, march 2000, pp. 385-
[2]
M. Gill, T. Lowrey, and J. Park, 'Ovonic Unified Memory - A high performance nonvolatile memory technology for stand-alone memory and embedded applications", 2002 IEEE Solid-State Circuits Conference Dig. Tech. Pap., vol. 1, Feb. 2002, pp. 458-459.
[3]
F. Pellizzer, A. Pirovano, F. Ottogalli, M. Mangistretti, M. Scaravaggi, P. Zuliani, M. Tosi, A. Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, A. Modelli, E. Varesi, T. Lowrey, A. Lacaita, G. Casagrande, P. Cappelletti, and R. Bez, "Novel itrench phase-change memory cell for embedded and standalone non-volatile memory applications", Proc. 2004 Symposium on VLSI Technology, June 2004, pp. 18-19.
S. Tyson,
390.
Figure 7. Chip microphotograph. -Set-Sweep Pulse -Sngle Box Pulse 7000000 6000000_
0
:,
5000000
X[4]
47000000
