high efficiency wide bandwidth power supplies for gsm ... - CiteSeerX
High Efficiency Wide Bandwidth Power Supplies for GSM and EDGE RF Power Amplifiers Yushan Li National Semiconductor 1820 Lefthand Circle, Longmont, CO 80501
Dragan Maksimovic University of Colorado ECE Dept., Boulder, CO 80309 [email protected]
[email protected]
Abstract—This paper presents and compares three circuit architectures that are promising candidates to efficiently and dynamically supply GSM and EDGE RF power amplifiers in handsets. The candidate architectures include a switcher with hysteretic control, and two linear-assisted switcher configurations. The architectures have been implemented and tested by simulation in a standard 0.5µ, µ, 5V CMOS process. The circuits are compared in terms of efficiency and reference tracking capabilities.
Figure 1. Linear regulator (LDO) as the power supply for an RF power amplifier.
I. INTRODUCTION In TDMA communication systems, such as GSM and EDGE, the power control of the RF power amplifier (PA) output has to meet the required time mask. One way to control the output RF power is through the control of its supply Vcc, as shown in Fig. 1. Assuming the commonly applied single-cell Li-Ion battery source, a linear regulator (“low-drop-out” or LDO) can be used to adjust the supply Vcc for the PA. In this power control architecture, the supply voltage Vcc has to slew from 0 to 3.7 V in 10-20 µs for the full power case (about 2 A), and Vcc has to precisely “track” the Vramp signal (reference) in a close-loop manner. Similar requirements are valid for the ramp down condition. In the GSM and linear EDGE systems, Vcc stays at the constant level (corresponding to certain output power level) during the transmission. In the polar EDGE system, Vcc also has to track the envelope of the modulated RF signal, while the RF input to the PA has constant envelope. An advantage of the polar EDGE system [1-2] is that a nonlinear RF PA can be used to improve its efficiency. Meeting the ramp time mask in GSM or linear EDGE systems requires a substantial slew-rate and bandwidth capability. Tracking the envelope in a polar EDGE system requires much wider bandwidth. A major challenge in practical realizations is to meet the high-bandwidth requirements while preserving the efficiency of the power supply for the RF PA.
II. CANDIDATE ARCHITECTURES A number of power supply architectures have been considered to address the GSM and EDGE PA applications. The following three architectures have been selected as the most promising ones: a hysteretic control switcher for GSM RF PA, and two linear-assisted switcher combinations: LDO+Switcher for the GSM and linear EDGE applications, and AB+Switcher for the polar EDGE application. A. Hysteretic Control Switcher Voltage-mode or current-mode constant-frequency PWM switchers are well known and commonly applied in DC-DC applications, with advantages including relatively small ripples, low conduction losses, and constant switching frequency. However, the wide-bandwidth tracking may require operation at very high switching frequencies, which reduces efficiency because of the switching losses. Switchers with hysteretic controls are also widely used [5-6]. The switching frequency is not constant, and varies adaptively depending on the load demands. The adaptive feature of the switching frequency is desirable for the high bandwidth requirement. Figure 2 shows a simple diagram of this architecture. The architecture has the advantage of relatively simple circuit implementation. The LC filter components are selected to meet the ripple requirements.
In conventional solutions based on an LDO [3-4], as illustrated in Fig. 1, the power supply efficiency is low at reduced power levels, when Vcc is low compared to the battery voltage Vbat. In this paper we describe and compare three alternative circuit architectures to achieve widebandwidth slewing and tracking requirements, while improving the efficiency over the full range of output power levels. Figure 2. Hysteretic control switcher architecture.
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B. LDO+Switcher Linear-assisted switchers are based on the idea of combining wide-bandwidth capabilities of linear regulators with high-efficiency of switching regulators. The “LDO+Switcher” architecture shown in Fig. 3 (similar to [7]) is one such combination. In the LDO+Switcher architecture of Fig. 3, two linear amplifiers are used: a current-sourcing amplifier for fast ramp up, and a current-sinking amplifier for fast ramp down. There is a small offset setup for the linear amplifiers so that they stay off during the steady state when the switcher provides all the load current. At extremely heavy loads, when Vcc is close to Vbat, this architecture also allows for load sharing between the switcher and the sourcing linear amplifier. The switcher can be a high efficiency PWM switcher, which can be synchronized with the system clock to reduce the impact of the switching noise in the receiver band. Low physical profile of this architecture can be realized with low inductance such as 1uH. A disadvantage of this architecture is that the output filter capacitance has to be relatively large to achieve small output voltage ripple. The large output capacitance imposes a challenge in designing the wide-bandwidth linear amplifiers.
Figure 3. LDO+Switcher architecture.
C. AB+Switcher The LDO+Switcher architecture has one important limitation when considered for polar EDGE applications: the linear amplifier output devices would turning on and off in attempting to track the RF envelope. The on-off transients, in combination with the relatively large filter capacitance are practical obstacles in meeting the widebandwidth envelope tracking requirement. An alternative linear-assisted architecture based on a combination of a class-AB linear amplifier and a switcher is considered to overcome this limitation. The “AB+Switcher” architecture is shown in Fig. 4. This kind of architecture has been reported for audio applications [8-13] and for RF envelope tracking [16], but only for relatively low tracking bandwidth. The bandwidth demands in a polar-EDGE application are significantly higher. In the AB+Switcher architecture of Fig. 4, the switcher provides the DC (and low frequency) load current, while the class-AB amplifier provides the high frequency load current while maintaining the tracking loop closed. The switcher is controlled by the output current of the class-AB amplifier.
The hysteretic current controller of the switcher attempts to minimize the output current of the class-AB amplifier, to maximize the overall efficiency. The output capacitance of this architecture is low to maintain the high bandwidth of the class-AB amplifier loop. It is important to note that the ripple current of the switcher has to be largely absorbed by the linear amplifier. Because of this, and because of the quiescent bias current for the class-AB output stage, this architecture is expected to have a lower efficiency compared with the LDO+Switcher architecture.
Figure 4. AB+Switcher architecture.
III. CIRCUIT DESIGN AND SIMULATION RESULTS A. Test Chip for Evaluation of Candidate Architectures In order to evaluate and compare the three different architectures in a practical circuit realization, a single test chip has been designed in a standard 0.5 µ, 5 V CMOS process. In the test chip, several building blocks, such as the large output transistors are re-used for all three architectures, while the control circuitry for each architecture can be individually selected by two programming bits. The circuits are intended to deliver up to 2 A to the RF PA. Each of the four transistors (2 for the switcher and 2 for the class AB amplifier or the LDOs) has the on resistance of about 80 mΩ. When the chip is configured for the particular architecture, all unnecessary blocks for the other architectures are shut down. B. Class-AB Amplifier, LDOs and Comparator The class-AB amplifier [14-15] shown in Fig. 5 has two stages: a folded cascode to provide the high gain, and a railto-rail output stage. The Miller compensation provides the dominant pole for the loop. There are two more nondominant poles: one from the output filter capacitance and one from the first stage input capacitance. The compensation network places a zero near the second pole of the loop to increase the phase margin. The capacitor in the feedback network also places a zero to further help the phase margin. Figure 6 shows the Bode plot of the loop gain. The phase margin is 72 degrees, the cross-over frequency is 8.4MHz, and the gain margin is 24dB. Floating current sources are used for the quiescent current control of the class-AB output stage. The quiescent current is 48mA, of which 47mA is from the output stage. There is a trade-off between the quiescent current and the amplifier linearity especially when the output current crossing over zero. The
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Figure 5. Schematic of the class-AB amplifier.
output current (Iab in Fig. 4) is sensed through the current mirrors of the output PMOS and NMOS. The LDO (class B) is a subset of the class-AB amplifier. The sourcing and sinking LDOs in the “LDO+Switcher” circuit are constructed from the class-AB amplifier by removing the output NMOS or PMOS, removed respectively, along with shutting down the quiescent control circuitry. The LDO bias current is about 1mA. Since the output capacitance of the “LDO+Switcher” is much larger than the “AB+Switcher” case, the compensation from proper output capacitor “esr” will help to maintain the good phase margin. The comparator in the hysteretic control switcher has the similar structure as the first gain stage of the class-AB amplifier.
current(s) from LDOs or AB amplifier; (c) error signal VfbVramp, where Vfb is the sensed feedback signal. The signal Vramp is ramped up and down in 10 µs with three steadystate values to represent the different output power levels. For the AB+Switcher architecture, a variable-frequency sinusoidal reference signal (50-220KHz) is instead applied to emulate the EDGE envelope signal. It can be seen that Vcc is able to track Vramp well in all three architectures. The LDO+Switcher shows better tracking than the hysteretic control switcher during the ramp up and ramp down transients. The AB+Switcher configuration can successfully track the 200KHz sinusoidal signal. We observe that the switcher in the linear-assisted LDO+Switcher and AB+Switcher configurations indeed provides the majority of the load current, which is important for high overall efficiency.
Figure 6. Loop gain Bode plot of class-AB amplifier.
C. Simulation Results Figures 7-9 show the waveforms obtained by simulation of the circuit implementations of the three architectures. In the simulations, a 10 µH inductor is used in all cases with 4.2V Vbat. The output filter capacitance is 2.2 µF for the hysteretic control switcher and the LDO+Switcher, and 10 nF for the AB+Switcher configuration. Signals in the waveforms are, from top to bottom: (a) Vcc, Vramp and Vfb overlapped; (b) Inductor current, and
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Figure 7. Simulated waveforms of the hysteretic control switcher.
Iload (mA) 2255 777 156
TABLE I ELECTRICAL EFFICIENCY COMPARISON Vcc Vramp Hyst. LDO+ LDO Switcher (V) (V) Switcher
3.8 1.3 0.3
1.45 0.5 0.1
91% 31% 6%
92% 86% 78%
91% 83% 65%
AB+ Switcher
89% 67% 12%
IV. CONCLUSION Three circuit architectures for the power supply in GSM and EDGE PA applications have been described and compared: a hysteretic control switcher, and two linearassisted architectures: LDO+Switcher and AB+Switcher The circuits have been implemented on a single prototype chip in a standard 0.5 µ, 5 V CMOS process and compared by simulation in terms of tracking capabilities and efficiency. It is shown that the three configurations have significantly better efficiency compared to the conventional solution based on a linear regulator only. The configurations differ in terms of efficiency, the size of filtering components, bandwidth, and linearity. ACKNOWLEDGMENT The authors would like to thank colleagues Steve Berg and Jim Doyle at National Semiconductor for their valuable technical inputs.
Figure 8. Simulated waveforms of the LDO+Switcher.
REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9]
[10] [11] [12]
Figure 9. Simulated waveforms of the AB+Switcher.
[13]
Efficiency has been calculated based on the simulations, and the results are listed Table I. In all cases, the proposed schemes have much better efficiency compared to the conventional LDO-only solution. The simulated efficiencies for the polar-EDGE application illustrated by the waveforms of Fig. 9 are: 89%@50KHz and 77% @220KHz.
[14] [15]
[16]
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SKY74076 power amplifier controller, Skyworks Solutions. TimeStar multi-mode polar modulator, Tropian Inc. TQM7M4014 datasheet, Triquint Semiconductor. LM3230/3228 datasheets, National Semiconductor. LM3485 datasheet, National Semiconductor. MAX8560/8561/8562 datasheet, Maxim Integrated Products. N. Schlumpf, M. Declercq and C. Dehollain, “A fast modulator for dynamic supply linear RF Power Amplifier,” IEEEJ. Solid-State Circuit., vol. 39, no. 7, pp. 1015-1025, Jul. 2004. G. R. Walker, “A class B switch-mode assisted linear amplifier,” IEEE Trans.PowerElectron. ,vol.18, no.6, pp.1278-1285, Nov. 2003. A. E. Ginart, R. M. Bass and W. M. Leach Jr., T. G. Habetler , “Analysis of the class ad audio amplifier including hysteresis effects,” IEEE Trans. Power Electron.., vol. 18, no. 2, pp. 679-685, Mar. 2003. R. A. R. van der Zee and E. van Tuijl, “A power-efficient audio amplifier combining switching and linear techniques,” IEEEJ. Solid-State Circuit., vol. 34, no. 7, pp. 985-991, Jul. 1999. N. S. Jung, N. I. Kim and G. H. Cho, “A new high-efficiency and super-fidelity analog amplifier with the aid of digital switching amplifier,” in Proc.29th Annu.IEEE PowerElectronSpec.Conf., 1998. H. Ertl, J. W. Kolar and F. C. Zach, “Basic considerations and topologies of switched-mode assisted linear power amplifiers”, IEEE Trans. Ind, Elecotron., vol. 44, no. 1, pp. 116-123, Feb. 1997. G. B. Yundt, “Series or parallel-connected composite amplifiers,” IEEE Trans. Power Electron. ,vol. PE-1, pp. 48-54, Jan. 1986. LM4901 datasheet, National Semiconductor. R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. Huijsing, “A compact power-efficient 3V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries,” IEEEJ. Solid-State Circuit., vol. 29, no. 12, pp. 1505-1513, Dec. 1994. P. Midya, "Linear switcher combination with novel feedback," IEEE PESC 2000, vol. 3, pp. 1425-1429.
Dragan Maksimovic University of Colorado ECE Dept., Boulder, CO 80309 [email protected]
[email protected]
Abstract—This paper presents and compares three circuit architectures that are promising candidates to efficiently and dynamically supply GSM and EDGE RF power amplifiers in handsets. The candidate architectures include a switcher with hysteretic control, and two linear-assisted switcher configurations. The architectures have been implemented and tested by simulation in a standard 0.5µ, µ, 5V CMOS process. The circuits are compared in terms of efficiency and reference tracking capabilities.
Figure 1. Linear regulator (LDO) as the power supply for an RF power amplifier.
I. INTRODUCTION In TDMA communication systems, such as GSM and EDGE, the power control of the RF power amplifier (PA) output has to meet the required time mask. One way to control the output RF power is through the control of its supply Vcc, as shown in Fig. 1. Assuming the commonly applied single-cell Li-Ion battery source, a linear regulator (“low-drop-out” or LDO) can be used to adjust the supply Vcc for the PA. In this power control architecture, the supply voltage Vcc has to slew from 0 to 3.7 V in 10-20 µs for the full power case (about 2 A), and Vcc has to precisely “track” the Vramp signal (reference) in a close-loop manner. Similar requirements are valid for the ramp down condition. In the GSM and linear EDGE systems, Vcc stays at the constant level (corresponding to certain output power level) during the transmission. In the polar EDGE system, Vcc also has to track the envelope of the modulated RF signal, while the RF input to the PA has constant envelope. An advantage of the polar EDGE system [1-2] is that a nonlinear RF PA can be used to improve its efficiency. Meeting the ramp time mask in GSM or linear EDGE systems requires a substantial slew-rate and bandwidth capability. Tracking the envelope in a polar EDGE system requires much wider bandwidth. A major challenge in practical realizations is to meet the high-bandwidth requirements while preserving the efficiency of the power supply for the RF PA.
II. CANDIDATE ARCHITECTURES A number of power supply architectures have been considered to address the GSM and EDGE PA applications. The following three architectures have been selected as the most promising ones: a hysteretic control switcher for GSM RF PA, and two linear-assisted switcher combinations: LDO+Switcher for the GSM and linear EDGE applications, and AB+Switcher for the polar EDGE application. A. Hysteretic Control Switcher Voltage-mode or current-mode constant-frequency PWM switchers are well known and commonly applied in DC-DC applications, with advantages including relatively small ripples, low conduction losses, and constant switching frequency. However, the wide-bandwidth tracking may require operation at very high switching frequencies, which reduces efficiency because of the switching losses. Switchers with hysteretic controls are also widely used [5-6]. The switching frequency is not constant, and varies adaptively depending on the load demands. The adaptive feature of the switching frequency is desirable for the high bandwidth requirement. Figure 2 shows a simple diagram of this architecture. The architecture has the advantage of relatively simple circuit implementation. The LC filter components are selected to meet the ripple requirements.
In conventional solutions based on an LDO [3-4], as illustrated in Fig. 1, the power supply efficiency is low at reduced power levels, when Vcc is low compared to the battery voltage Vbat. In this paper we describe and compare three alternative circuit architectures to achieve widebandwidth slewing and tracking requirements, while improving the efficiency over the full range of output power levels. Figure 2. Hysteretic control switcher architecture.
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B. LDO+Switcher Linear-assisted switchers are based on the idea of combining wide-bandwidth capabilities of linear regulators with high-efficiency of switching regulators. The “LDO+Switcher” architecture shown in Fig. 3 (similar to [7]) is one such combination. In the LDO+Switcher architecture of Fig. 3, two linear amplifiers are used: a current-sourcing amplifier for fast ramp up, and a current-sinking amplifier for fast ramp down. There is a small offset setup for the linear amplifiers so that they stay off during the steady state when the switcher provides all the load current. At extremely heavy loads, when Vcc is close to Vbat, this architecture also allows for load sharing between the switcher and the sourcing linear amplifier. The switcher can be a high efficiency PWM switcher, which can be synchronized with the system clock to reduce the impact of the switching noise in the receiver band. Low physical profile of this architecture can be realized with low inductance such as 1uH. A disadvantage of this architecture is that the output filter capacitance has to be relatively large to achieve small output voltage ripple. The large output capacitance imposes a challenge in designing the wide-bandwidth linear amplifiers.
Figure 3. LDO+Switcher architecture.
C. AB+Switcher The LDO+Switcher architecture has one important limitation when considered for polar EDGE applications: the linear amplifier output devices would turning on and off in attempting to track the RF envelope. The on-off transients, in combination with the relatively large filter capacitance are practical obstacles in meeting the widebandwidth envelope tracking requirement. An alternative linear-assisted architecture based on a combination of a class-AB linear amplifier and a switcher is considered to overcome this limitation. The “AB+Switcher” architecture is shown in Fig. 4. This kind of architecture has been reported for audio applications [8-13] and for RF envelope tracking [16], but only for relatively low tracking bandwidth. The bandwidth demands in a polar-EDGE application are significantly higher. In the AB+Switcher architecture of Fig. 4, the switcher provides the DC (and low frequency) load current, while the class-AB amplifier provides the high frequency load current while maintaining the tracking loop closed. The switcher is controlled by the output current of the class-AB amplifier.
The hysteretic current controller of the switcher attempts to minimize the output current of the class-AB amplifier, to maximize the overall efficiency. The output capacitance of this architecture is low to maintain the high bandwidth of the class-AB amplifier loop. It is important to note that the ripple current of the switcher has to be largely absorbed by the linear amplifier. Because of this, and because of the quiescent bias current for the class-AB output stage, this architecture is expected to have a lower efficiency compared with the LDO+Switcher architecture.
Figure 4. AB+Switcher architecture.
III. CIRCUIT DESIGN AND SIMULATION RESULTS A. Test Chip for Evaluation of Candidate Architectures In order to evaluate and compare the three different architectures in a practical circuit realization, a single test chip has been designed in a standard 0.5 µ, 5 V CMOS process. In the test chip, several building blocks, such as the large output transistors are re-used for all three architectures, while the control circuitry for each architecture can be individually selected by two programming bits. The circuits are intended to deliver up to 2 A to the RF PA. Each of the four transistors (2 for the switcher and 2 for the class AB amplifier or the LDOs) has the on resistance of about 80 mΩ. When the chip is configured for the particular architecture, all unnecessary blocks for the other architectures are shut down. B. Class-AB Amplifier, LDOs and Comparator The class-AB amplifier [14-15] shown in Fig. 5 has two stages: a folded cascode to provide the high gain, and a railto-rail output stage. The Miller compensation provides the dominant pole for the loop. There are two more nondominant poles: one from the output filter capacitance and one from the first stage input capacitance. The compensation network places a zero near the second pole of the loop to increase the phase margin. The capacitor in the feedback network also places a zero to further help the phase margin. Figure 6 shows the Bode plot of the loop gain. The phase margin is 72 degrees, the cross-over frequency is 8.4MHz, and the gain margin is 24dB. Floating current sources are used for the quiescent current control of the class-AB output stage. The quiescent current is 48mA, of which 47mA is from the output stage. There is a trade-off between the quiescent current and the amplifier linearity especially when the output current crossing over zero. The
1315
Figure 5. Schematic of the class-AB amplifier.
output current (Iab in Fig. 4) is sensed through the current mirrors of the output PMOS and NMOS. The LDO (class B) is a subset of the class-AB amplifier. The sourcing and sinking LDOs in the “LDO+Switcher” circuit are constructed from the class-AB amplifier by removing the output NMOS or PMOS, removed respectively, along with shutting down the quiescent control circuitry. The LDO bias current is about 1mA. Since the output capacitance of the “LDO+Switcher” is much larger than the “AB+Switcher” case, the compensation from proper output capacitor “esr” will help to maintain the good phase margin. The comparator in the hysteretic control switcher has the similar structure as the first gain stage of the class-AB amplifier.
current(s) from LDOs or AB amplifier; (c) error signal VfbVramp, where Vfb is the sensed feedback signal. The signal Vramp is ramped up and down in 10 µs with three steadystate values to represent the different output power levels. For the AB+Switcher architecture, a variable-frequency sinusoidal reference signal (50-220KHz) is instead applied to emulate the EDGE envelope signal. It can be seen that Vcc is able to track Vramp well in all three architectures. The LDO+Switcher shows better tracking than the hysteretic control switcher during the ramp up and ramp down transients. The AB+Switcher configuration can successfully track the 200KHz sinusoidal signal. We observe that the switcher in the linear-assisted LDO+Switcher and AB+Switcher configurations indeed provides the majority of the load current, which is important for high overall efficiency.
Figure 6. Loop gain Bode plot of class-AB amplifier.
C. Simulation Results Figures 7-9 show the waveforms obtained by simulation of the circuit implementations of the three architectures. In the simulations, a 10 µH inductor is used in all cases with 4.2V Vbat. The output filter capacitance is 2.2 µF for the hysteretic control switcher and the LDO+Switcher, and 10 nF for the AB+Switcher configuration. Signals in the waveforms are, from top to bottom: (a) Vcc, Vramp and Vfb overlapped; (b) Inductor current, and
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Figure 7. Simulated waveforms of the hysteretic control switcher.
Iload (mA) 2255 777 156
TABLE I ELECTRICAL EFFICIENCY COMPARISON Vcc Vramp Hyst. LDO+ LDO Switcher (V) (V) Switcher
3.8 1.3 0.3
1.45 0.5 0.1
91% 31% 6%
92% 86% 78%
91% 83% 65%
AB+ Switcher
89% 67% 12%
IV. CONCLUSION Three circuit architectures for the power supply in GSM and EDGE PA applications have been described and compared: a hysteretic control switcher, and two linearassisted architectures: LDO+Switcher and AB+Switcher The circuits have been implemented on a single prototype chip in a standard 0.5 µ, 5 V CMOS process and compared by simulation in terms of tracking capabilities and efficiency. It is shown that the three configurations have significantly better efficiency compared to the conventional solution based on a linear regulator only. The configurations differ in terms of efficiency, the size of filtering components, bandwidth, and linearity. ACKNOWLEDGMENT The authors would like to thank colleagues Steve Berg and Jim Doyle at National Semiconductor for their valuable technical inputs.
Figure 8. Simulated waveforms of the LDO+Switcher.
REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9]
[10] [11] [12]
Figure 9. Simulated waveforms of the AB+Switcher.
[13]
Efficiency has been calculated based on the simulations, and the results are listed Table I. In all cases, the proposed schemes have much better efficiency compared to the conventional LDO-only solution. The simulated efficiencies for the polar-EDGE application illustrated by the waveforms of Fig. 9 are: 89%@50KHz and 77% @220KHz.
[14] [15]
[16]
1317
SKY74076 power amplifier controller, Skyworks Solutions. TimeStar multi-mode polar modulator, Tropian Inc. TQM7M4014 datasheet, Triquint Semiconductor. LM3230/3228 datasheets, National Semiconductor. LM3485 datasheet, National Semiconductor. MAX8560/8561/8562 datasheet, Maxim Integrated Products. N. Schlumpf, M. Declercq and C. Dehollain, “A fast modulator for dynamic supply linear RF Power Amplifier,” IEEEJ. Solid-State Circuit., vol. 39, no. 7, pp. 1015-1025, Jul. 2004. G. R. Walker, “A class B switch-mode assisted linear amplifier,” IEEE Trans.PowerElectron. ,vol.18, no.6, pp.1278-1285, Nov. 2003. A. E. Ginart, R. M. Bass and W. M. Leach Jr., T. G. Habetler , “Analysis of the class ad audio amplifier including hysteresis effects,” IEEE Trans. Power Electron.., vol. 18, no. 2, pp. 679-685, Mar. 2003. R. A. R. van der Zee and E. van Tuijl, “A power-efficient audio amplifier combining switching and linear techniques,” IEEEJ. Solid-State Circuit., vol. 34, no. 7, pp. 985-991, Jul. 1999. N. S. Jung, N. I. Kim and G. H. Cho, “A new high-efficiency and super-fidelity analog amplifier with the aid of digital switching amplifier,” in Proc.29th Annu.IEEE PowerElectronSpec.Conf., 1998. H. Ertl, J. W. Kolar and F. C. Zach, “Basic considerations and topologies of switched-mode assisted linear power amplifiers”, IEEE Trans. Ind, Elecotron., vol. 44, no. 1, pp. 116-123, Feb. 1997. G. B. Yundt, “Series or parallel-connected composite amplifiers,” IEEE Trans. Power Electron. ,vol. PE-1, pp. 48-54, Jan. 1986. LM4901 datasheet, National Semiconductor. R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. Huijsing, “A compact power-efficient 3V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries,” IEEEJ. Solid-State Circuit., vol. 29, no. 12, pp. 1505-1513, Dec. 1994. P. Midya, "Linear switcher combination with novel feedback," IEEE PESC 2000, vol. 3, pp. 1425-1429.
