High Frequency Noise Immune Low-Dropout Regulator and Active ...
Graduate Category: Engineering and Technology Degree Level: Ph.D Abstract ID# 1016
High Frequency Noise Immune Low-Dropout Regulator and Active Loop Filter for a Low Jitter and Power Phase-Locked Loop Gyunam Jeon Faculty Advisor: Yong-Bin Kim, High Performance VLSI Research Laboratory Abstract
Supply Noise Mitigation Techniques
This paper presents high frequency noise immune low dropout (LDO) regulator and active loop filter (ALF) for a low jitter and power phase-locked loop (PLL) on 110nm CMOS technology and with 1V supply voltage. The high frequency noise of supply voltage is regulated by low-dropout (LDO) regulator. Other noises generated by each PLL block are filtered by ALF. Therefore, high frequency noise of the VCO's control voltage is eliminated and stable control voltage decreases PLL jitter. The LDO regulator provides 0.8V output, -83 dB PSRR with PLL load, 0.578mW power consumption, and 99.8% current efficiency with 40mA load current. As a result, the jitter of the PLL with LDO regulator and ALF improves from 44.9ps to 4.6ps.
Simulation Setup and Results
I. Low-Dropout Regulator
Vin Vref M20
EA
MP
Vout_LDO
Vin
M21
CZ
Vref
EA
•
M22 MP
Vout_LDO M21
CZ
M23
• •
Rfb1 •
Error amplifier zero compensation
M23
Rfb1
CL
Error amplifier gain compensation
Rfb2
•
LDO regulator provides a clean power supply voltage to the VCO The compensation stages are cancel out the supply noise A folded cascode amplifier provides high swing (2 2·VDS(sat) < Vout(max)
High Frequency Noise Immune Low-Dropout Regulator and Active Loop Filter for a Low Jitter and Power Phase-Locked Loop Gyunam Jeon Faculty Advisor: Yong-Bin Kim, High Performance VLSI Research Laboratory Abstract
Supply Noise Mitigation Techniques
This paper presents high frequency noise immune low dropout (LDO) regulator and active loop filter (ALF) for a low jitter and power phase-locked loop (PLL) on 110nm CMOS technology and with 1V supply voltage. The high frequency noise of supply voltage is regulated by low-dropout (LDO) regulator. Other noises generated by each PLL block are filtered by ALF. Therefore, high frequency noise of the VCO's control voltage is eliminated and stable control voltage decreases PLL jitter. The LDO regulator provides 0.8V output, -83 dB PSRR with PLL load, 0.578mW power consumption, and 99.8% current efficiency with 40mA load current. As a result, the jitter of the PLL with LDO regulator and ALF improves from 44.9ps to 4.6ps.
Simulation Setup and Results
I. Low-Dropout Regulator
Vin Vref M20
EA
MP
Vout_LDO
Vin
M21
CZ
Vref
EA
•
M22 MP
Vout_LDO M21
CZ
M23
• •
Rfb1 •
Error amplifier zero compensation
M23
Rfb1
CL
Error amplifier gain compensation
Rfb2
•
LDO regulator provides a clean power supply voltage to the VCO The compensation stages are cancel out the supply noise A folded cascode amplifier provides high swing (2 2·VDS(sat) < Vout(max)
