high-speed and wide-tuning-range lc frequency ... - Semantic Scholar
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➡ HIGH-SPEED AND WIDE-TUNING-RANGE LC FREQUENCY DIVIDERS Ken Yamamoto, Takayasu Norimatsu and Minoru Fujishima School of Frontier Sciences, The University of Tokyo 5-1-5-703 Kashiwanoha, Kashiwa, Chiba, 277-8561, Japan the following sections, the concept of the proposed circuit is explained and its fabrication results are discussed.
ABSTRACT Wide tuning-range frequency dividers based on an LC resonator are proposed for high-speed transceivers. The proposed circuit is fabricated using a two-metal and 0.5µm-gate CMOS process and realizes the minimum and the maximum frequencies of 7.74 GHz and 8.16 GHz, respectively, with the power consumption of 2.2 mW at the supply voltage of 0.9 V. To enlarge a tuning range without increasing power consumption, the LC divider with MOS varactors is also fabricated using the same process, where the minimum and the maximum frequencies are 1.49 GHz and 1.97 GHz, respectively, with the power consumption of 0.87 mW at the supply voltage of 1.2 V. Finally, the application to a phaselocked loop of the proposed circuit is described. 1. INTRODUCTION The technology for wireless communications such as a cellular phone, a PHS and a wireless LAN has progressed at a surprising speed. As for a cellular phone, a GSM uses 900 MHz, 1800 MHz and 1900 MHz band, and IMT-2000 will use 2 GHz band. Moreover, a 4G cellular phone will use higher frequency band. On the other hand, a wireless LAN will mainly use 5.2GHz band from now on, while 2.4 GHz band is widely used for the present. As the technology of wireless communications progresses, a higher frequency band tends to be used. As a result, a high-speed frequency synthesizer with a phase-locked loop (PLL) is required. The block diagram of PLL is shown in Fig. 1. In particular, a high-speed frequency divider is important to realize a high-speed PLL. For highspeed operation, the frequency divider utilizing an LC resonator is the most suitable one among various types of frequency dividers [1]-[3] because operating frequency is determined by the resonant frequency [4]. However, a tuning range of the LC divider is generally narrow. Since an operation margin is degraded with narrow tuning range, process variation may cause operation failure. Thus, the tuning range should be sufficiently large. To enhance the tuning range using an LC resonator, we propose a new frequency divider by effectively injecting input voltage. In
0-7803-8251-X/04/$17.00 ©2004 IEEE
2. DIFFERENTIAL INJECTION LOCKING FREQUENCY DIVIDER An injection-locked frequency divider [5] is known as the frequency divider utilizing an LC resonator. The circuit and the conceptual diagram of this divider are shown in Fig. 2. In this circuit, an input transistor is inserted in series with an oscillating circuit and it operates as a frequency divider by modulating an oscillating state. Here, the small signal model cut in half is described in the conceptual diagram, where Gp and C denote a parasitic conductance and capacitance, respectively. In this circuit, an input transistor and cross-coupled transistors comprise a mixer. Since the transconductance of cross-coupled transistors are modulated by input voltage, an oscillation state is modulated. As a result, the modulation is considered indirect and the tuning range cannot be wide. To overcome this problem, we proposed another type of circuit [6] as shown in Fig. 3. In this circuit, a switching transistor, modulating an oscillating state, is inserted between differential outputs. In the conceptual diagram of Fig. 3, the small signal model cut in half is shown. Assume that the self-oscillating frequency of the oscillator and the input frequency are f0 and f1, respectively. When the switch modulating the oscillator is turned off, the voltages of differential outputs become equal by 1/2f0 cycles. When the switch is turned on periodically by 1/f1 cycles, the voltages of differential outputs are equalized at the same time. When f1 is greater than 2f0, the phase of the input voltage leads the phase of the differential outputs. When f1 is smaller than 2f0, the phase of the input voltage lags behind the phase of the differential outputs. Consequently, the output phase is locked by the injected signal and the circuit operates as a divide-by-two prescalar. The relationship between the ac input and the ac differential outputs is shown in Fig. 4. In the proposed circuit, an input signal modulates an oscillation state directly by inserting a switch between differential outputs and the circuit is expected to enlarge a tuning range compared to the conventional circuit. We named it a
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ISCAS 2004
➡
➡ IN
REF
OUT
VCO
UP
Vctrl
PFD
B
A
DN
A
B
OUT IN
Programmable Counter
B
A
time
OUT L p Gp
C -Gm
L p Gp
IN
C -Gm
y2 A
B
Fig. 4 The relationship between ac input voltage and ac output voltage of the DILFD.
Fig. 1 Block diagram of PLL.
OUT
OUT
OUT Lp
Gp
C
-Gm IN
IN
Fig. 2 Circuit diagram and conceptual diagram of the conventional injection-locked divider .
IN
0
OUT IN
Lp
Gp
C
Input Power [dBm]
OUT
Fig. 5 Chip micrograph of the DILFD.
-Gm
Fig. 3 Circuit diagram and conceptual diagram of the differential-injection-locking frequency divider (DILFD).
-10
-20 -26 7.7
8.0
8.2
Operating Frequency [GHz]
Fig. 6 The relationship between input sensitivity and operating frequency at the supply voltage of 0.9 V.
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➡ differential-injection-locking frequency divider (DILFD). 3. MEASUREMENTS AND DISCUSSION The chip micrograph of the proposed circuit is shown in Fig. 5, where a two-metal and 0.5-µm-gate CMOS process is used. The relationship between input sensitivity and operating frequency at the supply voltage of 0.9 V is shown in Fig. 6. The self-oscillating frequency is 3.98 GHz and the minimum and the maximum operating frequencies are 7.74 GHz and 8.16 GHz, respectively with a power consumption of 2.2 mW. The minimum and the maximum operating frequencies as well as the power consumption are shown in Fig. 7 as a function of supply voltage. Assumed that the minimum and the maximum operating frequencies are fmin and fmax, respectively, relative tuning range, fR, is defined as fmax fmin . (1) fR = f max Figure 7 shows the trade-off between fR and power consumption, P. P and fR are 2.2 mW and 5.3%, respectively, at the supply voltage of 0.9 V while they are 5.4 mW and 10.3% at the supply voltage of 1.2 V. In the DILFD, fR increases and is saturated in the end as P increases. To enlarge fR without increasing P, modification of the circuit is required. Here, the relationship between input sensitivity and operating frequency is shown in Fig. 8, where the operating frequency at the minimum input power is double of the self-oscillating frequency. Since the operating frequency of the DILFD varies by changing the self-oscillating frequency, it can be enlarged as shown in Fig. 9. To change the self-oscillating frequency, the capacitance in the LC resonator should be changed. A pair of MOS varactors is adopted for this purpose. The circuit diagram of the DILFD with the MOS varactors is shown in Fig. 10, where the current source is also added to adjust the output dc bias. The chip micrograph of the proposed circuit is shown in Fig. 11, where a two-metal and 0.5µm-gate CMOS process is used. The relationship between input sensitivity and operating frequency is shown in Fig. 12, where a power consumption is 0.87 mW at the supply voltage of 1.2 V when the input voltage of the MOS varactors, Vctrl, varies from 0 V to 1.2 V. By changing Vctrl continuously, the minimum and the maximum operating frequencies of 1.49 GHz and 1.97 GHz are realized, respectively. Next, the application to a PLL of the proposed circuit shown in Fig. 10 is discussed. The tuning range of the first-stage frequency divider with the highest-operating frequency must cover that of a voltage-controlled oscillator (VCO) because the first-stage divider is connected to the VCO as shown in Fig. 1. When the same input voltage Vctrl controls operating frequencies of both
the first-stage divider and the VCO, the operating frequency of the divider can follow the oscillating frequency of the VCO. Namely, the tuning range of the divider can cover that of the VCO if the self-oscillating frequency of the divider is a half of that of a VCO independent of Vctrl. The block diagram of the PLL is shown in Fig. 13. 4. CONCLUSION The differential-injection-locking frequency divider with a wide tuning range is proposed. The circuit realized the minimum and the maximum frequencies of 7.74 GHz and 8.16 GHz, respectively and the power consumption of 2.2 mW at the supply voltage of 0.9 V using a two-metal 0.5µm-gate CMOS process. Moreover, MOS varactors are added to the DILFD to enlarge a tuning range without increasing a power consumption and the test circuit was fabricated using the same process. It realized the minimum and the maximum frequencies of 1.49 GHz and 1.97 GHz, respectively, with the power consumption of 0.87 mW at the supply voltage of 1.2 V by changing the input voltage of the varactors. As the application to a PLL of the proposed circuit is shown, the proposed circuit will be useful to realize a high-frequency PLL. 5. ACKNOWLEDGEMENT The authors would like to thank Mr. Tsuruta of DENSO Corporation for the chip fabrication. 6. REFERENCES [1]. H. Wu and A. Hajimiri, “A 19GHz 0.5mW 0.35µm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement,” ISSCC Digest of Tech. Papers, pp. 412-413, Feb. 2001. [2] R. Betancourt-Zamora, S. Verma and T. Lee, “1GHz and 2.8GHz CMOS Injection-locked Ring Oscillator Prescalers,” VLSI Symposium, pp. 47-50, June 2001. [3] J. Wong, V. Cheung and H. Luong, “A 1V 2.5mW 5.2GHz Frequency Divider in a 0.35µm CMOS Process”, VLSI Symposium, pp. 190-193, June 2002. [4] J. Lee and B. Razavi, “A 40-GHz Frequency Divider in 0.18µm CMOS Technology,” VLSI Symposium, pp. 259-262, June 2003. [5] H. R. Rategh, H. Samavari and T. H. Lee, “A CMOS Frequency Synthesizer with Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver,” IEEE Journal of SolidState Circuits, vol. 35, pp. 780-787, May 2000. [6] K. Yamamoto, T. Norimatsu and M. Fujishima, “1 V 2 GHz CMOS Frequency Divider” IEE Electronics Letters, vol. 39, pp. 1227-1228, Aug. 2003.
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10
fmin
7.3 0.6
0
1.0 Supply Voltage [V]
1.9
Input Power [dBm]
er
8.0
Tuning Range Tuning Range
Input Power [dBm]
17
fmax
Po w
Operating Frequency [GHz]
8.5
Power Consumption [mW]
➡
2 X Self Oscillating Frequency
Operating Frequency [GHz]
Operating Frequency [GHz]
Fig. 7 The minimum and maximum operating frequencies and the power consumption as a function of supply voltage.
2 X Self Oscillating Frequency
Fig. 8 The relationship between input sensitivity and operating frequency .
Fig. 9 The relationship between input sensitivity and operating frequency when self oscillating frequency is changed.
Vctrl
IN OUT
Fig. 11 Chip micrograph of the DILFD with MOS varactors.
Fig. 10 Circuit diagram and of the DILFD with MOS varactors.
Vctrl
Input Power [dBm]
2 0
VCO
REF -10
PFD
OUT
Vctrl
DN
-20 -30
UP
Vctrl = 0 V
Vctrl = 1.2 V
-38 1.4 2.0 Operating Frequency [GHz]
Programmable Counter
Fig. 12 The relationship between input sensitivity and operating frequency at the supply voltage of 1.2 V when the input voltage of MOS varactors, Vctrl, is changed from 0 V to 1.2 V .
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1st divider Fig. 13 Block diagram of PLL with the DILFD.
➡ HIGH-SPEED AND WIDE-TUNING-RANGE LC FREQUENCY DIVIDERS Ken Yamamoto, Takayasu Norimatsu and Minoru Fujishima School of Frontier Sciences, The University of Tokyo 5-1-5-703 Kashiwanoha, Kashiwa, Chiba, 277-8561, Japan the following sections, the concept of the proposed circuit is explained and its fabrication results are discussed.
ABSTRACT Wide tuning-range frequency dividers based on an LC resonator are proposed for high-speed transceivers. The proposed circuit is fabricated using a two-metal and 0.5µm-gate CMOS process and realizes the minimum and the maximum frequencies of 7.74 GHz and 8.16 GHz, respectively, with the power consumption of 2.2 mW at the supply voltage of 0.9 V. To enlarge a tuning range without increasing power consumption, the LC divider with MOS varactors is also fabricated using the same process, where the minimum and the maximum frequencies are 1.49 GHz and 1.97 GHz, respectively, with the power consumption of 0.87 mW at the supply voltage of 1.2 V. Finally, the application to a phaselocked loop of the proposed circuit is described. 1. INTRODUCTION The technology for wireless communications such as a cellular phone, a PHS and a wireless LAN has progressed at a surprising speed. As for a cellular phone, a GSM uses 900 MHz, 1800 MHz and 1900 MHz band, and IMT-2000 will use 2 GHz band. Moreover, a 4G cellular phone will use higher frequency band. On the other hand, a wireless LAN will mainly use 5.2GHz band from now on, while 2.4 GHz band is widely used for the present. As the technology of wireless communications progresses, a higher frequency band tends to be used. As a result, a high-speed frequency synthesizer with a phase-locked loop (PLL) is required. The block diagram of PLL is shown in Fig. 1. In particular, a high-speed frequency divider is important to realize a high-speed PLL. For highspeed operation, the frequency divider utilizing an LC resonator is the most suitable one among various types of frequency dividers [1]-[3] because operating frequency is determined by the resonant frequency [4]. However, a tuning range of the LC divider is generally narrow. Since an operation margin is degraded with narrow tuning range, process variation may cause operation failure. Thus, the tuning range should be sufficiently large. To enhance the tuning range using an LC resonator, we propose a new frequency divider by effectively injecting input voltage. In
0-7803-8251-X/04/$17.00 ©2004 IEEE
2. DIFFERENTIAL INJECTION LOCKING FREQUENCY DIVIDER An injection-locked frequency divider [5] is known as the frequency divider utilizing an LC resonator. The circuit and the conceptual diagram of this divider are shown in Fig. 2. In this circuit, an input transistor is inserted in series with an oscillating circuit and it operates as a frequency divider by modulating an oscillating state. Here, the small signal model cut in half is described in the conceptual diagram, where Gp and C denote a parasitic conductance and capacitance, respectively. In this circuit, an input transistor and cross-coupled transistors comprise a mixer. Since the transconductance of cross-coupled transistors are modulated by input voltage, an oscillation state is modulated. As a result, the modulation is considered indirect and the tuning range cannot be wide. To overcome this problem, we proposed another type of circuit [6] as shown in Fig. 3. In this circuit, a switching transistor, modulating an oscillating state, is inserted between differential outputs. In the conceptual diagram of Fig. 3, the small signal model cut in half is shown. Assume that the self-oscillating frequency of the oscillator and the input frequency are f0 and f1, respectively. When the switch modulating the oscillator is turned off, the voltages of differential outputs become equal by 1/2f0 cycles. When the switch is turned on periodically by 1/f1 cycles, the voltages of differential outputs are equalized at the same time. When f1 is greater than 2f0, the phase of the input voltage leads the phase of the differential outputs. When f1 is smaller than 2f0, the phase of the input voltage lags behind the phase of the differential outputs. Consequently, the output phase is locked by the injected signal and the circuit operates as a divide-by-two prescalar. The relationship between the ac input and the ac differential outputs is shown in Fig. 4. In the proposed circuit, an input signal modulates an oscillation state directly by inserting a switch between differential outputs and the circuit is expected to enlarge a tuning range compared to the conventional circuit. We named it a
IV - 361
ISCAS 2004
➡
➡ IN
REF
OUT
VCO
UP
Vctrl
PFD
B
A
DN
A
B
OUT IN
Programmable Counter
B
A
time
OUT L p Gp
C -Gm
L p Gp
IN
C -Gm
y2 A
B
Fig. 4 The relationship between ac input voltage and ac output voltage of the DILFD.
Fig. 1 Block diagram of PLL.
OUT
OUT
OUT Lp
Gp
C
-Gm IN
IN
Fig. 2 Circuit diagram and conceptual diagram of the conventional injection-locked divider .
IN
0
OUT IN
Lp
Gp
C
Input Power [dBm]
OUT
Fig. 5 Chip micrograph of the DILFD.
-Gm
Fig. 3 Circuit diagram and conceptual diagram of the differential-injection-locking frequency divider (DILFD).
-10
-20 -26 7.7
8.0
8.2
Operating Frequency [GHz]
Fig. 6 The relationship between input sensitivity and operating frequency at the supply voltage of 0.9 V.
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➡
➡ differential-injection-locking frequency divider (DILFD). 3. MEASUREMENTS AND DISCUSSION The chip micrograph of the proposed circuit is shown in Fig. 5, where a two-metal and 0.5-µm-gate CMOS process is used. The relationship between input sensitivity and operating frequency at the supply voltage of 0.9 V is shown in Fig. 6. The self-oscillating frequency is 3.98 GHz and the minimum and the maximum operating frequencies are 7.74 GHz and 8.16 GHz, respectively with a power consumption of 2.2 mW. The minimum and the maximum operating frequencies as well as the power consumption are shown in Fig. 7 as a function of supply voltage. Assumed that the minimum and the maximum operating frequencies are fmin and fmax, respectively, relative tuning range, fR, is defined as fmax fmin . (1) fR = f max Figure 7 shows the trade-off between fR and power consumption, P. P and fR are 2.2 mW and 5.3%, respectively, at the supply voltage of 0.9 V while they are 5.4 mW and 10.3% at the supply voltage of 1.2 V. In the DILFD, fR increases and is saturated in the end as P increases. To enlarge fR without increasing P, modification of the circuit is required. Here, the relationship between input sensitivity and operating frequency is shown in Fig. 8, where the operating frequency at the minimum input power is double of the self-oscillating frequency. Since the operating frequency of the DILFD varies by changing the self-oscillating frequency, it can be enlarged as shown in Fig. 9. To change the self-oscillating frequency, the capacitance in the LC resonator should be changed. A pair of MOS varactors is adopted for this purpose. The circuit diagram of the DILFD with the MOS varactors is shown in Fig. 10, where the current source is also added to adjust the output dc bias. The chip micrograph of the proposed circuit is shown in Fig. 11, where a two-metal and 0.5µm-gate CMOS process is used. The relationship between input sensitivity and operating frequency is shown in Fig. 12, where a power consumption is 0.87 mW at the supply voltage of 1.2 V when the input voltage of the MOS varactors, Vctrl, varies from 0 V to 1.2 V. By changing Vctrl continuously, the minimum and the maximum operating frequencies of 1.49 GHz and 1.97 GHz are realized, respectively. Next, the application to a PLL of the proposed circuit shown in Fig. 10 is discussed. The tuning range of the first-stage frequency divider with the highest-operating frequency must cover that of a voltage-controlled oscillator (VCO) because the first-stage divider is connected to the VCO as shown in Fig. 1. When the same input voltage Vctrl controls operating frequencies of both
the first-stage divider and the VCO, the operating frequency of the divider can follow the oscillating frequency of the VCO. Namely, the tuning range of the divider can cover that of the VCO if the self-oscillating frequency of the divider is a half of that of a VCO independent of Vctrl. The block diagram of the PLL is shown in Fig. 13. 4. CONCLUSION The differential-injection-locking frequency divider with a wide tuning range is proposed. The circuit realized the minimum and the maximum frequencies of 7.74 GHz and 8.16 GHz, respectively and the power consumption of 2.2 mW at the supply voltage of 0.9 V using a two-metal 0.5µm-gate CMOS process. Moreover, MOS varactors are added to the DILFD to enlarge a tuning range without increasing a power consumption and the test circuit was fabricated using the same process. It realized the minimum and the maximum frequencies of 1.49 GHz and 1.97 GHz, respectively, with the power consumption of 0.87 mW at the supply voltage of 1.2 V by changing the input voltage of the varactors. As the application to a PLL of the proposed circuit is shown, the proposed circuit will be useful to realize a high-frequency PLL. 5. ACKNOWLEDGEMENT The authors would like to thank Mr. Tsuruta of DENSO Corporation for the chip fabrication. 6. REFERENCES [1]. H. Wu and A. Hajimiri, “A 19GHz 0.5mW 0.35µm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement,” ISSCC Digest of Tech. Papers, pp. 412-413, Feb. 2001. [2] R. Betancourt-Zamora, S. Verma and T. Lee, “1GHz and 2.8GHz CMOS Injection-locked Ring Oscillator Prescalers,” VLSI Symposium, pp. 47-50, June 2001. [3] J. Wong, V. Cheung and H. Luong, “A 1V 2.5mW 5.2GHz Frequency Divider in a 0.35µm CMOS Process”, VLSI Symposium, pp. 190-193, June 2002. [4] J. Lee and B. Razavi, “A 40-GHz Frequency Divider in 0.18µm CMOS Technology,” VLSI Symposium, pp. 259-262, June 2003. [5] H. R. Rategh, H. Samavari and T. H. Lee, “A CMOS Frequency Synthesizer with Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver,” IEEE Journal of SolidState Circuits, vol. 35, pp. 780-787, May 2000. [6] K. Yamamoto, T. Norimatsu and M. Fujishima, “1 V 2 GHz CMOS Frequency Divider” IEE Electronics Letters, vol. 39, pp. 1227-1228, Aug. 2003.
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➠
10
fmin
7.3 0.6
0
1.0 Supply Voltage [V]
1.9
Input Power [dBm]
er
8.0
Tuning Range Tuning Range
Input Power [dBm]
17
fmax
Po w
Operating Frequency [GHz]
8.5
Power Consumption [mW]
➡
2 X Self Oscillating Frequency
Operating Frequency [GHz]
Operating Frequency [GHz]
Fig. 7 The minimum and maximum operating frequencies and the power consumption as a function of supply voltage.
2 X Self Oscillating Frequency
Fig. 8 The relationship between input sensitivity and operating frequency .
Fig. 9 The relationship between input sensitivity and operating frequency when self oscillating frequency is changed.
Vctrl
IN OUT
Fig. 11 Chip micrograph of the DILFD with MOS varactors.
Fig. 10 Circuit diagram and of the DILFD with MOS varactors.
Vctrl
Input Power [dBm]
2 0
VCO
REF -10
PFD
OUT
Vctrl
DN
-20 -30
UP
Vctrl = 0 V
Vctrl = 1.2 V
-38 1.4 2.0 Operating Frequency [GHz]
Programmable Counter
Fig. 12 The relationship between input sensitivity and operating frequency at the supply voltage of 1.2 V when the input voltage of MOS varactors, Vctrl, is changed from 0 V to 1.2 V .
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1st divider Fig. 13 Block diagram of PLL with the DILFD.
