Hybrid PCM Memory Controller - SLIDEBLAST.COM
Hybrid PCM Memory Controller Sang Muk Lee, Sang Don Kim and Seung Eun Lee* Department of Electronic Engineering Seoul National University of Science and Technology * [email protected] I.
INTRODUCTION
Over the past decade, DRAM has been a main memory in computing system. The new memory technology have been proposed to replace DRAM [1-2], because DRAM technology has limitations. It is well known that PCM (Phase Change Memory) would become one of the most promising memory thanks to low power, fast read performance, and non-volatile properties in the next decade [3]. However, PCM has short lifetime and long write operation time. Alexandre et al. increased a lifetime of PCM and decreased a write operation time in order to use PCM as a main memory [4]. In this paper, we present a hybrid PCM memory controller, which controls SRAM and PCM. The hybrid PCM memory controller was fabricated using Magnachip/Hynix 0.35 um CMOS technology, and verified the functionality of hybrid memory controller chip along with a microprocessor on a FPGA. II. HYBRID PCM MEMORY CONTROLLER A. System Architecture
Fig. 2. Chip Verification Environment III. CHIP IMPLEMENTAION AND RESULTS The PCM Hybrid memory controller was fabricated using Magnachip/Hynix 0.35 um CMOS technology. Figure 2 shows our chip verification environment. The memory controller operates up to 100MHz and provides two mode, which can control the PCM and SRAM. Cortex-M0 on FPGA accesses PCM and SRAM through the hybrid memory controller to verify the functionality of the memory controller. As a result, we verified memory controller such as write, read, erase via the implemented hybrid memory controller chip.
Figure 1 illustrates our system architecture, which includes a microprocessor, the hybrid memory controller and two kinds of memories (PCM and SRAM). Cortex-M0 controls the hybrid memory controller via AMBA bus interface. The hybrid memory controller includes PCM and SRAM controller, which is based on AHB bus interface. This bus interface transmits address, data, and memory control signal from Coretex-M0 to the memory controller.
. Fig. 3. Hybrid Memory Controller Chip Design REFERENCE [1]
[2]
Fig. 1. Hybrid PCM Memory Controller Architecture
[3]
[4]
Sang Don Kim, Yeong Seob Jeong, Ju Seong Lee and Seung Eun Lee, SDRAM Controller for Retention Time Analysis in Low Power Signal Processor, vol.222, Lecture Notes in Electrical Engineering, 2013, pp.335-339 Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie, Energy and Performance Driven Circuit Design for Emerging Phase-Change Memory, Asia and South Pacific Design Automation Conference (ASPDAC), 2010, pp.193–198. Wong, H.-S.P., Raoux S, SangBum Kim, Jiale Liang, Reifenberg John P., Rajendran B., Asheghi Mehdi, E. Goodson Kenneth, Phase Change Memory, Proceedings of the IEEE, Vol.98, 2010, pp.2201-2227 Alexandre P. Ferreira, Miao Zhou, Santiago Bock, Bruce Childres, Rami Melhem and Daniel Mosse, Increasing PCM Main Memory Lifetime, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, pp.914-919.
This work was supported by the IDEC(IC Design Education Center)
-page number-
2009 ISOCC
INTRODUCTION
Over the past decade, DRAM has been a main memory in computing system. The new memory technology have been proposed to replace DRAM [1-2], because DRAM technology has limitations. It is well known that PCM (Phase Change Memory) would become one of the most promising memory thanks to low power, fast read performance, and non-volatile properties in the next decade [3]. However, PCM has short lifetime and long write operation time. Alexandre et al. increased a lifetime of PCM and decreased a write operation time in order to use PCM as a main memory [4]. In this paper, we present a hybrid PCM memory controller, which controls SRAM and PCM. The hybrid PCM memory controller was fabricated using Magnachip/Hynix 0.35 um CMOS technology, and verified the functionality of hybrid memory controller chip along with a microprocessor on a FPGA. II. HYBRID PCM MEMORY CONTROLLER A. System Architecture
Fig. 2. Chip Verification Environment III. CHIP IMPLEMENTAION AND RESULTS The PCM Hybrid memory controller was fabricated using Magnachip/Hynix 0.35 um CMOS technology. Figure 2 shows our chip verification environment. The memory controller operates up to 100MHz and provides two mode, which can control the PCM and SRAM. Cortex-M0 on FPGA accesses PCM and SRAM through the hybrid memory controller to verify the functionality of the memory controller. As a result, we verified memory controller such as write, read, erase via the implemented hybrid memory controller chip.
Figure 1 illustrates our system architecture, which includes a microprocessor, the hybrid memory controller and two kinds of memories (PCM and SRAM). Cortex-M0 controls the hybrid memory controller via AMBA bus interface. The hybrid memory controller includes PCM and SRAM controller, which is based on AHB bus interface. This bus interface transmits address, data, and memory control signal from Coretex-M0 to the memory controller.
. Fig. 3. Hybrid Memory Controller Chip Design REFERENCE [1]
[2]
Fig. 1. Hybrid PCM Memory Controller Architecture
[3]
[4]
Sang Don Kim, Yeong Seob Jeong, Ju Seong Lee and Seung Eun Lee, SDRAM Controller for Retention Time Analysis in Low Power Signal Processor, vol.222, Lecture Notes in Electrical Engineering, 2013, pp.335-339 Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie, Energy and Performance Driven Circuit Design for Emerging Phase-Change Memory, Asia and South Pacific Design Automation Conference (ASPDAC), 2010, pp.193–198. Wong, H.-S.P., Raoux S, SangBum Kim, Jiale Liang, Reifenberg John P., Rajendran B., Asheghi Mehdi, E. Goodson Kenneth, Phase Change Memory, Proceedings of the IEEE, Vol.98, 2010, pp.2201-2227 Alexandre P. Ferreira, Miao Zhou, Santiago Bock, Bruce Childres, Rami Melhem and Daniel Mosse, Increasing PCM Main Memory Lifetime, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010, pp.914-919.
This work was supported by the IDEC(IC Design Education Center)
-page number-
2009 ISOCC
