Impact of pulse quenching effect on soft error ... - Semantic Scholar
Microelectronics Journal 44 (2013) 65–71
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Impact of pulse quenching effect on soft error vulnerabilities in combinational circuits based on standard cells Du Yankang, Chen Shuming n, Liu Biwei School of Computer Science, National University of Defense Technology, Changsha 410073, China
a r t i c l e i n f o
abstract
Article history: Received 14 August 2012 Received in revised form 22 November 2012 Accepted 23 November 2012 Available online 9 January 2013
In this study, we investigated the impact of pulse quenching effect on the soft error vulnerabilities in combinational circuits. Simulation results illustrate that soft error vulnerabilities could be reduced by 4–16% for the benchmark circuits when the pulse quenching effect is introduced. By adjusting the cell orientations of the quenching cells in the layout, the soft error vulnerabilities could be further reduced. It is suggested that new placement algorithm considering circuit reliability should be designed to reduce the circuit soft error vulnerabilities. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Multi-node charge collection Pulse quenching effect Layout
1. Introduction As the technology feature size of integrated circuits (ICs) scales, multi-node charge collection due to a single ion hit has been becoming a great concern [1–6]. It is a significant threat for the redundancy based storage elements used to mitigate single event upset (SEU). And many research works have been done to isolate the sensitive nodes to mitigate this problem [5,7]. However, this situation is complicated in combinational circuits. Fig. 1 presents two inverters that are physically adjacent in a circuit layout. When these two inverters are electrically related, pulse quenching effect could occur due to multi-node charge collection [8]. This would reduce the propagated single event transient (SET) pulse width, which is beneficial to reduce the circuit soft errors [8,9]. However, when these two inverters have no electrical relationship, multiple single event transient (MSET) pulses might appear due to charge sharing. MSET pulses could shrink or enlarge the soft error vulnerabilities, depending on the circuit topology [6,10]. For instance, when the generated MSET pulses converge at one logic cell and partially cancel each other, the SET pulse width at the primary outputs would be reduced [10]. This could lower the soft error vulnerabilities. At present, the design of large scale ICs is mostly based on standard cells. The decreased space between adjacent standard cells in the circuit layout makes multi-node charge collection among different standard cells serious. This would result in a complex effect on the soft error vulnerabilities of the combinational circuits. Multinode charge collection is closely related to the layout placement. Therefore, to introduce layout placement into the soft error analysis would be beneficial to evaluate the circuit reliability accurately.
n
Corresponding author. E-mail address: [email protected] (C. Shuming).
0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2012.11.011
Pagliarini et al. studied the effect of charge sharing among different standard cells on the functional behavior of the entire circuit [6]. However, their research work neglected the pulse quenching effect. The first study on pulse quenching effect revealed that when charge is collected on multiple electrically related transistors, the overall SET pulse width would be reduced partially or completely [8]. And a layout technique that enhances the pulse quenching effect in the two-stage standard cells is proposed to mitigate SET [9]. However, to the best of our knowledge, related works on pulse quenching effect are mainly focused on simple inverter chains or simple logic cells [8,9]. No previous study has introduced pulse quenching effect into the soft errors analysis for large scale ICs. In large combinational circuits, the occurrence of pulse quenching effect due to a single ion hit is determined by many factors, such as the distance between the logic cells, logical state, and ions incident location. An investigation of how much pulse quenching effect could shrink the soft error vulnerabilities would provide circuit designers with a detailed insight into the circuit reliability. In this study, based on a simple model used to analyze the effect of ions incident location on the pulse quenching effect, we introduce the pulse quenching effect into the soft error vulnerabilities analysis for large combinational circuits. And then, an approach to adjust the cell orientations of logic cells is proposed to enhance the pulse quenching effect to further reduce the soft error vulnerabilities.
2. Layout based SET pulse injection considering pulse quenching effect 2.1. Synthesis and placement As the size of devices scales, the distance between standard cells in the circuit layout decreases. This would make multi-node
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1
0
Ions Strike
Ions Strike
Charge Sharing
Charge sharing
1
1
0
SET Pulse width is reduced due to pulse quenching effect
1
0
Multiple SET pulses are generated due to charge sharing
Fig. 1. Circuit response when multi-node charge collection occurs in combinational circuits. (a) Pulse quenching effect and (b) multiple SET pulses.
charge collection among different cells more serious. However, the traditional fault injection approaches just assume that only one fault is caused by one ion hit [11], and the spatial relationship of layout placement is not taken into account. In this study, the layout placement is introduced to evaluate the impact of pulse quenching effect on the soft error vulnerabilities in large combinational circuits. Several electronic design automation (EDA) tools are adopted to determine the layout placement for combinational circuits. First, based on the standard 65 nm Taiwan Semiconductor Manufactory Company (TSMC) design library, the Synopsys design compiler (DC) is used to synthesize the circuits and produce the mapped gate-level netlists. The synthesis process is optimized for area and the delay from all inputs to all outputs is set to 2 ns. In this 65 nm TSMC design library, the minimum width for the PMOS transistor is 370 nm and the minimum width for the NMOS transistor is 270 nm. Logic cells using the minimum width of PMOS transistors and NMOS transistors are called x0 drive strength cells. Each logic cell has several different drive strengths in this design library, but we just use the cells with x0 drive strength in this study. The benchmark circuits are chosen from the ISCAS’85 suite. Pulse quenching effect could occur within multi-stage standard cells (e.g. AND, OR and XOR) or among different standard cells. Here, we focus on the evaluation of the pulse quenching effect among different standard cells. Therefore, only the three basic cells (NAND2, NOR and INV) are permitted during the synthesis process. This would lead to an area penalty, as presented in Table 1. Then, floorplanning, placement and routing are performed using Cadence Encounter tool to produce a final layout placement. During the placement process, we adopt the double-back rows mode, in which VDD and GND are shared by adjacent wells. The generated layout is saved in a design exchange format (DEF) file. In this study, the electrically related and physically adjacent cells in the circuit layout are termed quenching cells. And the cells that could quench the SET pulse width are called the passive quenching cells. To obtain the quenching cells in the layout placement, a C script is implemented to parse the DEF file. As presented in Fig. 2, PMOS transistor A in the off-state is assumed to be struck normally. Because charge sharing is most likely to occur in the same well, the PMOS transistors B and C in the off state would collect charge whereas the NMOS transistors in the p-well would collect little charge. The PMOS transistor D is electrically related to transistor A, and the pulse quenching effect could occur under this situation. The implemented layout tool would record the two logic cells containing transistors A and D as the quenching cells. And the logic cell containing transistor D is recorded as the passive quenching cell. After parsing the DEF file, all the quenching cells and their position in the layout placement are extracted.
Table 1 Area comparison for synthesis using two different sets of standard cells. Benchmark circuits
C1908 C2670 C3540 C432 C499 C5315 C6288 C7552
Area (lm2)
Area penalty (%)
All cells
Three basic cells
575.6 1107.2 1647.6 298 568 2375.6 4842.8 2710.8
714.8 1230 1741.6 298 795.2 2595.2 5107.2 3170.8
24.2 11.1 5.8 0 40 9.2 5.5 17
Fig. 2. Multi-node charge collection analysis for the circuit layout.
2.2. Modeling the effect of Ions incident location on pulse quenching effect Because pulse quenching effect is closely related to the distance between the ions incident location and the passive quenching cells in the layout, a simple model based on linear interpolation is proposed to model the impact of ions incident location on the pulse quenching effect. In our study, the large combinational circuits are assumed to be struck normally. As the transistor size and location are given for a certain standard cell, we suppose that the SET pulse width reduced by the pulse quenching effect is mainly determined by the distance between the ions incident location and the sensitive areas of the passive quenching cells. To simplify the analysis, it is assumed the charge collected by a certain node is not affected by
D. Yankang et al. / Microelectronics Journal 44 (2013) 65–71
Heavy Ions
OTHER INPUTS
INPUTS
produce the SET pulse, and this cell has little effect on the quenching ability of the studied INV cell. During the simulation, the ions would strike at the drain center of the INV cell as presented in Fig. 3. The distance between the ion strike location and the drain center of the studied INV cell is varied. The PWquenched, which is the SET pulse width quenched by the studied INV cell, could be expressed as PW quenched ¼ PW 1 2PW 2
CASE 1 CASE 2
350 300 250 200 150 100 50 0 -50 0.2
LOGIC CELL1
Y1
LOGIC CELL2
0.5
0.6
0.7
0.8
0.9
1.0
Fig. 5. Effect of distance from the ions incident location to the drain center of the INV cell on the quenched SET pulse width.
VDD
VDD
D
0.4
Distance from Ions Strike Location to Drain Center of the Studied INV Cell (um)
The Studied Device
S
0.3
Y2
Fig. 3. Quenching cells in the circuit layout.
The Device Used To Generate SET Pulse
ð1Þ
In this equation, PW1 is the SET pulse width at the output of the device used to produce the SET pulse and PW2 is the SET pulse width at the output of the studied INV cell. The simulated minimal distance between the ion hit location and the drain center of the studied INV cell is set according to the minimal transistor–transistor space of the 65 nm TSMC layout rules. The distance is then increased in steps of 0.1 mm until the quenched SET pulse width reaches 0. The LET of the ions is 30 MeV cm2/mg. Fig. 5 shows the effect of distance between the strike location and drain center of the studied INV cell on the quenched SET pulse width. This figure illustrates that the SET pulse width quenched by the studied INV cell is reduced as the distance from the ions incident location to the drain center of this INV cell increases. As the SET pulse width produced by the INV cell is 350 ps, it could be obtained that the SET pulse could be significantly reduced when the distance from the ions incident location to the drain center of this studied INV is small. The data obtained from the TCAD simulation are saved in twodimensional look-up tables. The effect of ions incident location on the pulse quenching effect is then evaluated via a simple linear interpolation of the TCAD results shown in Fig. 5. To validate this simple model, the linear interpolation results are compared to the results obtained by the three-dimensional TCAD simulation.
Quenched SET Pulse Width (ps)
other nodes when multiple nodes collect charge simultaneously due to a single particle strike. Three-dimensional technology computer-aided design (TCAD) numerical simulation is adopted to model the effect of ions incident location on the pulse quenching effect. Sentaurus TCAD from Synopsys is used for this part of the study. TCAD models are constructed according to the layout information in the 65 nm TSMC design library. The strip n-well contact with a width of 0.15 mm is used during the simulation. The distance between the n-well contact and the active area edge of the PMOS transistors is 0.5 mm. During the simulation, the LET value is assumed to be constant along the heavy ion track. The length and radius of the ion track are 5 mm and 0.05 mm, respectively. The following physical models are used: (1) Fermi–Dirac statistics; (2) band-gap narrowing effect; (3) doping-dependent SRH recombination and Auger recombination; (4) temperature, doping, electric field, and carrier–carrier-scattering impact on mobility; (5) incident heavy ions are modeled using a Gaussian radial profile with a characteristic 1/e radius of 0.1 m and a Gaussian temporal profile with a characteristic decay time of 0.25 ps; and (6) a hydrodynamic model is used for carrier transportation. Unless otherwise specified, the default models and parameters provided by Sentaurus TCAD vE-2010.12 are used. As presented in Fig. 3, logic cell1 and logic cell2 are assumed to be quenching cells, and the latter is the passive quenching cell. It is assumed that the PMOS transistors are in the off state in logic cell1. One SET pulse could appear at node Y1 when ions strike the PMOS transistors in logic cell1. Due to the pulse quenching effect, the SET pulse width at node Y2 could be reduced compared to that at node Y1. The ability of logic cell2 to reduce the SET pulse width is related to the amount of charge collected by its sensitive area, which is mainly determined by the distance between this area and the ions incident location. Because charge sharing is more pronounced in PMOS transistors in typical twin-well technology due to the parasitic bipolar effect [1,12], the PMOS transistors in the logic cells are mainly studied in our study. Fig. 4 shows the devices used to simulate the effect of ions incident location on the pulse quenching effect for the INV cell. Two different INV cell orientations are considered. Another INV electrically related to this studied INV cell is used to
67
D
Ions Incident Location Distance Between Ions Hit Location and Drain Center
S
The Device Used To Generate SET Pulse
The Studied Device
VDD
S
VDD
D
Ions Incident Location
S
D
Distance Between Ions Hit Location and Drain Center
Fig. 4. Devices used to simulate the effect of ions incident location on the pulse quenching effect for the INV cell. (a) CASE1 and (b) CASE2.
D. Yankang et al. / Microelectronics Journal 44 (2013) 65–71
Quenched SET Pulse Width (ps)
68
If the SET pulse at gate i could propagate to the primary outputs, the value of Ei(j) would be calculated by Eq. (3). Otherwise, the value of Ei(j) is equal to 0. Having obtained the soft error vulnerabilities of an individual gate, the soft error vulnerabilities of the whole circuit could be calculated by summing up the soft error vulnerabilities of each gate [13–16]. As presented in Eq. (4), CircuitSEVF represents the total circuit SEVF. X CircuitSEVF ¼ GateSEVF i ð4Þ
TCAD Proposed Model
300 280 260 240 220
i
200 0.35
0.40
0.45
0.50
CircuitSEVF is thus used as a metric to evaluate the soft error vulnerabilities of combinational circuits. Fig. 7 shows the whole process for evaluating the soft error vulnerabilities with consideration of the pulse quenching effect in combinational circuits.
0.55
Distance from Ions Incident Location to Drain Center of INV Cell (um) Fig. 6. Simulation results using the proposed model and the three-dimensional TCAD model.
4. Simulation results and discussion The distance between the ions strike location and the drain center of the studied INV cell is set to 0.35 mm, 0.45 mm and 0.55 mm. The placement direction for CASE1 presented in Fig. 4 is used. The simulation results shown in Fig. 6 indicate that this simple model conforms well to the TCAD simulation results. Similar simulations are also carried out for the other standard cells to determine their quenching ability and all TCAD simulation data are saved in two-dimensional look-up tables.
4.1. Impact of pulse quenching effect on the soft error vulnerabilities Before evaluating the circuit soft error vulnerabilities, we investigate the proportion of quenching cells in the circuit layout. Here, the electrically related cells are considered to be the two cells that have an electrical relationship in the circuit. Because the quenching cells are also the electrically related cells, the number of quenching cells is compared to the total number of electrically related cells in the circuits. The data in Table 2 show that the quenching cells account for a large proportion (approx. one-third)
3. Soft error vulnerabilities evaluation method Verilog Netlist
To evaluate the soft error vulnerabilities of the combinational circuits, the soft error vulnerabilities factor (SEVF), which is based on the probability of failure estimation model [13], is proposed in this paper. For each random input vector, the output value of each gate, one at a time, is injected into a single SET pulse. And the GateSEVFi, which is the SEVF of gate i, could be calculated by formula GateSEVF i ¼
1X P nEiðjÞ iðjÞ iðjÞ K
PWðt setup þ t hold Þ T clk
ð3Þ
Standard Cells
Synthesis Netlist
Quenching Ability of Logic Cells
Ploorplanning, Placement&Routing
ð2Þ
In the Eq. (2), K is the number of simulated input vectors. Pi(j) is the probability that gate i generates an SET pulse under input vector j when the drain area of gate i is struck, and Ei(j) is the probability that the generated SET pulse propagates to the circuit primary outputs or is latched under input vector j. To evaluate the soft error rates of combinational circuit, the drain area is usually taken as the sensitive area for transistors [13–18]. Here, we focus on the case where the drain area is hit by ions. Therefore, the value of Pi(j) is equal to the ratio of the area of sensitive drain area of gate i to the whole circuit area. Three masking effects (logical, electrical and latch-window masking effect) in combination circuits [14] are all considered to calculate Ei(j). Applying the depth first search (DFS) algorithm, the logical masking effect is used to extract all the paths from the gate i to the primary outputs under input vector j [19]. Then the SET pulse at gate i is propagated in the topological order using the electrical masking model proposed by Wang and Xie [15]. For the latch-window masking effect, the model presented in reference [16] is used. As presented in Eq. (3), P is the probability of the SET pulse at the primary outputs being latched. PW is the width of the SET pulse at the primary outputs. tsetup and thold are the setup and hold time of the flip-flops. And Tclk is the clock period. P¼
Design Compiler Systhensis
Layout DEF File Soft Error Vulnerabilities Analysis Tool Layout Analysis Tool
Soft Error Vulnerabilities Factor
Quenching Cells
Fig. 7. Process for introducing the pulse quenching effect into the evaluation of soft error vulnerabilities.
Table 2 Proportion of quenching cells in the layout placement for various benchmark circuits. Benchmark circuits
Total electrically related cells
Total Taken-up quenching cells proportion (%)
C1908 C2670 C3540 C432 C499 C5315 C6288 C7552
449 732 1117 191 501 1623 3421 2053
146 282 351 59 169 500 1271 655
32.5 38.5 31.4 30.9 33.7 30.8 37.1 31.9
D. Yankang et al. / Microelectronics Journal 44 (2013) 65–71
of the total electrically related cells. This investigation illustrates the prominence of the pulse quenching effect in the combinational circuits. For this simulation, the clock period is set to 400 MHz and the sum of the setup and hold time for the flip-flops is set to 60 ps. The incident ions with a LET of 30 MeV cm2/mg are assumed to strike the whole combinational circuits normally. The situation in which the drain areas are struck is especially studied. Piecewise linear (PWL) is used to characterize the injected SET pulse. For each random input vector, the output value of each gate, one at a time, is injected into a single SET pulse according to the output state of logic cells. When the output of one logic cell is HIGH, the NMOS transistors are sensitive and a negative SET pulse would be injected at the output of this logic cell. When the output of one logic cell is LOW, the PMOS transistors are sensitive and a positive SET pulse would be injected at the output of this logic cell. The injected SET pulse width is set according to the TCAD simulations. As the pulse quenching effect is not prominent in NMOS transistor in typical twin-well technology, the pulse quenching effect is not considered for the NMOS transistors. During the simulation, cases with and without the pulse quenching effect are considered. In both cases, the SET pulse is injected at the output of the directly hit node. For the case where pulse quenching effect is considered, the pulse width at the output of the passive quenching cells would be quenched. And the quenched pulse width is set according to the model proposed in Section 2.2. CircuitSEVF is then calculated for both cases. About 10,000 random input vectors are simulated. Table 3 presents the simulation results. As shown, when pulse quenching effect is introduced, the circuit soft error vulnerabilities factor could be reduced by 4–16% compared to the case Table 3 CircuitSEVF for different benchmark circuits with and without consideration of pulse quenching effect. Benchmark Circuits
CircuitSEVF
C1908 C2670 C3540 C432 C499 C5315 C6288 C7552
No Quenching
With Quenching
1.33E-03 8.51E-04 9.28E-04 5.13E-04 6.57E-04 7.79E-04 3.61E-03 1.16E-03
1.21E-03 7.15E-04 8.67E-04 4.93E-04 6.20E-04 7.38E-04 3.44E-03 1.09E-03
without considering pulse quenching effect for different benchmark circuit. For an in-depth analysis of the impact of pulse quenching effect on the soft error vulnerabilities, the SET pulse width distribution at
VDD
S
PMOS
NMOS
D
D
D
D
S
NMOS
S
VSS
VSS
Fig. 9. Two different cell orientations for the INV cell.
VDD
D
S
S
VDD
S
D
D
S
VDD
VDD
S
VDD
VDD
D
D
S
D
Fig. 10. Adjustment of cell orientations to enhance the pulse quenching effect.
Table 4 CircuitSEVF for different benchmark circuits when the layout is optimized.
Reduction in CircuitSEVF (%)
Benchmark Circuits
9.02 16.0 6.57 3.9 5.63 5.26 4.71 6.03
C1908 C2670 C3540 C432 C499 C5315 C6288 C7552
0.35
CircuitSEVF No Quenching
Optimized
Reduction in CircuitSEVF (%)
1.33E-03 8.51E-04 9.28E-04 5.13E-04 6.57E-04 7.79E-04 3.61E-03 1.16E-03
1.10E-03 6.68E-04 7.91E-04 4.35E-04 5.68E-04 6.71E-04 3.24E-03 1.02E-03
17.3 21.5 14.8 15.2 13.5 13.9 10.2 12.1
No_Quenching With_Quenching
0.30
0.25 0.20
Proportion
Proportion
VDD
PMOS
S
No_Quenching With_Quenching
0.30
69
0.15
0.25 0.20 0.15
0.10
0.10 0.05
0.05
0.00 0
10
0-
0 0 0 0 0 0 0 0 0 0 0 0 0 12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 360 0 0 0 0 0 0 0 0 0 0 0 0 28 30 32 34 12 14 16 18 20 22 24 26
1
00
SET Pulse Width (ps)
0.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 12 16 14 28 30 32 34 18 20 22 36 360 24 26 0- 00- 20- 40- 60- 80- 00- 20- 40- 60- 80- 00- 20- 401 1 1 2 2 2 2 3 3 1 1 3 2
SET Pulse Width (ps)
Fig. 8. SET pulse width distribution for the C1908 and C2670 circuits. (a) C1908 and (b) C2670.
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D. Yankang et al. / Microelectronics Journal 44 (2013) 65–71
Proportion
0.25
No_Quenching With_Quenching Optimization
No_Quenching With_Quenching Optimization
0.35 0.30
Proportion
0.30
0.20 0.15
0.25 0.20 0.15
0.10 0.10
0.05
0.05 0.00
0.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 360 0- 00- 20- 40- 60- 80- 00- 20- 40- 60- 80- 00- 20- 403 2 1 1 1 3 1 3 2 2 2 2 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 360 0 0 0 0 0 0 0 0 0 0 0 0 0 10 12 16 18 20 14 22 24 26 28 30 32 34
0-
SET Pulse Width (ps)
SET Pulse Width (ps)
Fig. 11. SET pulse width distribution for the C1908 and C2670 circuits after layout optimization. (a) C1908 and (b) C2670.
the primary outputs of circuits C1908 and C2670 is plotted in Fig. 8. As shown, when taking pulse quenching effect into consideration, the SET pulses with large pulse widths are reduced. And more SET pulses with short pulse widths appear. The reason is that when the pulse quenching effect is considered, the SET pulse width at the output of the passive quenching cells would be reduced compared to the SET pulse width at the output of the directly hit node. This would result in the reduction of SET pulse width at the primary outputs of the circuits. 4.2. Ideal optimized method to adjust the cell orientations As known, the cell orientation of each logic cell could be different. Fig. 9 presents two cell orientations for the INV cell. The ability of passive quenching cells to quench the SET pulse width is related to the distance from the ions incident location to the sensitive areas of the passive quenching cells. Different cell orientations would result in different distances. Minimization of this distance would beneficial to enhance the pulse quenching effect. In this study, an ideal optimized approach is proposed to adjust the cell orientations of the quenching cells to enhance the pulse quenching effect. Fig. 10 shows the PMOS transistors placement for two INV quenching cells. Fig. 10(a) presents two bad cell orientations that are unfavorable to the pulse quenching effect. The distance between the drain areas of these two PMOS transistors is not minimized. To enhance the pulse quenching effect, the drain areas of these two PMOS transistors are placed back-to-back as presented in Fig. 10(b). By using this placement, the passive quenching cells could collect as much charge as possible to quench the generated SET pulse width. As the NAND cell has a symmetric PMOS layout with the shared drain in the center, it would not be affected by this optimized approach. This approach is primarily aimed at the INV and NOR cells. To implement this optimized approach, the cell orientation parameter of the quenching cells in the DEF file obtained in Section 2.1 is modified. The modified principle is to minimize the distance between the drain areas of the quenching cells. Simulations similar to that described in Section 4.1 are conducted to calculate the circuit soft error vulnerabilities. The simulation results presented in Table 4 illustrate that soft error vulnerabilities are further reduced. More SET pulses with short pulse widths appear at the primary outputs due to the enhanced pulse quenching effect as presented in Fig. 11. As discussed, the layout placement could significantly affect the soft error vulnerabilities at advanced technologies. It would
be very promising to introduce the circuit reliability into the placement and routing algorithm.
5. Conclusion In this study, the impact of pulse quenching effect on the soft error vulnerabilities in large combinational circuits is investigated. Simulation results indicate that the soft error vulnerabilities could be reduced by 4–16% when pulse quenching effect is introduced. To enhance the pulse quenching effect, an ideal optimized approach is proposed for adjusting the cell orientations of the quenching cells in the circuit layout. The soft error vulnerabilities could be further reduced using this approach. As technology scales, the multi-node charge collection is becoming more prevalent. Introducing the layout placement into the soft error analysis would give the circuit designers a detailed insight into the circuit reliability. And new placement algorithms considering the circuit reliability would be promising in the future.
Acknowledgment This work is supported by the State Key Program of National Natural Science Foundation of China (Grant no. 60836004), National Natural Science Foundation of China (Grant nos. 61006070, 60906014) and Hunan Provincial Innovation Foundation for Postgraduate, China (Grant no. CX2012B028). References [1] O.A. Amusan, A.L. Witulski, L.W. Massengill, et al., Charge collection and charge sharing in a 130 nm CMOS technology, IEEE Trans. Nucl. Sci. 53 (6) (2006) 3253–3258. [2] J.R. Ahlbin, M.J. Gadlage, N.M. Atkinson, et al., Effect of multiple-transistor charge collection on single-event transient pulse widths, in: Proceedings of the IEEE International Reliability Physics Symposium (IRPS), May 2010, pp. 198–201. [3] V.B. Sheshadri, B.L. Bhuva, R.A. Reed, et al., Effects of multi-node charge collection in flip-flop designs at advanced technology nodes, in: Proceedings of the IEEE International Reliability Physics Symposium (IRPS), May, 2010, pp. 1026–1030. [4] T. Uemura, Y. Tosaka, H. Matsuyama, et al., SEILA: soft error immune latch for mitigating multi-node-SEU and local-clock-SET, in: Proceedings of the IEEE International Reliability Physics Symposium (IRPS), May, 2010, pp. 218–223. [5] R. Harada, Y. Mitsuyama, M. Hashimoto, et al., Neutron induced single event multiple transients with voltage scaling and body biasing, in: Proceedings of the IEEE International Reliability Physics Symposium (IRPS), April, 2011, pp. 253–257.
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Impact of pulse quenching effect on soft error vulnerabilities in combinational circuits based on standard cells Du Yankang, Chen Shuming n, Liu Biwei School of Computer Science, National University of Defense Technology, Changsha 410073, China
a r t i c l e i n f o
abstract
Article history: Received 14 August 2012 Received in revised form 22 November 2012 Accepted 23 November 2012 Available online 9 January 2013
In this study, we investigated the impact of pulse quenching effect on the soft error vulnerabilities in combinational circuits. Simulation results illustrate that soft error vulnerabilities could be reduced by 4–16% for the benchmark circuits when the pulse quenching effect is introduced. By adjusting the cell orientations of the quenching cells in the layout, the soft error vulnerabilities could be further reduced. It is suggested that new placement algorithm considering circuit reliability should be designed to reduce the circuit soft error vulnerabilities. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Multi-node charge collection Pulse quenching effect Layout
1. Introduction As the technology feature size of integrated circuits (ICs) scales, multi-node charge collection due to a single ion hit has been becoming a great concern [1–6]. It is a significant threat for the redundancy based storage elements used to mitigate single event upset (SEU). And many research works have been done to isolate the sensitive nodes to mitigate this problem [5,7]. However, this situation is complicated in combinational circuits. Fig. 1 presents two inverters that are physically adjacent in a circuit layout. When these two inverters are electrically related, pulse quenching effect could occur due to multi-node charge collection [8]. This would reduce the propagated single event transient (SET) pulse width, which is beneficial to reduce the circuit soft errors [8,9]. However, when these two inverters have no electrical relationship, multiple single event transient (MSET) pulses might appear due to charge sharing. MSET pulses could shrink or enlarge the soft error vulnerabilities, depending on the circuit topology [6,10]. For instance, when the generated MSET pulses converge at one logic cell and partially cancel each other, the SET pulse width at the primary outputs would be reduced [10]. This could lower the soft error vulnerabilities. At present, the design of large scale ICs is mostly based on standard cells. The decreased space between adjacent standard cells in the circuit layout makes multi-node charge collection among different standard cells serious. This would result in a complex effect on the soft error vulnerabilities of the combinational circuits. Multinode charge collection is closely related to the layout placement. Therefore, to introduce layout placement into the soft error analysis would be beneficial to evaluate the circuit reliability accurately.
n
Corresponding author. E-mail address: [email protected] (C. Shuming).
0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2012.11.011
Pagliarini et al. studied the effect of charge sharing among different standard cells on the functional behavior of the entire circuit [6]. However, their research work neglected the pulse quenching effect. The first study on pulse quenching effect revealed that when charge is collected on multiple electrically related transistors, the overall SET pulse width would be reduced partially or completely [8]. And a layout technique that enhances the pulse quenching effect in the two-stage standard cells is proposed to mitigate SET [9]. However, to the best of our knowledge, related works on pulse quenching effect are mainly focused on simple inverter chains or simple logic cells [8,9]. No previous study has introduced pulse quenching effect into the soft errors analysis for large scale ICs. In large combinational circuits, the occurrence of pulse quenching effect due to a single ion hit is determined by many factors, such as the distance between the logic cells, logical state, and ions incident location. An investigation of how much pulse quenching effect could shrink the soft error vulnerabilities would provide circuit designers with a detailed insight into the circuit reliability. In this study, based on a simple model used to analyze the effect of ions incident location on the pulse quenching effect, we introduce the pulse quenching effect into the soft error vulnerabilities analysis for large combinational circuits. And then, an approach to adjust the cell orientations of logic cells is proposed to enhance the pulse quenching effect to further reduce the soft error vulnerabilities.
2. Layout based SET pulse injection considering pulse quenching effect 2.1. Synthesis and placement As the size of devices scales, the distance between standard cells in the circuit layout decreases. This would make multi-node
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1
0
Ions Strike
Ions Strike
Charge Sharing
Charge sharing
1
1
0
SET Pulse width is reduced due to pulse quenching effect
1
0
Multiple SET pulses are generated due to charge sharing
Fig. 1. Circuit response when multi-node charge collection occurs in combinational circuits. (a) Pulse quenching effect and (b) multiple SET pulses.
charge collection among different cells more serious. However, the traditional fault injection approaches just assume that only one fault is caused by one ion hit [11], and the spatial relationship of layout placement is not taken into account. In this study, the layout placement is introduced to evaluate the impact of pulse quenching effect on the soft error vulnerabilities in large combinational circuits. Several electronic design automation (EDA) tools are adopted to determine the layout placement for combinational circuits. First, based on the standard 65 nm Taiwan Semiconductor Manufactory Company (TSMC) design library, the Synopsys design compiler (DC) is used to synthesize the circuits and produce the mapped gate-level netlists. The synthesis process is optimized for area and the delay from all inputs to all outputs is set to 2 ns. In this 65 nm TSMC design library, the minimum width for the PMOS transistor is 370 nm and the minimum width for the NMOS transistor is 270 nm. Logic cells using the minimum width of PMOS transistors and NMOS transistors are called x0 drive strength cells. Each logic cell has several different drive strengths in this design library, but we just use the cells with x0 drive strength in this study. The benchmark circuits are chosen from the ISCAS’85 suite. Pulse quenching effect could occur within multi-stage standard cells (e.g. AND, OR and XOR) or among different standard cells. Here, we focus on the evaluation of the pulse quenching effect among different standard cells. Therefore, only the three basic cells (NAND2, NOR and INV) are permitted during the synthesis process. This would lead to an area penalty, as presented in Table 1. Then, floorplanning, placement and routing are performed using Cadence Encounter tool to produce a final layout placement. During the placement process, we adopt the double-back rows mode, in which VDD and GND are shared by adjacent wells. The generated layout is saved in a design exchange format (DEF) file. In this study, the electrically related and physically adjacent cells in the circuit layout are termed quenching cells. And the cells that could quench the SET pulse width are called the passive quenching cells. To obtain the quenching cells in the layout placement, a C script is implemented to parse the DEF file. As presented in Fig. 2, PMOS transistor A in the off-state is assumed to be struck normally. Because charge sharing is most likely to occur in the same well, the PMOS transistors B and C in the off state would collect charge whereas the NMOS transistors in the p-well would collect little charge. The PMOS transistor D is electrically related to transistor A, and the pulse quenching effect could occur under this situation. The implemented layout tool would record the two logic cells containing transistors A and D as the quenching cells. And the logic cell containing transistor D is recorded as the passive quenching cell. After parsing the DEF file, all the quenching cells and their position in the layout placement are extracted.
Table 1 Area comparison for synthesis using two different sets of standard cells. Benchmark circuits
C1908 C2670 C3540 C432 C499 C5315 C6288 C7552
Area (lm2)
Area penalty (%)
All cells
Three basic cells
575.6 1107.2 1647.6 298 568 2375.6 4842.8 2710.8
714.8 1230 1741.6 298 795.2 2595.2 5107.2 3170.8
24.2 11.1 5.8 0 40 9.2 5.5 17
Fig. 2. Multi-node charge collection analysis for the circuit layout.
2.2. Modeling the effect of Ions incident location on pulse quenching effect Because pulse quenching effect is closely related to the distance between the ions incident location and the passive quenching cells in the layout, a simple model based on linear interpolation is proposed to model the impact of ions incident location on the pulse quenching effect. In our study, the large combinational circuits are assumed to be struck normally. As the transistor size and location are given for a certain standard cell, we suppose that the SET pulse width reduced by the pulse quenching effect is mainly determined by the distance between the ions incident location and the sensitive areas of the passive quenching cells. To simplify the analysis, it is assumed the charge collected by a certain node is not affected by
D. Yankang et al. / Microelectronics Journal 44 (2013) 65–71
Heavy Ions
OTHER INPUTS
INPUTS
produce the SET pulse, and this cell has little effect on the quenching ability of the studied INV cell. During the simulation, the ions would strike at the drain center of the INV cell as presented in Fig. 3. The distance between the ion strike location and the drain center of the studied INV cell is varied. The PWquenched, which is the SET pulse width quenched by the studied INV cell, could be expressed as PW quenched ¼ PW 1 2PW 2
CASE 1 CASE 2
350 300 250 200 150 100 50 0 -50 0.2
LOGIC CELL1
Y1
LOGIC CELL2
0.5
0.6
0.7
0.8
0.9
1.0
Fig. 5. Effect of distance from the ions incident location to the drain center of the INV cell on the quenched SET pulse width.
VDD
VDD
D
0.4
Distance from Ions Strike Location to Drain Center of the Studied INV Cell (um)
The Studied Device
S
0.3
Y2
Fig. 3. Quenching cells in the circuit layout.
The Device Used To Generate SET Pulse
ð1Þ
In this equation, PW1 is the SET pulse width at the output of the device used to produce the SET pulse and PW2 is the SET pulse width at the output of the studied INV cell. The simulated minimal distance between the ion hit location and the drain center of the studied INV cell is set according to the minimal transistor–transistor space of the 65 nm TSMC layout rules. The distance is then increased in steps of 0.1 mm until the quenched SET pulse width reaches 0. The LET of the ions is 30 MeV cm2/mg. Fig. 5 shows the effect of distance between the strike location and drain center of the studied INV cell on the quenched SET pulse width. This figure illustrates that the SET pulse width quenched by the studied INV cell is reduced as the distance from the ions incident location to the drain center of this INV cell increases. As the SET pulse width produced by the INV cell is 350 ps, it could be obtained that the SET pulse could be significantly reduced when the distance from the ions incident location to the drain center of this studied INV is small. The data obtained from the TCAD simulation are saved in twodimensional look-up tables. The effect of ions incident location on the pulse quenching effect is then evaluated via a simple linear interpolation of the TCAD results shown in Fig. 5. To validate this simple model, the linear interpolation results are compared to the results obtained by the three-dimensional TCAD simulation.
Quenched SET Pulse Width (ps)
other nodes when multiple nodes collect charge simultaneously due to a single particle strike. Three-dimensional technology computer-aided design (TCAD) numerical simulation is adopted to model the effect of ions incident location on the pulse quenching effect. Sentaurus TCAD from Synopsys is used for this part of the study. TCAD models are constructed according to the layout information in the 65 nm TSMC design library. The strip n-well contact with a width of 0.15 mm is used during the simulation. The distance between the n-well contact and the active area edge of the PMOS transistors is 0.5 mm. During the simulation, the LET value is assumed to be constant along the heavy ion track. The length and radius of the ion track are 5 mm and 0.05 mm, respectively. The following physical models are used: (1) Fermi–Dirac statistics; (2) band-gap narrowing effect; (3) doping-dependent SRH recombination and Auger recombination; (4) temperature, doping, electric field, and carrier–carrier-scattering impact on mobility; (5) incident heavy ions are modeled using a Gaussian radial profile with a characteristic 1/e radius of 0.1 m and a Gaussian temporal profile with a characteristic decay time of 0.25 ps; and (6) a hydrodynamic model is used for carrier transportation. Unless otherwise specified, the default models and parameters provided by Sentaurus TCAD vE-2010.12 are used. As presented in Fig. 3, logic cell1 and logic cell2 are assumed to be quenching cells, and the latter is the passive quenching cell. It is assumed that the PMOS transistors are in the off state in logic cell1. One SET pulse could appear at node Y1 when ions strike the PMOS transistors in logic cell1. Due to the pulse quenching effect, the SET pulse width at node Y2 could be reduced compared to that at node Y1. The ability of logic cell2 to reduce the SET pulse width is related to the amount of charge collected by its sensitive area, which is mainly determined by the distance between this area and the ions incident location. Because charge sharing is more pronounced in PMOS transistors in typical twin-well technology due to the parasitic bipolar effect [1,12], the PMOS transistors in the logic cells are mainly studied in our study. Fig. 4 shows the devices used to simulate the effect of ions incident location on the pulse quenching effect for the INV cell. Two different INV cell orientations are considered. Another INV electrically related to this studied INV cell is used to
67
D
Ions Incident Location Distance Between Ions Hit Location and Drain Center
S
The Device Used To Generate SET Pulse
The Studied Device
VDD
S
VDD
D
Ions Incident Location
S
D
Distance Between Ions Hit Location and Drain Center
Fig. 4. Devices used to simulate the effect of ions incident location on the pulse quenching effect for the INV cell. (a) CASE1 and (b) CASE2.
D. Yankang et al. / Microelectronics Journal 44 (2013) 65–71
Quenched SET Pulse Width (ps)
68
If the SET pulse at gate i could propagate to the primary outputs, the value of Ei(j) would be calculated by Eq. (3). Otherwise, the value of Ei(j) is equal to 0. Having obtained the soft error vulnerabilities of an individual gate, the soft error vulnerabilities of the whole circuit could be calculated by summing up the soft error vulnerabilities of each gate [13–16]. As presented in Eq. (4), CircuitSEVF represents the total circuit SEVF. X CircuitSEVF ¼ GateSEVF i ð4Þ
TCAD Proposed Model
300 280 260 240 220
i
200 0.35
0.40
0.45
0.50
CircuitSEVF is thus used as a metric to evaluate the soft error vulnerabilities of combinational circuits. Fig. 7 shows the whole process for evaluating the soft error vulnerabilities with consideration of the pulse quenching effect in combinational circuits.
0.55
Distance from Ions Incident Location to Drain Center of INV Cell (um) Fig. 6. Simulation results using the proposed model and the three-dimensional TCAD model.
4. Simulation results and discussion The distance between the ions strike location and the drain center of the studied INV cell is set to 0.35 mm, 0.45 mm and 0.55 mm. The placement direction for CASE1 presented in Fig. 4 is used. The simulation results shown in Fig. 6 indicate that this simple model conforms well to the TCAD simulation results. Similar simulations are also carried out for the other standard cells to determine their quenching ability and all TCAD simulation data are saved in two-dimensional look-up tables.
4.1. Impact of pulse quenching effect on the soft error vulnerabilities Before evaluating the circuit soft error vulnerabilities, we investigate the proportion of quenching cells in the circuit layout. Here, the electrically related cells are considered to be the two cells that have an electrical relationship in the circuit. Because the quenching cells are also the electrically related cells, the number of quenching cells is compared to the total number of electrically related cells in the circuits. The data in Table 2 show that the quenching cells account for a large proportion (approx. one-third)
3. Soft error vulnerabilities evaluation method Verilog Netlist
To evaluate the soft error vulnerabilities of the combinational circuits, the soft error vulnerabilities factor (SEVF), which is based on the probability of failure estimation model [13], is proposed in this paper. For each random input vector, the output value of each gate, one at a time, is injected into a single SET pulse. And the GateSEVFi, which is the SEVF of gate i, could be calculated by formula GateSEVF i ¼
1X P nEiðjÞ iðjÞ iðjÞ K
PWðt setup þ t hold Þ T clk
ð3Þ
Standard Cells
Synthesis Netlist
Quenching Ability of Logic Cells
Ploorplanning, Placement&Routing
ð2Þ
In the Eq. (2), K is the number of simulated input vectors. Pi(j) is the probability that gate i generates an SET pulse under input vector j when the drain area of gate i is struck, and Ei(j) is the probability that the generated SET pulse propagates to the circuit primary outputs or is latched under input vector j. To evaluate the soft error rates of combinational circuit, the drain area is usually taken as the sensitive area for transistors [13–18]. Here, we focus on the case where the drain area is hit by ions. Therefore, the value of Pi(j) is equal to the ratio of the area of sensitive drain area of gate i to the whole circuit area. Three masking effects (logical, electrical and latch-window masking effect) in combination circuits [14] are all considered to calculate Ei(j). Applying the depth first search (DFS) algorithm, the logical masking effect is used to extract all the paths from the gate i to the primary outputs under input vector j [19]. Then the SET pulse at gate i is propagated in the topological order using the electrical masking model proposed by Wang and Xie [15]. For the latch-window masking effect, the model presented in reference [16] is used. As presented in Eq. (3), P is the probability of the SET pulse at the primary outputs being latched. PW is the width of the SET pulse at the primary outputs. tsetup and thold are the setup and hold time of the flip-flops. And Tclk is the clock period. P¼
Design Compiler Systhensis
Layout DEF File Soft Error Vulnerabilities Analysis Tool Layout Analysis Tool
Soft Error Vulnerabilities Factor
Quenching Cells
Fig. 7. Process for introducing the pulse quenching effect into the evaluation of soft error vulnerabilities.
Table 2 Proportion of quenching cells in the layout placement for various benchmark circuits. Benchmark circuits
Total electrically related cells
Total Taken-up quenching cells proportion (%)
C1908 C2670 C3540 C432 C499 C5315 C6288 C7552
449 732 1117 191 501 1623 3421 2053
146 282 351 59 169 500 1271 655
32.5 38.5 31.4 30.9 33.7 30.8 37.1 31.9
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of the total electrically related cells. This investigation illustrates the prominence of the pulse quenching effect in the combinational circuits. For this simulation, the clock period is set to 400 MHz and the sum of the setup and hold time for the flip-flops is set to 60 ps. The incident ions with a LET of 30 MeV cm2/mg are assumed to strike the whole combinational circuits normally. The situation in which the drain areas are struck is especially studied. Piecewise linear (PWL) is used to characterize the injected SET pulse. For each random input vector, the output value of each gate, one at a time, is injected into a single SET pulse according to the output state of logic cells. When the output of one logic cell is HIGH, the NMOS transistors are sensitive and a negative SET pulse would be injected at the output of this logic cell. When the output of one logic cell is LOW, the PMOS transistors are sensitive and a positive SET pulse would be injected at the output of this logic cell. The injected SET pulse width is set according to the TCAD simulations. As the pulse quenching effect is not prominent in NMOS transistor in typical twin-well technology, the pulse quenching effect is not considered for the NMOS transistors. During the simulation, cases with and without the pulse quenching effect are considered. In both cases, the SET pulse is injected at the output of the directly hit node. For the case where pulse quenching effect is considered, the pulse width at the output of the passive quenching cells would be quenched. And the quenched pulse width is set according to the model proposed in Section 2.2. CircuitSEVF is then calculated for both cases. About 10,000 random input vectors are simulated. Table 3 presents the simulation results. As shown, when pulse quenching effect is introduced, the circuit soft error vulnerabilities factor could be reduced by 4–16% compared to the case Table 3 CircuitSEVF for different benchmark circuits with and without consideration of pulse quenching effect. Benchmark Circuits
CircuitSEVF
C1908 C2670 C3540 C432 C499 C5315 C6288 C7552
No Quenching
With Quenching
1.33E-03 8.51E-04 9.28E-04 5.13E-04 6.57E-04 7.79E-04 3.61E-03 1.16E-03
1.21E-03 7.15E-04 8.67E-04 4.93E-04 6.20E-04 7.38E-04 3.44E-03 1.09E-03
without considering pulse quenching effect for different benchmark circuit. For an in-depth analysis of the impact of pulse quenching effect on the soft error vulnerabilities, the SET pulse width distribution at
VDD
S
PMOS
NMOS
D
D
D
D
S
NMOS
S
VSS
VSS
Fig. 9. Two different cell orientations for the INV cell.
VDD
D
S
S
VDD
S
D
D
S
VDD
VDD
S
VDD
VDD
D
D
S
D
Fig. 10. Adjustment of cell orientations to enhance the pulse quenching effect.
Table 4 CircuitSEVF for different benchmark circuits when the layout is optimized.
Reduction in CircuitSEVF (%)
Benchmark Circuits
9.02 16.0 6.57 3.9 5.63 5.26 4.71 6.03
C1908 C2670 C3540 C432 C499 C5315 C6288 C7552
0.35
CircuitSEVF No Quenching
Optimized
Reduction in CircuitSEVF (%)
1.33E-03 8.51E-04 9.28E-04 5.13E-04 6.57E-04 7.79E-04 3.61E-03 1.16E-03
1.10E-03 6.68E-04 7.91E-04 4.35E-04 5.68E-04 6.71E-04 3.24E-03 1.02E-03
17.3 21.5 14.8 15.2 13.5 13.9 10.2 12.1
No_Quenching With_Quenching
0.30
0.25 0.20
Proportion
Proportion
VDD
PMOS
S
No_Quenching With_Quenching
0.30
69
0.15
0.25 0.20 0.15
0.10
0.10 0.05
0.05
0.00 0
10
0-
0 0 0 0 0 0 0 0 0 0 0 0 0 12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 360 0 0 0 0 0 0 0 0 0 0 0 0 28 30 32 34 12 14 16 18 20 22 24 26
1
00
SET Pulse Width (ps)
0.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 12 16 14 28 30 32 34 18 20 22 36 360 24 26 0- 00- 20- 40- 60- 80- 00- 20- 40- 60- 80- 00- 20- 401 1 1 2 2 2 2 3 3 1 1 3 2
SET Pulse Width (ps)
Fig. 8. SET pulse width distribution for the C1908 and C2670 circuits. (a) C1908 and (b) C2670.
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Proportion
0.25
No_Quenching With_Quenching Optimization
No_Quenching With_Quenching Optimization
0.35 0.30
Proportion
0.30
0.20 0.15
0.25 0.20 0.15
0.10 0.10
0.05
0.05 0.00
0.00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 12 14 16 18 20 22 24 26 28 30 32 34 36 360 0- 00- 20- 40- 60- 80- 00- 20- 40- 60- 80- 00- 20- 403 2 1 1 1 3 1 3 2 2 2 2 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 -34 -36 360 0 0 0 0 0 0 0 0 0 0 0 0 0 10 12 16 18 20 14 22 24 26 28 30 32 34
0-
SET Pulse Width (ps)
SET Pulse Width (ps)
Fig. 11. SET pulse width distribution for the C1908 and C2670 circuits after layout optimization. (a) C1908 and (b) C2670.
the primary outputs of circuits C1908 and C2670 is plotted in Fig. 8. As shown, when taking pulse quenching effect into consideration, the SET pulses with large pulse widths are reduced. And more SET pulses with short pulse widths appear. The reason is that when the pulse quenching effect is considered, the SET pulse width at the output of the passive quenching cells would be reduced compared to the SET pulse width at the output of the directly hit node. This would result in the reduction of SET pulse width at the primary outputs of the circuits. 4.2. Ideal optimized method to adjust the cell orientations As known, the cell orientation of each logic cell could be different. Fig. 9 presents two cell orientations for the INV cell. The ability of passive quenching cells to quench the SET pulse width is related to the distance from the ions incident location to the sensitive areas of the passive quenching cells. Different cell orientations would result in different distances. Minimization of this distance would beneficial to enhance the pulse quenching effect. In this study, an ideal optimized approach is proposed to adjust the cell orientations of the quenching cells to enhance the pulse quenching effect. Fig. 10 shows the PMOS transistors placement for two INV quenching cells. Fig. 10(a) presents two bad cell orientations that are unfavorable to the pulse quenching effect. The distance between the drain areas of these two PMOS transistors is not minimized. To enhance the pulse quenching effect, the drain areas of these two PMOS transistors are placed back-to-back as presented in Fig. 10(b). By using this placement, the passive quenching cells could collect as much charge as possible to quench the generated SET pulse width. As the NAND cell has a symmetric PMOS layout with the shared drain in the center, it would not be affected by this optimized approach. This approach is primarily aimed at the INV and NOR cells. To implement this optimized approach, the cell orientation parameter of the quenching cells in the DEF file obtained in Section 2.1 is modified. The modified principle is to minimize the distance between the drain areas of the quenching cells. Simulations similar to that described in Section 4.1 are conducted to calculate the circuit soft error vulnerabilities. The simulation results presented in Table 4 illustrate that soft error vulnerabilities are further reduced. More SET pulses with short pulse widths appear at the primary outputs due to the enhanced pulse quenching effect as presented in Fig. 11. As discussed, the layout placement could significantly affect the soft error vulnerabilities at advanced technologies. It would
be very promising to introduce the circuit reliability into the placement and routing algorithm.
5. Conclusion In this study, the impact of pulse quenching effect on the soft error vulnerabilities in large combinational circuits is investigated. Simulation results indicate that the soft error vulnerabilities could be reduced by 4–16% when pulse quenching effect is introduced. To enhance the pulse quenching effect, an ideal optimized approach is proposed for adjusting the cell orientations of the quenching cells in the circuit layout. The soft error vulnerabilities could be further reduced using this approach. As technology scales, the multi-node charge collection is becoming more prevalent. Introducing the layout placement into the soft error analysis would give the circuit designers a detailed insight into the circuit reliability. And new placement algorithms considering the circuit reliability would be promising in the future.
Acknowledgment This work is supported by the State Key Program of National Natural Science Foundation of China (Grant no. 60836004), National Natural Science Foundation of China (Grant nos. 61006070, 60906014) and Hunan Provincial Innovation Foundation for Postgraduate, China (Grant no. CX2012B028). References [1] O.A. Amusan, A.L. Witulski, L.W. Massengill, et al., Charge collection and charge sharing in a 130 nm CMOS technology, IEEE Trans. Nucl. Sci. 53 (6) (2006) 3253–3258. [2] J.R. Ahlbin, M.J. Gadlage, N.M. Atkinson, et al., Effect of multiple-transistor charge collection on single-event transient pulse widths, in: Proceedings of the IEEE International Reliability Physics Symposium (IRPS), May 2010, pp. 198–201. [3] V.B. Sheshadri, B.L. Bhuva, R.A. Reed, et al., Effects of multi-node charge collection in flip-flop designs at advanced technology nodes, in: Proceedings of the IEEE International Reliability Physics Symposium (IRPS), May, 2010, pp. 1026–1030. [4] T. Uemura, Y. Tosaka, H. Matsuyama, et al., SEILA: soft error immune latch for mitigating multi-node-SEU and local-clock-SET, in: Proceedings of the IEEE International Reliability Physics Symposium (IRPS), May, 2010, pp. 218–223. [5] R. Harada, Y. Mitsuyama, M. Hashimoto, et al., Neutron induced single event multiple transients with voltage scaling and body biasing, in: Proceedings of the IEEE International Reliability Physics Symposium (IRPS), April, 2011, pp. 253–257.
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