Impact of Statistical Variability and Charge Trapping on 14 nm SOI ...

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Impact of Statistical Variability and Charge Trapping on 14 nm SOI FinFET SRAM Cell Stability ! X. Wang1, B. Cheng1, A.R. Brown2, C. Millar2, J. B. Kuang3, S. Nassif3, A. Asenov1,2! !

1 Device Modelling Group,! University of Glasgow, UK

! 2 Gold Standard Simulations Ltd, UK



3 IBM Research – Austin, USA



! 1! ESSDERC, 16-20 September 2013, Bucharest Romania! !

Outline! q  Introduction! q  14 nm node DG SOI FinFETs! q  Simulation of Random Charge Trapping and

Statistical Variability Sources! q  Compact Modelling Methodology! q  Charge Trapping Impact on SRAM SNM! q  Charge Trapping Impact on SRAM WNM! q  Summary!

2!

Introduction •  Why this study?! •  Novel 3-D architecture FinFET will be widely adopted at 14 nm technology, with reduced variability on SOI substrate due to tolerance to low channel doping.!

•  However, (1) statistical aspect of reliability due to random individual trapping becomes an increasingly important issue. (2) In addition, charge trapping impact is affected by statistical variability sources.!

•  Accurately modeling reliability of nanoscale transistors in circuit level should take care of above mentioned properties, therefore requires a “statistical” method, rather than describing average reliability behavior.!

•  SRAM stability is susceptible to variability, therefore statistical study is needed.! 3!

FinFET

IMEC! Intel! 22nm! !

Veloso et. IEDM, 2009!

Fin Edge Roughness:! width, height, slope!

TSMC! Chang et., IEDM, 2009!

Bulk substrate!

IBM! Chang et., VLSI tech., 2011!

SOI substrate! 4!

Simulation Design of 14nm SOI FinFETs (GU-IBM collaboration) TE GA

MC calibrated @ 85°C!

W

fin

SOURCE

Double-Gate ! SOI FinFET!

LG

to

x

! E

XID DO

IE UR

B

TE RA

T BS

SU

Monte Carlo!

-1

2.5 2.0 source

7

fin

1.5

Velocity [x10 cm s ]

H

DRAIN

HM

Calibrated DD

drain

20!

EOT (nm)!

0.8!

WF (nm)!

10!

HF (nm)!

25!

NSD (cm-3 )!

3.0E20!

NCH (cm-3 )!

1.0E15!

VDD (V)!

0.9!

IOFF (nA/μm) !

10!

IDSAT (mA/μm) ! 0.9/0.8!

1.0

DIBL (mV/V)!

Default DD

0.5 0.0

Lg (nm)!

VG 0.420

30 40 Position [nm]

-0.8!

56/65!

Ref.: ITRS 2010 update!

50

5!

Intrinsic Parameter Fluctuations Statistical Variability Sources

TiN!

potential!

Random dopants!

Polysilicon/Metal Gate! Granularity!

Line Edge Roughness! 6!

Statistical variability simulation GER: ΔLG , ΔSCE! FER: ΔWFIN , Δconfinement! ΔRSD! RDD: ΔRSD , ΔNA! MGG: ΔΦM , Δψsurf !

•  Each variability source has different impact on the device parameters and performance.! Wang, et al, IEDM 2011, pp103-106! 7!

Interaction: Charge trapping vs Statistical variability sources Sensitive regions!

•  FER: local shortenings!

•  MGG: metal grains with high currents underneath!

•  RDD: current percolation paths! Wang et al, SISPAD 2012, pp.296-299! 8!

Vt RTS Distribution and Reliability are affected by Statistical Variability

1-CDF

1

Single Trapping!

0.1

Single Trapping 0.01 Uniform Device ’Atomistic’ Devices

0.001 0

Uniform device!

2

4

6

6VT (mV)

8

10

Wang et al., SNW 2012, pp.77-78!

Atomistic device!

•  In the presence of SV, the RTS distribution tail is increased! Multi-trapping!

RTS: random telegraph signal!

9!

Random charge trapping effect on VT

Normal Quantile

4

2

-2

Trapping Density (cm ) 0 1E11 5E11 1E12

0

-2

-4 0.1

0.15

0.2

0.25

VT (V)

0.3

0.35

0.4

Poisson distribution ! of trapping charge ! number is assumed!

•  First, the average VT shift increases with degradation heuristically;! •  Most important, the statistical variability increases with degradation.! 10!

Statistical Compact Modelling Method •  A small set of BSIM-CMG compact model parameters is used to extract statistical samples at fresh stage, also applied to degradation.! •  In circuits random fresh samples are assigned, responding stressed samples are put for stressed transistors.! •  Assume trapping effect is dynamically recoverable.! •  e.g., M2 is biased with high VG and low VD, subject to PBTI!

retention!

PU! PG!

PG!

PD!

6-Transistor SRAM cell! PU: pull-up transistor, p-FinFET;! PG: pass-gate transistor, n-FinFET;! PD: pull-down transistor, n-FinFET;! 11!

What happens to SRAM SNM after stress? A

VR (V)

0.8

SNM(A)

0.6 0.4 0.2 0 0

SNM(B)

Fresh Stress (state A) Stress (state B)

0.2

0.4

B 0.6

VL (V)

0.8

SNM: static noise margin, the SRAM stability for read mode! State A: left 0, right 1; State B: left 1, right 0!

•  Generally, stress induced trapping leads to less static noise margin ! •  Heavier N/PBTI, more threshold shift, less stability! ! 12!

SNM Distribution

Two types of SRAM cells! with fin-number ratio! of PU:PG:PD,! 111 SRAM and 112 SRAM! are examined!

•  First of all, the distribution is non-Gaussian.! •  Compared with 111-fin SRAM cells, 112-fin cells increase SNM.! •  With charge trapping induced degradations, the SNM is reduced.! 13!

Charge trapping effects on SNM 20

SNM (mV)

250

200

150

18

mSNM (mV)

SNM(A), 1:1:1 SNM, 1:1:1 SNM(A), 1:1:2 SNM, 1:1:2

16

SNM(A), 1:1:1 SNM, 1:1:1 SNM(A), 1:1:2 SNM, 1:1:2

14 12 10 8

100 0

2e+11

4e+11

6e+11

8e+11 -2

Trapping Density (cm )

1e+12

6 0

2e+11

4e+11

6e+11

8e+11 -2

1e+12

Trapping Density (cm )

•  The average SNM is reduced by up to 30 mV, with charge trapping induced degradations.! •  The statistical variation of SNM increases by 30-40% with degradation.! •  112-fin SRAM cells show better stability. Compared with 111-fin cells, 112-fin cells increases SNM by ~45% in average.! 14!

What happens to SRAM WNM after stress? 0.8

VL (V)

0.6 Fresh Stressed

0.4

0.2 WNM

0 0

!

0.2

0.4

0.6

0.8

VR (V) WNM: write noise margin, SRAM stability for write mode!

•  In contrary to SNM, WNM increases a bit due to charge trapping.! •  The WNM distribution is non-Gaussian.! 15!

Charge trapping effects on WNM

WNM (mV)

400

16

WNM (state A), 1:1:1 WNM, 1:1:1 WNM (state A), 1:1:2 WNM, 1:1:2

mWNM (mV)

420

380 360 340 320 0

2e+11

4e+11

6e+11

8e+11 -2

Trapping Density (cm )

1e+12

14

WNM (state A), 1:1:1 WNM, 1:1:1 WNM (state A), 1:1:2 WNM, 1:1:2

12

10

8 0

2e+11

4e+11

6e+11

8e+11 -2

1e+12

Trapping Density (cm )

•  The average WNM increases after stress, which is contrary to read SNM.! •  The standard deviation of WNM increases after stress, which is similar to read SNM.!

16!

SNM vs WNM with SV and random charge trapping Correlation Coefficient

0 Correlation between SNM and WNM

-0.2

-0.4

(VL=’0’,VR=’1’), 1:1:1 Minimum, 1:1:1 (VL=’0’,VR=’1’), 1:1:2 Minimum, 1:1:2

-0.6

-0.8 0

2e+11

4e+11

6e+11

8e+11 -2

1e+12

Trapping Density (cm )

•  Anti-correlation between SNM and WNM exists for one storing node.! •  Minimum defined SNM and WNM show decorrelations, due to statistically independent transistors responding to two storing states.! 17!

Impact on Six-sigma yield stress induced degradations

µ - 6m (mV)

400

300 SNM, 1:1:1 SNM, 1:1:2 WNM, 1:1:1 WNM, 1:1:2

200

100

0 0

2e+11

4e+11

6e+11

8e+11 -2

1e+12

Trapping Density (cm )

•  6-sigma of read SNM is greatly affected by stress induced charge trapping, not only due to average SNM reduction, but also by boosted statistical variability. ! •  112-fin SRAM cells show much better stability than high-density fin cells.! 18!

Summary

•  The random charge trapping effect can be accurately captured using the similar statistical compact modelling practice with statistical variability.! •  SRAM cell read stability is degraded by stress induced charge trapping; The statistical variation of SNM and WNM increased with degradations.! •  112 FinFET SRAM shows much better stability compared with high-density SRAM cells.! •  With the more random trapping, the read SNM six-sigma yield is reduced dramatically due to enhanced variation. ! 19!

Acknowledge

•  It is in part supported by Scottish Funding Council through Knowledge Transfer Project “Statistical Design and Verification of Analogue Systems”.! ! ! !! !Thank you for your attention.! ! ! ! 20!