Impact of Stress-Induced Backflow on Full-Chip Electromigration Risk ...
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6, JUNE 2006
Impact of Stress-Induced Backflow on Full-Chip Electromigration Risk Assessment Haldun Haznedar, Member, IEEE, Martin Gall, Vladimir Zolotov, Senior Member, IEEE, Pon Sung Ku, Member, IEEE, Chanhee Oh, Member, IEEE, and Rajendran Panda, Member, IEEE
Abstract—This paper presents a linear system formulation for evaluating full-chip electromigration (EM) risk in general (straight line, tree, and mesh) wiring topologies, considering stress-induced backflow of metal ions. The system of equations is based on stress gradients and mass displacements in wire segments as variables, and is formulated for efficient implementation in computer-aided design (CAD) tools for designing highperformance microprocessor chips involving large databases. Derived from a well-known hydrostatic stress model in tree interconnects (J. Appl. Phys., vol. 47, no. 4, p. 1203, 1976; IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 5, p. 576, 1999; Microelectron. Reliab., vol. 39, no. 11, p. 1667, 1999), the system is readily modified for evaluating EM risk in mesh topologies. The authors demonstrated a significant increase in the predicted lifetime of a high-performance microprocessor with the application of the proposed method to filter out risk-free structures from subsequent statistical EM risk calculations. Index Terms—Electromigration, integrated circuit reliability.
I. I NTRODUCTION
E
LECTROMIGRATION (EM) is the process of diffusion of wire metal ions due to electrical current flowing through the wire. This process results in the formation of voids and hillocks (metal accumulation) on the surface of the wire. At voids, the wire becomes thinner and locally more resistive. A higher local resistance increases joule heating and wire temperature, which further accelerate EM. Eventually, the void grows up so that the total wire resistance becomes too high for proper circuit operation, and this leads to EM failure. Hillock build-up is hazardous for chip operation too because it may create short circuits with adjacent interconnects. Advancement in very large scale integration (VLSI) process technology has aggressively reduced interconnect wire sizes (in both width and thickness), while chip-power levels have not
Manuscript received November 4, 2004; revised March 21, 2005. This paper was recommended by Associate Editor W. Schoenmaker. H. Haznedar, M. Gall and R. Panda are with Freescale Semiconductor, Inc., Austin, TX 78735 USA (e-mail: [email protected], Martin.Gall@ freescale.com; [email protected]). V. Zolotov was with Freescale Semiconductor, Inc., Austin, TX 78735 USA. He is now with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]). P. S. Ku is with Freescale Semiconductor, Inc., Tempe, AZ 85284 USA (e-mail: [email protected]). C. Oh was with Freescale Semiconductor, Inc., Austin, TX 78735 USA. He is now with Nascentric Inc., Austin, TX 78759 USA (e-mail: chanhee.oh@ nascentric.com). Digital Object Identifier 10.1109/TCAD.2005.855941
decreased at the same pace. In fact, introduction of copper for interconnect has reduced the wire resistance, enabling faster switching frequencies and resulting in increased maximum and average current densities in interconnects. Moreover, there are environmental factors, such as higher operating temperatures demanded by some applications (e.g., automotive controllers), and process technology factors, such as low-k dielectrics, silicon on insulator (SOI) transistors, and higher metal stacks, which aid and accelerate EM failure. Today’s larger chip designs with higher integration densities mean much higher interconnect counts per chip that tend to increase the probability of chip failure due to EM. The traditional approach to EM analysis has been based on developing and applying design rules. Usually, an EM design rule limits the current density through interconnect wires. It is a well-known fact that alternating current does not create significant EM damage. Therefore, EM design rules limit mainly average currents through interconnect wires whereas AC rules control local self-heating. Most of the interconnections between cells have only alternating currents because during rise transitions the current flows from the driver to the load and during fall transitions its direction is reversed. This helps to exclude from EM analysis many intercell interconnects. However, intracell interconnects often have unidirectional currents and are potentially susceptible to EM. Traditional EM design rules are constructed to guarantee a low probability of chip failure even in the worst case of all interconnects having maximum allowable currents. Taking into account the fact that, in modern VLSI chips, the total number of interconnects can reach as many as hundreds of millions, these EM design rules should be very stringent. A statistical EM budgeting methodology (SEB) was proposed to estimate the risk of EM failure due to the actual distribution of the current density [1]. Following this methodology, a more recent study showed that a design rule approach is overly pessimistic because many wires have current densities significantly lower than the maximum specified by guidelines [2]. This approach was proven to be very successful for full-chip EM analysis. Another well-known EM phenomenon is the stress-induced backflow [3]. Experiments show that short wires are significantly less susceptible to EM and can safely conduct a much higher current than long wires of the same width and thickness. EM moves ions from one side of the wire to the other. This creates mechanical stress in the wire that in turn creates mass flux in the direction opposite to the EM-induced flux. If the mechanical stress due to EM is less than a certain critical value, these two fluxes are well balanced and the wire has no
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HAZNEDAR et al.: IMPACT OF STRESS-INDUCED BACKFLOW ON FULL-CHIP ELECTROMIGRATION RISK ASSESSMENT
Fig. 1.
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EM in a wire segment. (a) Wire with electric current. (b) Wire cross section. (c) Material displacement due to electric current and mechanical stress.
significant voids or hillocks, which signifies a virtually eternal lifetime for the wire. If the mechanical stress is higher than the critical value, EM defects grow and the wire will eventually have an EM failure. The stress-induced backflow phenomenon can be utilized to reduce pessimism in the EM analysis. All the wires that are not susceptible to EM due to this effect can potentially be excluded when computing the probability of chip failure and its lifetime. The maximum wire length that can conduct a given current without EM violation is called the critical length [3]. For different current densities, the value of the critical length is different. For straight and uniform wire segments, it is known that the product of the critical length and the current density is constant. However, most interconnect structures used in VLSI chips are significantly more complex than a uniform wire segment. Moreover, the current density in different wire segments of the same interconnect structure is different, as different wire segments can be of different widths and carry different amounts of current. Therefore, the estimation of stress-induced backflow is significantly more complicated for complex interconnect structures and especially for structures with loops (meshes). An accurate and compact model for computing mechanical stress due to EM is necessary for developing computer-aided design (CAD) tools targeted for full-chip analysis. One of the most suitable theoretical models of EM for CAD implementation was proposed in [3], [4], and [13]. This model was based on differential equations describing the migrations of metal ions and vacancies as fluid–gas systems. In this paper, we present a methodology suitable for developing a full-chip EM analysis tool, which assesses the impact of the critical length effect at the chip level. In order to be able to handle large high-performance microprocessor chips with hundreds of million nets, we utilize a linear approximation of the aforementioned differential equations. We consider an interconnect wire structure consisting of all edges in the same layer that are connected together as a single object where EM failure may occur. We show that for straight-line and tree-like structures, an EM model, which assumes a hydrostatic stress state at each position in the segment, provides a well-defined and consistent linear system of equations. The solution of this system for the
given current densities provides values for mechanical stress in wires due to EM. By comparing these with the critical values, one can assess the EM risk of the circuit. Interconnect structures without EM risk are excluded from further analysis. All the other wires are analyzed by our SEB methodology [2]. We also demonstrate that for mesh interconnect structures the system of mechanical stress equations is incompletely defined. Therefore, there is a need to develop a technique transforming it into a completely defined linear system of equations with a unique solution. This transformation is again based on the same model of hydrostatic mechanical stress due to EM. We have implemented the proposed technique of stressinduced backflow calculation in our full-chip EM analysis tool [5]. All interconnects wherein the mechanical stress is below the critical level for EM failure are filtered out to reduce pessimism in EM risk assessment. The methodology has been successfully employed for EM analysis of high-performance microprocessor chips. The rest of the paper is organized as follows. Section II presents the main assumptions, equations, and their solutions of a hydrostatic model of mechanical stress due to EM for uniform and straight wire segments using the basics of the theory of elasticity. In Section III, we apply the proposed model to treelike interconnect structures. Section IV shows that the system of equations presented in Section II is incomplete and can have many solutions for mesh interconnect structures. Using this analysis, we develop a system of equations with a unique solution. In Section V, we give details of an implementation of the proposed technique and present some experimental data. Section VI discusses future work. In Section VII, we draw our conclusions. II. H YDROSTATIC M ODEL OF M ECHANICAL S TRESS Fig. 1 shows a wire segment with electrical current flowing from the right side of the wire to its left. Electrons hit Cu ions of the metal wire and push them in the direction opposite to the electrical current. The ion movement results in variation of the metal density along the wire from values higher than normal (compression) at the right hand side of the wire to values lower
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than normal (tension) at its left hand side. This density variation creates a mechanical stress gradient along the wire. The tensile stress has positive values whereas the compressive stress has negative values in accordance with the convention employed in the theory of elasticity. The nonzero stress gradient leads to a metal-ion flux in the direction opposite to the original ion flux. Then, the balanced state is described by the differential equation of equilibrium [3] jρq = Ω
dσ dx
(1)
where j is the current density flowing through the wire, ρ is the metal resistivity, q is the effective charge of the metal ion, Ω is the atomic volume, and dσ/dx is the gradient of the mechanical stress σ. Combining all constant terms, we obtain the differential equation for stress along the wire in equilibrium dσ = cj dx
(2)
where c = ρq/Ω. In modern VLSI interconnects, Cu wires are enclosed in dielectrics such as pure or C-doped SiO2 . At sufficiently high stress values, induced by ion diffusion, voids or hillocks can result in EM failure. However, we are interested in analyzing the range of stresses significant enough to affect the metal wire but small enough not to create a failure. We analyze the situation when there is no void or hillock formation, but they may occur, if we continue to increase the current and hence the mechanical stress. If the stress exceeds a certain critical value, a void is formed at the end of the wire. The failure usually takes place at the end of the interconnect where maximum tension occurs. Thus, we have a current-induced flux creating a stress-directed counterflux in a thin and narrow interconnect line embedded in a surrounding dielectric continuum and with blocking boundaries located at the ends of the line. The Cu diffusion is inhibited at contact and via sites through the use of tungsten-based plugs for the contact case and tantalumbased barrier layers for the via case. Both materials are highly stable, refractory metals, and have negligible diffusivities for Cu. This stress-induced backflow retards EM damage, and below a critical trace length, the EM flux is entirely balanced by the stress-directed backflow of ions. This behavior allows us to employ the theory of elasticity to formalize the system in a simple and computationally efficient way as follows. A material put under load deforms. If the load increase leads to a proportional increase in deformation, the material is linear. If the material, when unloaded, returns to its original shape, it is also elastic. When a body is loaded, the original coordinates of all its points move to a new position. Finding their displacement determines all the strains and the stresses causing them. The displacement vector of a point A moving to another point A has components in the x, y, z directions, which are usually called u, v, w. Under a linear transformation, geometric shapes retain their basic identity: straight lines remain straight. However, such a linear transformation may involve volume change (isotropic effect), distortion (shear or
deviatoric effect), and rotation. Displacement fields caused by boundary loads or similar perturbations to the initial condition are usually nonlinear; the fundamental linear assumption of calculus, however, permits us to use the relations of finite linear transformation in describing the relative displacement (i.e., deformation) du, dv, dw of differential elements dx, dy, dz. This depiction involves a tensor of second order. Since any tensor can be resolved into symmetric and asymmetric components where symmetry or asymmetry is with respect to the diagonal when the tensor is represented in matrix form, the aforementioned effects can be seen separately when the tensor is decomposed into its component parts. On a differential scale, then, as long as u, v, and w are continuous and small, we have the total derivative expressed in terms of the strain (deformation) tensor as ∂u ∂u ∂u dx du ∂x ∂y ∂z ∂v ∂v ∂v dv = (3) ∂x ∂y ∂z dy . ∂w ∂w ∂w dz dw ∂x
∂y
∂z
Splitting the strain tensor into its symmetric and asymmetric components yields [6] ∂u ∂u ∂u
∂x ∂v ∂x ∂w ∂x
∂y ∂v ∂y ∂w ∂y
∂z ∂v ∂z ∂w ∂z
1 2
∂u ∂x
∂v + ∂u = 12 ∂x ∂y
1 ∂w ∂u 2 ∂x + ∂z
∂u ∂y
∂v ∂x
+
∂v ∂y
1 2 1 2
∂u
1 ∂w ∂v 2 ∂y + ∂z εij , symmetric strain tensor
0
∂v + 12 ∂x − ∂u ∂y
1 ∂w ∂u 2 ∂x − ∂z
1 2
∂u ∂y
− 0
∂v ∂x
∂z
+
∂w ∂x
∂v ∂z
+
∂w ∂y
∂w ∂z 1 2
1 2
1 ∂w ∂v 2 ∂y − ∂z asymmetric strain tensor
∂u
∂z
∂v ∂z
−
∂w ∂x
−
∂w ∂y
0
.
(4) The symmetric portion is further decomposed into isotropic and deviatoric components εij = εm (isotropic strain tensor) + eij (deviatoric strain tensor)
(5)
where εm =
1 (εx + εy + εz ). 3
(6)
This uncoupling of the tensor into isotropic and deviatoric parts directly corresponds to the fundamental physical reality of material behavior under load. Each individual element of the symmetric strain tensor produces the normal or hydrostatic strain, i.e., the deformation of the orthogonal differential base length dx, dy, and dz with respect to finite base lengths x, y, and z when u, v, and
HAZNEDAR et al.: IMPACT OF STRESS-INDUCED BACKFLOW ON FULL-CHIP ELECTROMIGRATION RISK ASSESSMENT
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w are linear functions. In IC interconnects, the load is the electrical current and it flows in one dimension; thus, there is no rotation involved and the tangential shear effect can safely be assumed to be negligible for the wear out mechanism under consideration. Therefore, the strain tensor of order two is reduced to a simple uniaxial scalar (i.e., a tensor of order zero). Strain εx is the individual diagonal element in the x-direction in the symmetric component of the tensor in (4). It produces a deformation of the differential base length dx εx =
du ∂u = ∂x dx
(7)
where u is the displacement in the x-direction due to deformation. On the other hand, stress is defined as the limiting value of average force per unit area as the cross-sectional area approaches zero [7]. Similar to the strain tensor, the stress tensor has symmetric isotropic and asymmetric deviatoric components. The isotropic component is essentially scalar, having only magnitude in all principal directions. The mean stress σm
1 = (σx + σy + σz ) 3
σx M
(8) 0
(9)
where the constant M is the experimentally determined modulus. In practice, an appropriate bulk modulus is used, as explicated in [8]. Note that the fundamental assumption in this discussion is that the displacements are small, continuous, and smooth. Thus, over differential base lengths, deformations are linear and elasticity yields a linear stress–strain relationship. When this is no longer the case, peculiarities develop in the mathematical displacement field, corresponding to physical voids and hillocks in metals, a condition defined as yield, which signifies the end of the elasticity domain. Then, the theory of plasticity takes over. Once this occurs, the structure is permanently deformed and lifetime is drastically reduced. In interconnects, this corresponds to EM failures. If the wire cross-section is constant, integrating (2) leads to an expression for the hydrostatic stress as a function of distance σ(x) = cjx + σ0
(10)
where σ0 is the stress at the reference node. From (7) and (9), we also have du =
1 σ(x)dx M
which, upon integration over the length of the wire segment, yields
is the hydrostatic pressure if negative and causes only volume change. The deviatoric component causes only distortion or shear with no volume change. In a state of hydrostatic pressure, Hooke’s Law gives the strain–stress relationship as εx =
Fig. 2. Single-layer net fragment. (a) Net fragment. (b) Its graphical representation.
(11)
1 du = M
σ(x)dx
(12)
0
1 u − u0 = σ0 + cj. M 2M
(13)
But, from (10), cj = σ − σ0 . Substituting this into (13) and simplifying, we get u − u0 =
(σ + σ0 ). 2M
(14)
For any point where several wire segments are connected together, the law of conservation of mass is valid as well. Assuming that the volume of the internal node connected to several wire segments is negligibly small to accumulate any amount of material, the law of conservation of mass expresses the simple fact that the net amount of material coming from all wire segments is zero. Assuming that all wire segments have the same thickness, this is expressed by
wi ui = 0
(15)
where wi is the width of the ith segment. III. M ECHANICAL S TRESS E QUATIONS FOR A T REE L AYOUT Fig. 2 shows a net fragment lying on a single layer and its graph model G(N, E), where N = {ni } is a set of nodes and E = {ej } is a set of edges ej = (nj1 , nj2 ). Each wire segment is modeled by a directed edge. The edge direction indicates the direction of the positive electrical current and mass displacement. For each edge em = (ni , nk ), we know the length m and width wm and the density jm of the electrical current flowing through it.
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Using the mechanical stress model described above by (10), (14), and (15), we can construct the following system of equations. 1) Stress equations describe the relation between the electric current density jm flowing through an edge em = (ni , nj ) and the mechanical stress values at the source and sink nodes ni , nj of the edge, i.e., σj − σi = cm jm
(16)
where c is the coefficient in (2) defined by the physical properties of the wire material. 2) Displacement equations describe the relation between mechanical stress values σi , σj at the source and sink nodes ni , nj of the edge em = (ni , nj ) and the wire material mass displacement ui , uj at the source and sink ends of the edge, i.e., uj − ui =
m (σj + σi ). 2M
(17)
3) The law of conservation of mass states that for each node ni of the directed graph, taking into account the direction of the edges and denoting the incoming edge as positive, the amount of incoming and outgoing displacements is always the same, i.e., ep ∈IN(ni )
wp up −
wq uq = 0
Fig. 3. Layout structure with a loop. (a) Fragment of a net layout. (b) Its graph model.
(18)
eq ∈OUT(ni )
where IN(ni ) is a set of incoming edges at node ni , OUT(ni ) is a set of outgoing edges from node ni , ep and eq are incoming and outgoing edges incident to node ni , up and uq denote wire material mass displacement at the incoming and outgoing edges, respectively, and wp , wq are the widths of the respective wire segments. Equation (18) neglects the accumulation of material in internal nodes with multiple wire segments, which is quite a valid assumption, because the node volume is usually much smaller than that of the wire segments. Moreover, this volume is partially included in the wires. From the above construction, it is clear that the number of stress equations in (16) is the same as the number of displacement equations in (17) and is equal to the number of graph edges NE . The number of equations in (18) equals the number of graph nodes NN . Therefore, the total number of unknown variables is 2NE + NN . The number of stress variables equals the number of graph nodes NN . The number of displacement variables ui and uj equals 2NE , twice the number of graph edges. Consequently, the total number of unknown variables is equal to the number of equations. For tree-like layout structures, (16)–(18) are independent of each other and the whole system has a unique solution. Equation independence can be proven by induction using the properties of trees [2]. It is obvious for wire structures consisting of a single wire segment. Assuming that the equations are independent for a tree T , consisting of K edges, it is not difficult to show the independence of the equations for a tree
Fig. 4.
Loop of wires e1 , e2 , . . . , ek .
with K + 1 edges, constructed by connecting a wire segment to an arbitrary node of a tree T . IV. M ECHANICAL S TRESS E QUATIONS FOR A M ESH L AYOUT For the mesh layout with loops of wires, however, the above system of mechanical stress equations (16)–(18) is not independent. Fig. 3(a) shows an example of a layout with a loop of wires. A graph model of this layout is shown in Fig. 3(b). For this example, we shall show that the stress equations (16) are linearly dependent and displacement equations (17) are incomplete, i.e., combined with other equations, they do not define unique values for mass displacements. We will show how to modify the original system of mechanical stress equations (16)–(18) to make it well defined to produce a unique solution. A. Linear Dependence of Stress Equations The first problem occurs with stress equations in (16). Assume that we have a loop with nodes n1 , n2 , . . . , nk and edges e1 = (n1 , n2 ), e2 = (n2 , n3 ), . . . , ek−1 = (nk−1 , nk ), ek = (nk , n1 ), as shown in Fig. 4. Then the mechanical stress equations for edges of this loop are given as σ2 − σ1 = c1 j1 σ3 − σ2 = c2 j2 .. . σk − σk−1 = ck−1 jk−1 σ1 − σk = ck jk .
(19)
HAZNEDAR et al.: IMPACT OF STRESS-INDUCED BACKFLOW ON FULL-CHIP ELECTROMIGRATION RISK ASSESSMENT
Summing up all the equations except the last one, we obtain σk − σ1 = c
k−1
p jp .
(20)
p=1
The left hand side of this equation differs from the left hand side of the last equation of the system in (19) by its sign only. Thus, the equation set (19) is not independent. We need to analyze the right hand side of (20) and compare it with the right hand side of the last equation of the system represented by (19). Using Ohm’s law for each edge ep and the corresponding wire segment, we can express the current density jp flowing through the edge as jp =
vp − vp+1 vp − vp+1 = wp rp ρs p
(21)
where νp and νp+1 are the node potentials at np , np+1 ; rp , wp , p are the resistance, width, and length of the wire segment, respectively; and ρs is the wire metal sheet resistance, which is the same for all wires, since they are on the same layer. Substituting (21) for current density in (20) and performing obvious algebraic simplifications, we obtain σk − σ1 =
c (v1 − vk ). ρs
(22)
Similarly, substituting (21) for the current density in the last equation of system in (19), we get σ1 − σk =
c (vk − v1 ). ρs
(23)
This equation is exactly the same as (22). Therefore, it proves that, for the loop, the system in (19) is consistent, but its equations are not independent. One of its equations is a logical consequence of all the others and should be removed from the system. From the above considerations, it is clear that the equation to be removed can be selected arbitrarily from the stress equations for the nodes in the loop so that the loop is broken. However, the system of mechanical stress equations for a layout with a loop then becomes underdetermined.
Each added increment in this vector is defined as ∆up ≡
∆u wp
∆u = −u1s wp
(24)
where ups and upf are mass displacements at the source and sink ends of the edge ep , respectively, with 1 ≤ p ≤ k. Using (24), we form a new vector of mass displacements as U = (u1s + ∆u1 , u1f + ∆u1 , . . . , uks + ∆uk , ukf + ∆uk ). (25)
(27)
which is equivalent to adding u1s = 0
The second problem occurs with displacement equations in (17). We again consider a loop of nodes and wires, as shown in Fig. 4. Assume that the solution of mechanical stress equations (16)–(18) includes the vector of mass displacements for edges forming the loop, i.e.,
(26)
where ∆u is an arbitrary value selected to be the same for all ∆up . Then, (25) satisfies (17) and (18). Equations in (17) are satisfied because the mass displacements at the sink and source of an edge are modified by the same value. Equations in (18) either include no modified values of displacements or include them in pairs: one with a positive and the other with a negative sign corresponding to incoming and outgoing loop edges at a node. The value added to each displacement is inversely proportional to the corresponding wire width in (26). Therefore, these added values ∆up wp cancel each other in (18), corresponding to the loop nodes ni , and any solution in the form of (25) constructed from its valid solution satisfies all the mechanical stress equations. This rather unexpected phenomenon has a very simple physical explanation. Our model of mechanical stress assumes that the metal wire at EM stress values behaves as a fluid. However, fluid can flow in loop pipes without any additional pressure or tensile stress. This is exactly equivalent to our conclusion that any valid displacement solution can be modified in the way specified by (25) and (26). Of course, in real wire loops, no rotation flow of wire material occurs because adhesion of wire material (Cu and barrier) to the dielectric shell surrounding it and the corresponding tangential stress prevents this rotation. However, according to modern theory of EM [3], [4], [13], this stress component is negligibly small compared with compressive and tensile stresses. Therefore, we ignore it in our computations. As a result, we have to impose additional restrictions on mass displacement in order to make our equations have a unique solution. For convenience, we select the constant ∆u as
B. Incompleteness of Displacement Equations
U = (u1s , u1f , u2s , u2f , . . . , uks , ukf )
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(28)
to the original system of mechanical stress equations (16)–(18). Adding (28) prevents mechanical stress equations (16)–(18) from having multiple solutions due to the rotation flow of the wire material, which, in reality, is prohibited by adhesion of wire material to the dielectric, as explained above. C. General Mesh Layouts We have shown that for a layout with a single loop, one of the stress equations in (16) for loop nodes is linearly dependent on the others and should be removed from the system. Furthermore, to make the system of equations completely determined, it is necessary to correct the mass displacement at one of the loop wires.
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Fig. 7. Graph model with a floating limb attached at various points of the metal line (a) anode, (b) middle, and (c) cathode.
Fig. 5. Example of a mesh layout and its graph model with four fundamental loops. (a) Net fragment. (b) Graph representation of the fragment’s spanning tree T . Branches {b1 , . . . , b10 } are shown with solid lines and chords {c1 , c2 , c3 , c4 } with dashed lines.
Fig. 6. Algorithm for constructing a system of mechanical stress equations for mesh structures.
Fig. 5 shows an example of a multiloop mesh layout and the corresponding graph model. For loop analysis, it is more convenient to use nondirected graphs. Edge directions are required only for constructing mechanical stress equations and can be selected in an arbitrary way. They affect only signs of coefficients in the system of equations. From graph theory [9], it is known that it is always possible to construct a fundamental set of loops S = {L1 , L2 , . . . , Lr } such that any two loops Li and Lk from this set differ at least by one edge and none of the loops is a linear combination of the other loops. Moreover, any other loop of the graph is a combination of fundamental loops. A fundamental set of loops can be constructed as follows: 1) build a spanning tree of the graph; 2) construct for each chord ci (edge outside of the spanning tree), the corresponding fundamental loop by combining this chord with the required spanning tree branches bk . The algorithm for constructing mechanical stress equations for a general mesh layout is shown in Fig. 6. It starts by constructing the system of mechanical stress equations (16)–(18), ignoring issues related to the layout loops. Then the algorithm transforms the constructed system into a correct one by removing dependent stress equations and adding required displacement equations.
V. I MPLEMENTATION AND R ESULTS We have implemented the proposed stress-induced backflow calculation in a full-chip EM analysis software that implements the SEB as well. The software takes extracted parasitic and device netlists as the input, which are back annotated with geometrical information, such as wire segment widths and lengths, and metal layers. From the input netlists, wire segments that are contiguous on the same metal layer are identified. For each of these wire segments, the worst-case (i.e., maximum) average current is computed, which is then used for mechanical stress calculations at the blocking boundaries of each wire segment, i.e., at via and contact interfaces. During this calculation, the spanning tree-based algorithm, as described in Section IV-C, is applied to detect any loop. Generic matrix packages are used for the solution of the linear system of equations during current density and mechanical stress computations. As an example of mechanical stress computation, floating limbs are attached to various places of a single wire segment, as shown in Fig. 7, and the calculated stress values are summarized in Table I. The metal-ion movement due to the electron wind results in a higher metal density at the anode side of the wire that creates compressive stress, whereas the lower metal density at the cathode leads to tensile stress. When the limb is attached to the anode (node a), the metal ion will move from the “active” region into the “inactive floating limb region” and the stress level at the anode will be lower than the one without a limb. In contrast, the stress level at the cathode (node c) will be higher because the effective length of the total metal line becomes longer. However, if the floating limb of the same length is attached to the cathode, the calculated stress values are exactly the opposite of the previous case. When the floating limb is attached exactly in the middle (node b) of the line, the stress value at this point becomes zero because of the symmetry and mass conservation. The floating limb has no stress gradient since there is no current flowing through it. The constant c in (2) is estimated to be 2.5 MPa−µm/mA. When the length of the limb is varied, the stress values at each node are changed, as shown in Fig. 8. When the limb length at cathode is increased, the tensile stress at cathode decreases, whereas the compressive stress at anode increases. On the contrary, as the length of the limb attached to the anode is elongated, the tensile stress at the cathode increases, while the compressive stress at the anode decreases. The limb attached at the middle does not affect the stress value at all, as expected.
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TABLE I CALCULATED STRESS VALUES AT EACH NODE WHEN A FLOATING LIMB IS ATTACHED AT DIFFERENT NODES
VI. F UTURE W ORK The implementation of the stress calculator for full-chip power grid analysis is currently underway. Before one can assume that the critical length effect leads to essentially infinite lifetime of the signal and clock nets, its experimental validation under high-frequency pulsed-DC operation in Cu-based interconnects has to be carried out. Work is currently in progress for this purpose. Initial wafer-level results using pulsed-DC currents on actual test structures, conducted at an ambient temperature of 300 ◦ C and with moderate effective current densities, indicate that short interconnect lines behave as expected, assuming an “effective DC” critical length effect. Furthermore, the effect of the superposition of thermal stresses—on the order of almost 400 MPa [12]—and EM-induced stresses needs to be evaluated. Both stress relaxation and void growth kinetics need to be taken into account and experimental data should be extrapolated to 105 ◦ C operating conditions to ensure that the critical length effect is indeed operative at long chip lifetimes. Fig. 8. Stress values at anode and cathode are calculated as a function of limb length.
This simple example demonstrates that attaching a floating limb at a critical node can be useful to control the mechanical stress. The full-chip EM risk assessment has been applied to a high-performance microprocessor for embedded applications at a junction temperature of 105 ◦ C. The analysis, including mechanical stress computations, took about an hour on three Unix workstations running in parallel. This design contains more than 56 million transistors. Signal and clock nets were treated separately from the power grid. The chip-level results for signals and clocks indicate that the highest EM-induced stress is in the order of 140 MPa, both in tension and compression, leading to a maximum stress difference of 280 MPa between blocking boundaries. It was found that segments with the highest current density values were relatively short. The critical current density × length product (jl)∗ under DC conditions was measured to be about 3700 A/cm for the metallization used for the microprocessor described in this study [10]. With a lower bound on (jl)∗ of 3000 A/cm and an estimated effective charge value Z ∗ (q = Z ∗ e, where e is the electronic charge) close to unity at 105 ◦ C [11], the highest stress difference between wire segment ends is on the order of 750 MPa. This value is higher than the calculated 280 MPa from the chip analysis, indicating that the critical length effect, if applicable for non-DC signals under the assumption of an effective current model, should prevent all interconnects on the signal and clock circuits from EM failures.
VII. C ONCLUSION We described here an efficient and accurate technique of EM risk analysis taking into account the critical length effect, which plays a very important role in EM phenomena in shortwire structures. The proposed technique can handle general (tree and mesh) layout structures and is suitable for full-chip analysis. Our approach is based on computing mechanical stress caused by electrical current in copper-wire structures. Using basic concepts of the theory of elasticity, we showed that hydrostatic stress can be efficiently computed for EM risk assessment by solving a system of linear equations. We developed an efficient algorithm for constructing this system for general (tree and mesh) layout structures that describes relations between stress and material displacement in copper wires with high-density electrical current. The hydrostatic model assumed an equiaxial stress state. It was shown that this approach results in an incomplete system of equations in mesh structures. In this case, it is possible to change the system to a fully determined one by introducing an additional equation to compute correct values of hydrostatic mechanical stress. R EFERENCES [1] J. Kitchin, “Statistical electromigration budgeting for reliable design and verification in a 300-MHz microprocessor,” in IEEE Symp. VLSI Circuits, Kyoto, Japan, 1995, pp. 115–116. [2] C. Oh, H. Haznedar, M. Gall, A. Grinshpon, V. Zolotov, P. Ku, and R. Panda, “A methodology for chip-level electromigration risk assessment
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[3] [4]
[5]
[6] [7] [8]
[9] [10]
[11] [12] [13]
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and product qualification,” in Proc. 5th Int. Symp. Quality Electronic Design (ISQED), San Jose, CA, 2004, pp. 232–237. I. A. Blech, “Electromigration in thin aluminum films on titanium nitride,” J. Appl. Phys., vol. 47, no. 4, pp. 1203–1208, Apr. 1976. J. J. Clement, S. P. Riege, R. Cvijetic, and C. V. Thompson, “Methodology for electromigration critical threshold design rule evaluation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 5, pp. 576– 581, May 1999. C. Oh, D. Blaauw, M. R. Becer, V. Zolotov, R. Panda, and A. Dasgupta, “Static electromigration analysis for signal interconnects,” in Proc. 4th Int. Symp. Quality Electronic Design (ISQED), San Jose, CA, 2003, pp. 377–382. R. Richards, Jr., Principles of Solid Mechanics. Boca Raton, FL: CRC Press, 2001. P. C. Chou and N. J. Pagano, Elasticity: Tensor, Dyadic, and Engineering Approaches. Princeton, NJ: Van Nostrand, 1967. R. G. Filippi, R. A. Wachnik, C.-P. Eng, D. Chidambarrao, P. C. Wang, and J. F. White, “The effect of current density, stripe length, stripe width, and temperature on resistance saturation during electromigration testing,” J. Appl. Phys., vol. 91, no. 9, pp. 5787–5795, May 2002. N. Deo, Graph Theory With Applications to Engineering and Computer Science. Englewood Cliffs, NJ: Prentice-Hall, 1974. S. Thrasher, M. Gall, C. Capasso, P. Justison, R. Hernandez, T. Nguyen, and H. Kawasaki, “Examination of critical length effect in copper interconnects with oxide and low-k dielectrics,” in Proc. 7th Int. Workshop Stress-Induced Phenomena, Austin, TX, 2004, pp. 165–172. R. Rosenberg, D. C. Edelstein, C.-K. Hu, and K. P. Rodbell, “Copper metallization for high performance silicon technology,” Annu. Rev. Mater. Sci., vol. 30, pp. 229–262, Aug. 2000. D. Gan, G. Wang, and P. S. Ho, “Effects of dielectric material and line width on thermal stresses in Cu lines,” in Proc. IEEE Int. Interconnect Technical Conf., Burlingame, CA, 2002, pp. 271–273. W. Schoenmaker and V. Petrescu, “Modeling electromigration as a fluid–gas system,” Microelectron. Reliab., vol. 39, no. 11, pp. 1667–1676, Nov. 1999.
Haldun Haznedar (S’78–M’82) received the B.S. degree in electrical engineering from the Middle East Technical University, Ankara, Turkey, in 1975, the M.S. degree in electrical engineering from the University of Alabama, Hunstville, in 1977, and the Ph.D. degree in electrical engineering from the University of Alabama, Tuscaloosa, AL, in 1981. After working in the academia for seven years, he joined Texas Instruments in 1990 and Motorola in 2001, and has been involved in the development of computer-aided design (CAD) tools and methodology for high-performance IC designs. In 1991, he published Digital Microelectronics, an advancedundergraduate textbook, and holds one U.S. patent. His interests lie in all aspects of CAD and intrinsic-reliability engineering as well as the Philosophy of Mind. Dr. Haznedar is a member of the Tau Beta Pi.
Martin Gall received the M.S. degree (Diplomphysiker) in physics from the RheinischWestfaelische Technische Hochschule Aachen, Germany, in 1992 and the Ph.D. degree in materials science and engineering from The University of Texas, Austin, in 1999. Most of his dissertation work was conducted at Motorola’s Advanced Products Research and Development Laboratory. In 1995, he joined Freescale Semiconductor, Inc./Motorola, Austin, TX, and has been working in the area of backend reliability, mainly addressing issues with electromigration and stress-induced voiding. In mid-1999, he joined The Technical University at Delft (Netherlands) for a one-year assignment as a Visiting Scientist. Upon his return to Freescale Semiconductor, Inc./Motorola, he continued backend reliability development for the 130- and 90-nm technology nodes. Since 2002, he has been leading the interconnect reliability team at the Technology Solutions Organization, mainly focusing on implementation of advanced low-k dielectrics. He (co)authored over 30 papers and serves as a technical committee member or reviewer for leading conferences and journals.
Vladimir Zolotov (M’97–SM’04) received the M.S. degree in electrical engineering from the Moscow Institute of Electronics, Moscow, Russia, in 1977, and the Ph.D. degree in electrical engineering from the Scientific Research Institute of Micro Devices, Moscow, Russia, in 1988. He was previously with Motorola Inc., where he was involved in the development of EDA tools and methodology for high-performance and low-power very large scale integration (VLSI) designs. He is currently a Research Staff Member at the IBM T.J. Watson Research Center, Yorktown Heights, NY, where he is working on statistical static timing analysis. His research interests include statistical timing, signal integrity, fast circuit simulation, reliability analysis, on chip inductance, and optimization of VLSI.
Pon Sung Ku (M’97) received the M.S. degree in electrical engineering from the University of Arizona, Tucson, and the Ph.D. degree in electrical engineering from the Arizona State University, Tempe, in 1986 and 1995, respectively. In 1986, he joined IBM General Product Division, San Jose, and developed a test system for magnetic hard drive testing. Since joining the Motorola Semiconductor Products Sector in 1994, he has worked in the area of Si IC reliability and technology modeling. He is currently the Manager of the Advanced Reliability Engineering Team in Freescale Semiconductor, Inc., Phoenix, AZ. His main research area is the design for reliability and device reliability. Dr. Ku is a member of the IEEE Electron Devices Society.
Chanhee Oh (S’87–M’95) received the B.S. degree in control and instrumentation engineering from Seoul National University, Korea, in 1987 and the M.S. and Ph.D. degrees, both in electrical engineering, from the University of Texas, Austin, in 1989 and 1995, respectively. Prior to joining Freescale Semiconductor, Inc., Austin, TX, he was with a microprocessor development group at Advanced Micro Devices, Austin, TX. From 1997 to 2004, he was with Freescale Semiconductor, Inc., where he led internal development of EDA solutions for high-performance very large scale integration (VLSI) designs. Since 2004, he has been with Nascentric Inc., Austin, TX, where he holds a technical leadership position for research and development of high-speed circuit simulation and analysis tools. He has over 20 technical publications and holds a U.S. patent. His research interests include signal integrity, circuit simulation, reliability, timing analysis, and optimization of VLSI circuits.
Rajendran Panda (M’97) received the B.E. degree (Honors) in electrical and electronics engineering from Madurai University, India, in 1978, the Bachelor of Laws (LL.B.) degree from Bangalore University, India, in 1984, and the Ph.D. degree in computer science from the University of Illinois at Urbana-Champaign, in 1996. From 1978 to 1991, he was a practicing Electrical Engineer at Bharat Heavy Electricals Limited, India, specializing in utility systems, industrial controls, and automation systems. Since 1996, he has been with Freescale Semiconductor, Inc., Austin, TX (the erstwhile Semiconductor Products Sector of Motorola), where he is currently managing a computeraided design (CAD) research and development team. He has published over 40 journal and conference papers, including two best papers, and presented tutorials and invited talks on these topics. His research interests include very large scale integration (VLSI) power distribution, signal integrity, and lowpower high-performance design issues. Dr. Panda is currently serving in the technical program committees of the International Conference on Computer Aided Design (ICCAD), the International Symposium on Quality Electronic Design (ISQED), and the Design, Automation and Test in Europe (DATE) conferences.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6, JUNE 2006
Impact of Stress-Induced Backflow on Full-Chip Electromigration Risk Assessment Haldun Haznedar, Member, IEEE, Martin Gall, Vladimir Zolotov, Senior Member, IEEE, Pon Sung Ku, Member, IEEE, Chanhee Oh, Member, IEEE, and Rajendran Panda, Member, IEEE
Abstract—This paper presents a linear system formulation for evaluating full-chip electromigration (EM) risk in general (straight line, tree, and mesh) wiring topologies, considering stress-induced backflow of metal ions. The system of equations is based on stress gradients and mass displacements in wire segments as variables, and is formulated for efficient implementation in computer-aided design (CAD) tools for designing highperformance microprocessor chips involving large databases. Derived from a well-known hydrostatic stress model in tree interconnects (J. Appl. Phys., vol. 47, no. 4, p. 1203, 1976; IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 5, p. 576, 1999; Microelectron. Reliab., vol. 39, no. 11, p. 1667, 1999), the system is readily modified for evaluating EM risk in mesh topologies. The authors demonstrated a significant increase in the predicted lifetime of a high-performance microprocessor with the application of the proposed method to filter out risk-free structures from subsequent statistical EM risk calculations. Index Terms—Electromigration, integrated circuit reliability.
I. I NTRODUCTION
E
LECTROMIGRATION (EM) is the process of diffusion of wire metal ions due to electrical current flowing through the wire. This process results in the formation of voids and hillocks (metal accumulation) on the surface of the wire. At voids, the wire becomes thinner and locally more resistive. A higher local resistance increases joule heating and wire temperature, which further accelerate EM. Eventually, the void grows up so that the total wire resistance becomes too high for proper circuit operation, and this leads to EM failure. Hillock build-up is hazardous for chip operation too because it may create short circuits with adjacent interconnects. Advancement in very large scale integration (VLSI) process technology has aggressively reduced interconnect wire sizes (in both width and thickness), while chip-power levels have not
Manuscript received November 4, 2004; revised March 21, 2005. This paper was recommended by Associate Editor W. Schoenmaker. H. Haznedar, M. Gall and R. Panda are with Freescale Semiconductor, Inc., Austin, TX 78735 USA (e-mail: [email protected], Martin.Gall@ freescale.com; [email protected]). V. Zolotov was with Freescale Semiconductor, Inc., Austin, TX 78735 USA. He is now with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail: [email protected]). P. S. Ku is with Freescale Semiconductor, Inc., Tempe, AZ 85284 USA (e-mail: [email protected]). C. Oh was with Freescale Semiconductor, Inc., Austin, TX 78735 USA. He is now with Nascentric Inc., Austin, TX 78759 USA (e-mail: chanhee.oh@ nascentric.com). Digital Object Identifier 10.1109/TCAD.2005.855941
decreased at the same pace. In fact, introduction of copper for interconnect has reduced the wire resistance, enabling faster switching frequencies and resulting in increased maximum and average current densities in interconnects. Moreover, there are environmental factors, such as higher operating temperatures demanded by some applications (e.g., automotive controllers), and process technology factors, such as low-k dielectrics, silicon on insulator (SOI) transistors, and higher metal stacks, which aid and accelerate EM failure. Today’s larger chip designs with higher integration densities mean much higher interconnect counts per chip that tend to increase the probability of chip failure due to EM. The traditional approach to EM analysis has been based on developing and applying design rules. Usually, an EM design rule limits the current density through interconnect wires. It is a well-known fact that alternating current does not create significant EM damage. Therefore, EM design rules limit mainly average currents through interconnect wires whereas AC rules control local self-heating. Most of the interconnections between cells have only alternating currents because during rise transitions the current flows from the driver to the load and during fall transitions its direction is reversed. This helps to exclude from EM analysis many intercell interconnects. However, intracell interconnects often have unidirectional currents and are potentially susceptible to EM. Traditional EM design rules are constructed to guarantee a low probability of chip failure even in the worst case of all interconnects having maximum allowable currents. Taking into account the fact that, in modern VLSI chips, the total number of interconnects can reach as many as hundreds of millions, these EM design rules should be very stringent. A statistical EM budgeting methodology (SEB) was proposed to estimate the risk of EM failure due to the actual distribution of the current density [1]. Following this methodology, a more recent study showed that a design rule approach is overly pessimistic because many wires have current densities significantly lower than the maximum specified by guidelines [2]. This approach was proven to be very successful for full-chip EM analysis. Another well-known EM phenomenon is the stress-induced backflow [3]. Experiments show that short wires are significantly less susceptible to EM and can safely conduct a much higher current than long wires of the same width and thickness. EM moves ions from one side of the wire to the other. This creates mechanical stress in the wire that in turn creates mass flux in the direction opposite to the EM-induced flux. If the mechanical stress due to EM is less than a certain critical value, these two fluxes are well balanced and the wire has no
0278-0070/$20.00 © 2006 IEEE
HAZNEDAR et al.: IMPACT OF STRESS-INDUCED BACKFLOW ON FULL-CHIP ELECTROMIGRATION RISK ASSESSMENT
Fig. 1.
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EM in a wire segment. (a) Wire with electric current. (b) Wire cross section. (c) Material displacement due to electric current and mechanical stress.
significant voids or hillocks, which signifies a virtually eternal lifetime for the wire. If the mechanical stress is higher than the critical value, EM defects grow and the wire will eventually have an EM failure. The stress-induced backflow phenomenon can be utilized to reduce pessimism in the EM analysis. All the wires that are not susceptible to EM due to this effect can potentially be excluded when computing the probability of chip failure and its lifetime. The maximum wire length that can conduct a given current without EM violation is called the critical length [3]. For different current densities, the value of the critical length is different. For straight and uniform wire segments, it is known that the product of the critical length and the current density is constant. However, most interconnect structures used in VLSI chips are significantly more complex than a uniform wire segment. Moreover, the current density in different wire segments of the same interconnect structure is different, as different wire segments can be of different widths and carry different amounts of current. Therefore, the estimation of stress-induced backflow is significantly more complicated for complex interconnect structures and especially for structures with loops (meshes). An accurate and compact model for computing mechanical stress due to EM is necessary for developing computer-aided design (CAD) tools targeted for full-chip analysis. One of the most suitable theoretical models of EM for CAD implementation was proposed in [3], [4], and [13]. This model was based on differential equations describing the migrations of metal ions and vacancies as fluid–gas systems. In this paper, we present a methodology suitable for developing a full-chip EM analysis tool, which assesses the impact of the critical length effect at the chip level. In order to be able to handle large high-performance microprocessor chips with hundreds of million nets, we utilize a linear approximation of the aforementioned differential equations. We consider an interconnect wire structure consisting of all edges in the same layer that are connected together as a single object where EM failure may occur. We show that for straight-line and tree-like structures, an EM model, which assumes a hydrostatic stress state at each position in the segment, provides a well-defined and consistent linear system of equations. The solution of this system for the
given current densities provides values for mechanical stress in wires due to EM. By comparing these with the critical values, one can assess the EM risk of the circuit. Interconnect structures without EM risk are excluded from further analysis. All the other wires are analyzed by our SEB methodology [2]. We also demonstrate that for mesh interconnect structures the system of mechanical stress equations is incompletely defined. Therefore, there is a need to develop a technique transforming it into a completely defined linear system of equations with a unique solution. This transformation is again based on the same model of hydrostatic mechanical stress due to EM. We have implemented the proposed technique of stressinduced backflow calculation in our full-chip EM analysis tool [5]. All interconnects wherein the mechanical stress is below the critical level for EM failure are filtered out to reduce pessimism in EM risk assessment. The methodology has been successfully employed for EM analysis of high-performance microprocessor chips. The rest of the paper is organized as follows. Section II presents the main assumptions, equations, and their solutions of a hydrostatic model of mechanical stress due to EM for uniform and straight wire segments using the basics of the theory of elasticity. In Section III, we apply the proposed model to treelike interconnect structures. Section IV shows that the system of equations presented in Section II is incomplete and can have many solutions for mesh interconnect structures. Using this analysis, we develop a system of equations with a unique solution. In Section V, we give details of an implementation of the proposed technique and present some experimental data. Section VI discusses future work. In Section VII, we draw our conclusions. II. H YDROSTATIC M ODEL OF M ECHANICAL S TRESS Fig. 1 shows a wire segment with electrical current flowing from the right side of the wire to its left. Electrons hit Cu ions of the metal wire and push them in the direction opposite to the electrical current. The ion movement results in variation of the metal density along the wire from values higher than normal (compression) at the right hand side of the wire to values lower
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than normal (tension) at its left hand side. This density variation creates a mechanical stress gradient along the wire. The tensile stress has positive values whereas the compressive stress has negative values in accordance with the convention employed in the theory of elasticity. The nonzero stress gradient leads to a metal-ion flux in the direction opposite to the original ion flux. Then, the balanced state is described by the differential equation of equilibrium [3] jρq = Ω
dσ dx
(1)
where j is the current density flowing through the wire, ρ is the metal resistivity, q is the effective charge of the metal ion, Ω is the atomic volume, and dσ/dx is the gradient of the mechanical stress σ. Combining all constant terms, we obtain the differential equation for stress along the wire in equilibrium dσ = cj dx
(2)
where c = ρq/Ω. In modern VLSI interconnects, Cu wires are enclosed in dielectrics such as pure or C-doped SiO2 . At sufficiently high stress values, induced by ion diffusion, voids or hillocks can result in EM failure. However, we are interested in analyzing the range of stresses significant enough to affect the metal wire but small enough not to create a failure. We analyze the situation when there is no void or hillock formation, but they may occur, if we continue to increase the current and hence the mechanical stress. If the stress exceeds a certain critical value, a void is formed at the end of the wire. The failure usually takes place at the end of the interconnect where maximum tension occurs. Thus, we have a current-induced flux creating a stress-directed counterflux in a thin and narrow interconnect line embedded in a surrounding dielectric continuum and with blocking boundaries located at the ends of the line. The Cu diffusion is inhibited at contact and via sites through the use of tungsten-based plugs for the contact case and tantalumbased barrier layers for the via case. Both materials are highly stable, refractory metals, and have negligible diffusivities for Cu. This stress-induced backflow retards EM damage, and below a critical trace length, the EM flux is entirely balanced by the stress-directed backflow of ions. This behavior allows us to employ the theory of elasticity to formalize the system in a simple and computationally efficient way as follows. A material put under load deforms. If the load increase leads to a proportional increase in deformation, the material is linear. If the material, when unloaded, returns to its original shape, it is also elastic. When a body is loaded, the original coordinates of all its points move to a new position. Finding their displacement determines all the strains and the stresses causing them. The displacement vector of a point A moving to another point A has components in the x, y, z directions, which are usually called u, v, w. Under a linear transformation, geometric shapes retain their basic identity: straight lines remain straight. However, such a linear transformation may involve volume change (isotropic effect), distortion (shear or
deviatoric effect), and rotation. Displacement fields caused by boundary loads or similar perturbations to the initial condition are usually nonlinear; the fundamental linear assumption of calculus, however, permits us to use the relations of finite linear transformation in describing the relative displacement (i.e., deformation) du, dv, dw of differential elements dx, dy, dz. This depiction involves a tensor of second order. Since any tensor can be resolved into symmetric and asymmetric components where symmetry or asymmetry is with respect to the diagonal when the tensor is represented in matrix form, the aforementioned effects can be seen separately when the tensor is decomposed into its component parts. On a differential scale, then, as long as u, v, and w are continuous and small, we have the total derivative expressed in terms of the strain (deformation) tensor as ∂u ∂u ∂u dx du ∂x ∂y ∂z ∂v ∂v ∂v dv = (3) ∂x ∂y ∂z dy . ∂w ∂w ∂w dz dw ∂x
∂y
∂z
Splitting the strain tensor into its symmetric and asymmetric components yields [6] ∂u ∂u ∂u
∂x ∂v ∂x ∂w ∂x
∂y ∂v ∂y ∂w ∂y
∂z ∂v ∂z ∂w ∂z
1 2
∂u ∂x
∂v + ∂u = 12 ∂x ∂y
1 ∂w ∂u 2 ∂x + ∂z
∂u ∂y
∂v ∂x
+
∂v ∂y
1 2 1 2
∂u
1 ∂w ∂v 2 ∂y + ∂z εij , symmetric strain tensor
0
∂v + 12 ∂x − ∂u ∂y
1 ∂w ∂u 2 ∂x − ∂z
1 2
∂u ∂y
− 0
∂v ∂x
∂z
+
∂w ∂x
∂v ∂z
+
∂w ∂y
∂w ∂z 1 2
1 2
1 ∂w ∂v 2 ∂y − ∂z asymmetric strain tensor
∂u
∂z
∂v ∂z
−
∂w ∂x
−
∂w ∂y
0
.
(4) The symmetric portion is further decomposed into isotropic and deviatoric components εij = εm (isotropic strain tensor) + eij (deviatoric strain tensor)
(5)
where εm =
1 (εx + εy + εz ). 3
(6)
This uncoupling of the tensor into isotropic and deviatoric parts directly corresponds to the fundamental physical reality of material behavior under load. Each individual element of the symmetric strain tensor produces the normal or hydrostatic strain, i.e., the deformation of the orthogonal differential base length dx, dy, and dz with respect to finite base lengths x, y, and z when u, v, and
HAZNEDAR et al.: IMPACT OF STRESS-INDUCED BACKFLOW ON FULL-CHIP ELECTROMIGRATION RISK ASSESSMENT
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w are linear functions. In IC interconnects, the load is the electrical current and it flows in one dimension; thus, there is no rotation involved and the tangential shear effect can safely be assumed to be negligible for the wear out mechanism under consideration. Therefore, the strain tensor of order two is reduced to a simple uniaxial scalar (i.e., a tensor of order zero). Strain εx is the individual diagonal element in the x-direction in the symmetric component of the tensor in (4). It produces a deformation of the differential base length dx εx =
du ∂u = ∂x dx
(7)
where u is the displacement in the x-direction due to deformation. On the other hand, stress is defined as the limiting value of average force per unit area as the cross-sectional area approaches zero [7]. Similar to the strain tensor, the stress tensor has symmetric isotropic and asymmetric deviatoric components. The isotropic component is essentially scalar, having only magnitude in all principal directions. The mean stress σm
1 = (σx + σy + σz ) 3
σx M
(8) 0
(9)
where the constant M is the experimentally determined modulus. In practice, an appropriate bulk modulus is used, as explicated in [8]. Note that the fundamental assumption in this discussion is that the displacements are small, continuous, and smooth. Thus, over differential base lengths, deformations are linear and elasticity yields a linear stress–strain relationship. When this is no longer the case, peculiarities develop in the mathematical displacement field, corresponding to physical voids and hillocks in metals, a condition defined as yield, which signifies the end of the elasticity domain. Then, the theory of plasticity takes over. Once this occurs, the structure is permanently deformed and lifetime is drastically reduced. In interconnects, this corresponds to EM failures. If the wire cross-section is constant, integrating (2) leads to an expression for the hydrostatic stress as a function of distance σ(x) = cjx + σ0
(10)
where σ0 is the stress at the reference node. From (7) and (9), we also have du =
1 σ(x)dx M
which, upon integration over the length of the wire segment, yields
is the hydrostatic pressure if negative and causes only volume change. The deviatoric component causes only distortion or shear with no volume change. In a state of hydrostatic pressure, Hooke’s Law gives the strain–stress relationship as εx =
Fig. 2. Single-layer net fragment. (a) Net fragment. (b) Its graphical representation.
(11)
1 du = M
σ(x)dx
(12)
0
1 u − u0 = σ0 + cj. M 2M
(13)
But, from (10), cj = σ − σ0 . Substituting this into (13) and simplifying, we get u − u0 =
(σ + σ0 ). 2M
(14)
For any point where several wire segments are connected together, the law of conservation of mass is valid as well. Assuming that the volume of the internal node connected to several wire segments is negligibly small to accumulate any amount of material, the law of conservation of mass expresses the simple fact that the net amount of material coming from all wire segments is zero. Assuming that all wire segments have the same thickness, this is expressed by
wi ui = 0
(15)
where wi is the width of the ith segment. III. M ECHANICAL S TRESS E QUATIONS FOR A T REE L AYOUT Fig. 2 shows a net fragment lying on a single layer and its graph model G(N, E), where N = {ni } is a set of nodes and E = {ej } is a set of edges ej = (nj1 , nj2 ). Each wire segment is modeled by a directed edge. The edge direction indicates the direction of the positive electrical current and mass displacement. For each edge em = (ni , nk ), we know the length m and width wm and the density jm of the electrical current flowing through it.
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Using the mechanical stress model described above by (10), (14), and (15), we can construct the following system of equations. 1) Stress equations describe the relation between the electric current density jm flowing through an edge em = (ni , nj ) and the mechanical stress values at the source and sink nodes ni , nj of the edge, i.e., σj − σi = cm jm
(16)
where c is the coefficient in (2) defined by the physical properties of the wire material. 2) Displacement equations describe the relation between mechanical stress values σi , σj at the source and sink nodes ni , nj of the edge em = (ni , nj ) and the wire material mass displacement ui , uj at the source and sink ends of the edge, i.e., uj − ui =
m (σj + σi ). 2M
(17)
3) The law of conservation of mass states that for each node ni of the directed graph, taking into account the direction of the edges and denoting the incoming edge as positive, the amount of incoming and outgoing displacements is always the same, i.e., ep ∈IN(ni )
wp up −
wq uq = 0
Fig. 3. Layout structure with a loop. (a) Fragment of a net layout. (b) Its graph model.
(18)
eq ∈OUT(ni )
where IN(ni ) is a set of incoming edges at node ni , OUT(ni ) is a set of outgoing edges from node ni , ep and eq are incoming and outgoing edges incident to node ni , up and uq denote wire material mass displacement at the incoming and outgoing edges, respectively, and wp , wq are the widths of the respective wire segments. Equation (18) neglects the accumulation of material in internal nodes with multiple wire segments, which is quite a valid assumption, because the node volume is usually much smaller than that of the wire segments. Moreover, this volume is partially included in the wires. From the above construction, it is clear that the number of stress equations in (16) is the same as the number of displacement equations in (17) and is equal to the number of graph edges NE . The number of equations in (18) equals the number of graph nodes NN . Therefore, the total number of unknown variables is 2NE + NN . The number of stress variables equals the number of graph nodes NN . The number of displacement variables ui and uj equals 2NE , twice the number of graph edges. Consequently, the total number of unknown variables is equal to the number of equations. For tree-like layout structures, (16)–(18) are independent of each other and the whole system has a unique solution. Equation independence can be proven by induction using the properties of trees [2]. It is obvious for wire structures consisting of a single wire segment. Assuming that the equations are independent for a tree T , consisting of K edges, it is not difficult to show the independence of the equations for a tree
Fig. 4.
Loop of wires e1 , e2 , . . . , ek .
with K + 1 edges, constructed by connecting a wire segment to an arbitrary node of a tree T . IV. M ECHANICAL S TRESS E QUATIONS FOR A M ESH L AYOUT For the mesh layout with loops of wires, however, the above system of mechanical stress equations (16)–(18) is not independent. Fig. 3(a) shows an example of a layout with a loop of wires. A graph model of this layout is shown in Fig. 3(b). For this example, we shall show that the stress equations (16) are linearly dependent and displacement equations (17) are incomplete, i.e., combined with other equations, they do not define unique values for mass displacements. We will show how to modify the original system of mechanical stress equations (16)–(18) to make it well defined to produce a unique solution. A. Linear Dependence of Stress Equations The first problem occurs with stress equations in (16). Assume that we have a loop with nodes n1 , n2 , . . . , nk and edges e1 = (n1 , n2 ), e2 = (n2 , n3 ), . . . , ek−1 = (nk−1 , nk ), ek = (nk , n1 ), as shown in Fig. 4. Then the mechanical stress equations for edges of this loop are given as σ2 − σ1 = c1 j1 σ3 − σ2 = c2 j2 .. . σk − σk−1 = ck−1 jk−1 σ1 − σk = ck jk .
(19)
HAZNEDAR et al.: IMPACT OF STRESS-INDUCED BACKFLOW ON FULL-CHIP ELECTROMIGRATION RISK ASSESSMENT
Summing up all the equations except the last one, we obtain σk − σ1 = c
k−1
p jp .
(20)
p=1
The left hand side of this equation differs from the left hand side of the last equation of the system in (19) by its sign only. Thus, the equation set (19) is not independent. We need to analyze the right hand side of (20) and compare it with the right hand side of the last equation of the system represented by (19). Using Ohm’s law for each edge ep and the corresponding wire segment, we can express the current density jp flowing through the edge as jp =
vp − vp+1 vp − vp+1 = wp rp ρs p
(21)
where νp and νp+1 are the node potentials at np , np+1 ; rp , wp , p are the resistance, width, and length of the wire segment, respectively; and ρs is the wire metal sheet resistance, which is the same for all wires, since they are on the same layer. Substituting (21) for current density in (20) and performing obvious algebraic simplifications, we obtain σk − σ1 =
c (v1 − vk ). ρs
(22)
Similarly, substituting (21) for the current density in the last equation of system in (19), we get σ1 − σk =
c (vk − v1 ). ρs
(23)
This equation is exactly the same as (22). Therefore, it proves that, for the loop, the system in (19) is consistent, but its equations are not independent. One of its equations is a logical consequence of all the others and should be removed from the system. From the above considerations, it is clear that the equation to be removed can be selected arbitrarily from the stress equations for the nodes in the loop so that the loop is broken. However, the system of mechanical stress equations for a layout with a loop then becomes underdetermined.
Each added increment in this vector is defined as ∆up ≡
∆u wp
∆u = −u1s wp
(24)
where ups and upf are mass displacements at the source and sink ends of the edge ep , respectively, with 1 ≤ p ≤ k. Using (24), we form a new vector of mass displacements as U = (u1s + ∆u1 , u1f + ∆u1 , . . . , uks + ∆uk , ukf + ∆uk ). (25)
(27)
which is equivalent to adding u1s = 0
The second problem occurs with displacement equations in (17). We again consider a loop of nodes and wires, as shown in Fig. 4. Assume that the solution of mechanical stress equations (16)–(18) includes the vector of mass displacements for edges forming the loop, i.e.,
(26)
where ∆u is an arbitrary value selected to be the same for all ∆up . Then, (25) satisfies (17) and (18). Equations in (17) are satisfied because the mass displacements at the sink and source of an edge are modified by the same value. Equations in (18) either include no modified values of displacements or include them in pairs: one with a positive and the other with a negative sign corresponding to incoming and outgoing loop edges at a node. The value added to each displacement is inversely proportional to the corresponding wire width in (26). Therefore, these added values ∆up wp cancel each other in (18), corresponding to the loop nodes ni , and any solution in the form of (25) constructed from its valid solution satisfies all the mechanical stress equations. This rather unexpected phenomenon has a very simple physical explanation. Our model of mechanical stress assumes that the metal wire at EM stress values behaves as a fluid. However, fluid can flow in loop pipes without any additional pressure or tensile stress. This is exactly equivalent to our conclusion that any valid displacement solution can be modified in the way specified by (25) and (26). Of course, in real wire loops, no rotation flow of wire material occurs because adhesion of wire material (Cu and barrier) to the dielectric shell surrounding it and the corresponding tangential stress prevents this rotation. However, according to modern theory of EM [3], [4], [13], this stress component is negligibly small compared with compressive and tensile stresses. Therefore, we ignore it in our computations. As a result, we have to impose additional restrictions on mass displacement in order to make our equations have a unique solution. For convenience, we select the constant ∆u as
B. Incompleteness of Displacement Equations
U = (u1s , u1f , u2s , u2f , . . . , uks , ukf )
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(28)
to the original system of mechanical stress equations (16)–(18). Adding (28) prevents mechanical stress equations (16)–(18) from having multiple solutions due to the rotation flow of the wire material, which, in reality, is prohibited by adhesion of wire material to the dielectric, as explained above. C. General Mesh Layouts We have shown that for a layout with a single loop, one of the stress equations in (16) for loop nodes is linearly dependent on the others and should be removed from the system. Furthermore, to make the system of equations completely determined, it is necessary to correct the mass displacement at one of the loop wires.
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Fig. 7. Graph model with a floating limb attached at various points of the metal line (a) anode, (b) middle, and (c) cathode.
Fig. 5. Example of a mesh layout and its graph model with four fundamental loops. (a) Net fragment. (b) Graph representation of the fragment’s spanning tree T . Branches {b1 , . . . , b10 } are shown with solid lines and chords {c1 , c2 , c3 , c4 } with dashed lines.
Fig. 6. Algorithm for constructing a system of mechanical stress equations for mesh structures.
Fig. 5 shows an example of a multiloop mesh layout and the corresponding graph model. For loop analysis, it is more convenient to use nondirected graphs. Edge directions are required only for constructing mechanical stress equations and can be selected in an arbitrary way. They affect only signs of coefficients in the system of equations. From graph theory [9], it is known that it is always possible to construct a fundamental set of loops S = {L1 , L2 , . . . , Lr } such that any two loops Li and Lk from this set differ at least by one edge and none of the loops is a linear combination of the other loops. Moreover, any other loop of the graph is a combination of fundamental loops. A fundamental set of loops can be constructed as follows: 1) build a spanning tree of the graph; 2) construct for each chord ci (edge outside of the spanning tree), the corresponding fundamental loop by combining this chord with the required spanning tree branches bk . The algorithm for constructing mechanical stress equations for a general mesh layout is shown in Fig. 6. It starts by constructing the system of mechanical stress equations (16)–(18), ignoring issues related to the layout loops. Then the algorithm transforms the constructed system into a correct one by removing dependent stress equations and adding required displacement equations.
V. I MPLEMENTATION AND R ESULTS We have implemented the proposed stress-induced backflow calculation in a full-chip EM analysis software that implements the SEB as well. The software takes extracted parasitic and device netlists as the input, which are back annotated with geometrical information, such as wire segment widths and lengths, and metal layers. From the input netlists, wire segments that are contiguous on the same metal layer are identified. For each of these wire segments, the worst-case (i.e., maximum) average current is computed, which is then used for mechanical stress calculations at the blocking boundaries of each wire segment, i.e., at via and contact interfaces. During this calculation, the spanning tree-based algorithm, as described in Section IV-C, is applied to detect any loop. Generic matrix packages are used for the solution of the linear system of equations during current density and mechanical stress computations. As an example of mechanical stress computation, floating limbs are attached to various places of a single wire segment, as shown in Fig. 7, and the calculated stress values are summarized in Table I. The metal-ion movement due to the electron wind results in a higher metal density at the anode side of the wire that creates compressive stress, whereas the lower metal density at the cathode leads to tensile stress. When the limb is attached to the anode (node a), the metal ion will move from the “active” region into the “inactive floating limb region” and the stress level at the anode will be lower than the one without a limb. In contrast, the stress level at the cathode (node c) will be higher because the effective length of the total metal line becomes longer. However, if the floating limb of the same length is attached to the cathode, the calculated stress values are exactly the opposite of the previous case. When the floating limb is attached exactly in the middle (node b) of the line, the stress value at this point becomes zero because of the symmetry and mass conservation. The floating limb has no stress gradient since there is no current flowing through it. The constant c in (2) is estimated to be 2.5 MPa−µm/mA. When the length of the limb is varied, the stress values at each node are changed, as shown in Fig. 8. When the limb length at cathode is increased, the tensile stress at cathode decreases, whereas the compressive stress at anode increases. On the contrary, as the length of the limb attached to the anode is elongated, the tensile stress at the cathode increases, while the compressive stress at the anode decreases. The limb attached at the middle does not affect the stress value at all, as expected.
HAZNEDAR et al.: IMPACT OF STRESS-INDUCED BACKFLOW ON FULL-CHIP ELECTROMIGRATION RISK ASSESSMENT
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TABLE I CALCULATED STRESS VALUES AT EACH NODE WHEN A FLOATING LIMB IS ATTACHED AT DIFFERENT NODES
VI. F UTURE W ORK The implementation of the stress calculator for full-chip power grid analysis is currently underway. Before one can assume that the critical length effect leads to essentially infinite lifetime of the signal and clock nets, its experimental validation under high-frequency pulsed-DC operation in Cu-based interconnects has to be carried out. Work is currently in progress for this purpose. Initial wafer-level results using pulsed-DC currents on actual test structures, conducted at an ambient temperature of 300 ◦ C and with moderate effective current densities, indicate that short interconnect lines behave as expected, assuming an “effective DC” critical length effect. Furthermore, the effect of the superposition of thermal stresses—on the order of almost 400 MPa [12]—and EM-induced stresses needs to be evaluated. Both stress relaxation and void growth kinetics need to be taken into account and experimental data should be extrapolated to 105 ◦ C operating conditions to ensure that the critical length effect is indeed operative at long chip lifetimes. Fig. 8. Stress values at anode and cathode are calculated as a function of limb length.
This simple example demonstrates that attaching a floating limb at a critical node can be useful to control the mechanical stress. The full-chip EM risk assessment has been applied to a high-performance microprocessor for embedded applications at a junction temperature of 105 ◦ C. The analysis, including mechanical stress computations, took about an hour on three Unix workstations running in parallel. This design contains more than 56 million transistors. Signal and clock nets were treated separately from the power grid. The chip-level results for signals and clocks indicate that the highest EM-induced stress is in the order of 140 MPa, both in tension and compression, leading to a maximum stress difference of 280 MPa between blocking boundaries. It was found that segments with the highest current density values were relatively short. The critical current density × length product (jl)∗ under DC conditions was measured to be about 3700 A/cm for the metallization used for the microprocessor described in this study [10]. With a lower bound on (jl)∗ of 3000 A/cm and an estimated effective charge value Z ∗ (q = Z ∗ e, where e is the electronic charge) close to unity at 105 ◦ C [11], the highest stress difference between wire segment ends is on the order of 750 MPa. This value is higher than the calculated 280 MPa from the chip analysis, indicating that the critical length effect, if applicable for non-DC signals under the assumption of an effective current model, should prevent all interconnects on the signal and clock circuits from EM failures.
VII. C ONCLUSION We described here an efficient and accurate technique of EM risk analysis taking into account the critical length effect, which plays a very important role in EM phenomena in shortwire structures. The proposed technique can handle general (tree and mesh) layout structures and is suitable for full-chip analysis. Our approach is based on computing mechanical stress caused by electrical current in copper-wire structures. Using basic concepts of the theory of elasticity, we showed that hydrostatic stress can be efficiently computed for EM risk assessment by solving a system of linear equations. We developed an efficient algorithm for constructing this system for general (tree and mesh) layout structures that describes relations between stress and material displacement in copper wires with high-density electrical current. The hydrostatic model assumed an equiaxial stress state. It was shown that this approach results in an incomplete system of equations in mesh structures. In this case, it is possible to change the system to a fully determined one by introducing an additional equation to compute correct values of hydrostatic mechanical stress. R EFERENCES [1] J. Kitchin, “Statistical electromigration budgeting for reliable design and verification in a 300-MHz microprocessor,” in IEEE Symp. VLSI Circuits, Kyoto, Japan, 1995, pp. 115–116. [2] C. Oh, H. Haznedar, M. Gall, A. Grinshpon, V. Zolotov, P. Ku, and R. Panda, “A methodology for chip-level electromigration risk assessment
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and product qualification,” in Proc. 5th Int. Symp. Quality Electronic Design (ISQED), San Jose, CA, 2004, pp. 232–237. I. A. Blech, “Electromigration in thin aluminum films on titanium nitride,” J. Appl. Phys., vol. 47, no. 4, pp. 1203–1208, Apr. 1976. J. J. Clement, S. P. Riege, R. Cvijetic, and C. V. Thompson, “Methodology for electromigration critical threshold design rule evaluation,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 18, no. 5, pp. 576– 581, May 1999. C. Oh, D. Blaauw, M. R. Becer, V. Zolotov, R. Panda, and A. Dasgupta, “Static electromigration analysis for signal interconnects,” in Proc. 4th Int. Symp. Quality Electronic Design (ISQED), San Jose, CA, 2003, pp. 377–382. R. Richards, Jr., Principles of Solid Mechanics. Boca Raton, FL: CRC Press, 2001. P. C. Chou and N. J. Pagano, Elasticity: Tensor, Dyadic, and Engineering Approaches. Princeton, NJ: Van Nostrand, 1967. R. G. Filippi, R. A. Wachnik, C.-P. Eng, D. Chidambarrao, P. C. Wang, and J. F. White, “The effect of current density, stripe length, stripe width, and temperature on resistance saturation during electromigration testing,” J. Appl. Phys., vol. 91, no. 9, pp. 5787–5795, May 2002. N. Deo, Graph Theory With Applications to Engineering and Computer Science. Englewood Cliffs, NJ: Prentice-Hall, 1974. S. Thrasher, M. Gall, C. Capasso, P. Justison, R. Hernandez, T. Nguyen, and H. Kawasaki, “Examination of critical length effect in copper interconnects with oxide and low-k dielectrics,” in Proc. 7th Int. Workshop Stress-Induced Phenomena, Austin, TX, 2004, pp. 165–172. R. Rosenberg, D. C. Edelstein, C.-K. Hu, and K. P. Rodbell, “Copper metallization for high performance silicon technology,” Annu. Rev. Mater. Sci., vol. 30, pp. 229–262, Aug. 2000. D. Gan, G. Wang, and P. S. Ho, “Effects of dielectric material and line width on thermal stresses in Cu lines,” in Proc. IEEE Int. Interconnect Technical Conf., Burlingame, CA, 2002, pp. 271–273. W. Schoenmaker and V. Petrescu, “Modeling electromigration as a fluid–gas system,” Microelectron. Reliab., vol. 39, no. 11, pp. 1667–1676, Nov. 1999.
Haldun Haznedar (S’78–M’82) received the B.S. degree in electrical engineering from the Middle East Technical University, Ankara, Turkey, in 1975, the M.S. degree in electrical engineering from the University of Alabama, Hunstville, in 1977, and the Ph.D. degree in electrical engineering from the University of Alabama, Tuscaloosa, AL, in 1981. After working in the academia for seven years, he joined Texas Instruments in 1990 and Motorola in 2001, and has been involved in the development of computer-aided design (CAD) tools and methodology for high-performance IC designs. In 1991, he published Digital Microelectronics, an advancedundergraduate textbook, and holds one U.S. patent. His interests lie in all aspects of CAD and intrinsic-reliability engineering as well as the Philosophy of Mind. Dr. Haznedar is a member of the Tau Beta Pi.
Martin Gall received the M.S. degree (Diplomphysiker) in physics from the RheinischWestfaelische Technische Hochschule Aachen, Germany, in 1992 and the Ph.D. degree in materials science and engineering from The University of Texas, Austin, in 1999. Most of his dissertation work was conducted at Motorola’s Advanced Products Research and Development Laboratory. In 1995, he joined Freescale Semiconductor, Inc./Motorola, Austin, TX, and has been working in the area of backend reliability, mainly addressing issues with electromigration and stress-induced voiding. In mid-1999, he joined The Technical University at Delft (Netherlands) for a one-year assignment as a Visiting Scientist. Upon his return to Freescale Semiconductor, Inc./Motorola, he continued backend reliability development for the 130- and 90-nm technology nodes. Since 2002, he has been leading the interconnect reliability team at the Technology Solutions Organization, mainly focusing on implementation of advanced low-k dielectrics. He (co)authored over 30 papers and serves as a technical committee member or reviewer for leading conferences and journals.
Vladimir Zolotov (M’97–SM’04) received the M.S. degree in electrical engineering from the Moscow Institute of Electronics, Moscow, Russia, in 1977, and the Ph.D. degree in electrical engineering from the Scientific Research Institute of Micro Devices, Moscow, Russia, in 1988. He was previously with Motorola Inc., where he was involved in the development of EDA tools and methodology for high-performance and low-power very large scale integration (VLSI) designs. He is currently a Research Staff Member at the IBM T.J. Watson Research Center, Yorktown Heights, NY, where he is working on statistical static timing analysis. His research interests include statistical timing, signal integrity, fast circuit simulation, reliability analysis, on chip inductance, and optimization of VLSI.
Pon Sung Ku (M’97) received the M.S. degree in electrical engineering from the University of Arizona, Tucson, and the Ph.D. degree in electrical engineering from the Arizona State University, Tempe, in 1986 and 1995, respectively. In 1986, he joined IBM General Product Division, San Jose, and developed a test system for magnetic hard drive testing. Since joining the Motorola Semiconductor Products Sector in 1994, he has worked in the area of Si IC reliability and technology modeling. He is currently the Manager of the Advanced Reliability Engineering Team in Freescale Semiconductor, Inc., Phoenix, AZ. His main research area is the design for reliability and device reliability. Dr. Ku is a member of the IEEE Electron Devices Society.
Chanhee Oh (S’87–M’95) received the B.S. degree in control and instrumentation engineering from Seoul National University, Korea, in 1987 and the M.S. and Ph.D. degrees, both in electrical engineering, from the University of Texas, Austin, in 1989 and 1995, respectively. Prior to joining Freescale Semiconductor, Inc., Austin, TX, he was with a microprocessor development group at Advanced Micro Devices, Austin, TX. From 1997 to 2004, he was with Freescale Semiconductor, Inc., where he led internal development of EDA solutions for high-performance very large scale integration (VLSI) designs. Since 2004, he has been with Nascentric Inc., Austin, TX, where he holds a technical leadership position for research and development of high-speed circuit simulation and analysis tools. He has over 20 technical publications and holds a U.S. patent. His research interests include signal integrity, circuit simulation, reliability, timing analysis, and optimization of VLSI circuits.
Rajendran Panda (M’97) received the B.E. degree (Honors) in electrical and electronics engineering from Madurai University, India, in 1978, the Bachelor of Laws (LL.B.) degree from Bangalore University, India, in 1984, and the Ph.D. degree in computer science from the University of Illinois at Urbana-Champaign, in 1996. From 1978 to 1991, he was a practicing Electrical Engineer at Bharat Heavy Electricals Limited, India, specializing in utility systems, industrial controls, and automation systems. Since 1996, he has been with Freescale Semiconductor, Inc., Austin, TX (the erstwhile Semiconductor Products Sector of Motorola), where he is currently managing a computeraided design (CAD) research and development team. He has published over 40 journal and conference papers, including two best papers, and presented tutorials and invited talks on these topics. His research interests include very large scale integration (VLSI) power distribution, signal integrity, and lowpower high-performance design issues. Dr. Panda is currently serving in the technical program committees of the International Conference on Computer Aided Design (ICCAD), the International Symposium on Quality Electronic Design (ISQED), and the Design, Automation and Test in Europe (DATE) conferences.
