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Microelectronics Journal 44 (2013) 80–85
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Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models Muthupandian Cheralathan a,n, Esteban Contreras b, Joaquı´n Alvarado c, Antonio Cerdeira b, ˜ iguez a Giuseppe Iannaccone d, Enrico Sangiorgi e, Benjamin In a
DEEEA, Universitat Rovira i Virgili, 26 Av. Paisos Catalans, Tarragona 43007, Spain SEES, CINVESTAV, Av. IPN No.2508, Apto. Postal 14-740, 07360 DF, Mexico c ´noma de Puebla, 72570 Puebla, Me´xico CIDS, Beneme´rita Universidad Auto d Department of Information Engineering, University of Pisa-IU.NET, Pisa, Italy e ARCES, University of Bologna-IU.NET, Cesena, Italy b
a r t i c l e i n f o
a b s t r a c t
Article history: Received 6 July 2012 Received in revised form 2 November 2012 Accepted 14 November 2012 Available online 31 December 2012
In this paper we present the results of the implementation of a nanoscale double-gate (DG) MOSFET compact model, which includes hydrodynamic transport model, in Verilog-A in order to carry out circuit simulation. The model in Verilog-A is used with the SMASH circuit simulator for the analysis of the DC and transient behavior electrical CMOS circuits. Template devices representative for a downscaled symmetric double-gate MOSFET was used to validate the models for n-channel and p-channel. A CMOS inverter and a ring oscillator have been analyzed. Comparison of its performance between the drift-diffusion (DD) and hydrodynamic transport model within the practical range of bias voltages has been highlighted. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Double-gate MOSFET Hydrodynamic Verilog-A SMASH
1. Introduction The device-scaling concept has been the main guiding principle of the MOS-device engineering over the past few decades [1]. As the conventional bulk MOSFET technology is scaling down towards the practical limit, DG MOSFETs appeared as a promising technological alternative that has attracted substantial research interests due to superior short channel control, volume inversion, etc. There has been work dedicated to modeling and simulation of DG MOSFETs. Compact core models for undoped and doped symmetric DG MOSFETs have been presented, even using new artificial intelligence based approaches [2–7]. The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. Accurate and time computationally efficient compact models of DG MOSFETs are required to predict or simulate circuit performance. For a circuit simulation the main task is to have a precise transistor model to reproduce the transistor behavior, which is either already introduced or can be implemented in the commercial circuit simulators to be used. In
n
Corresponding author. E-mail addresses: [email protected], [email protected] (M. Cheralathan). 0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2012.11.006
recent years, some work has been done on the implementation of DG MOSFET compact models in circuit simulators [8–11]. In this work, we present the implementation of a DG MOSFET compact model including hydrodynamic transport model in Verilog-A for circuit simulators. The model is based on an analytical expression that models the variation of surface potential as well as the difference of potential at the surface and at the middle of the silicon layer [2]. This model for the potentials is used in an analytical compact model for the drain current of a double-gate MOSFETs derived from a core charge control model which results from the solution of the 1D Poisson’s Eq. (3). Electrostatic short-channel effects (threshold voltage roll-off, DIBL, subthreshold swing degradation) were introduced in the core model using scalable and geometry dependent equations. This model is valid from lightly doped to highly doped devices [3]. We extended this model to include hydrodynamic transport model [12]. The extended model includes a gate dielectric thickness correction [13] and also a threshold voltage correction [14] through which the quantum effects are taken into account. Besides, charge and capacitance models consistent with the DC model were developed. In [12] we validated this model for n-channel DG MOSFETs by comparison with numerical simulations obtained using advanced transport models. In this paper, first of all, we extend this model to p-channel devices and we validate it by comparison with numerical simulations based on
M. Cheralathan et al. / Microelectronics Journal 44 (2013) 80–85
advanced transport models. The entire models for n-channel and p-channel devices is implemented in Verilog-A, which allows the use of the model in commercial circuit simulators for circuit design of both digital and analog applications. We have shown examples of DG MOSFET based CMOS circuits namely, an inverter and a ring oscillator. Finally, we compare results between driftdiffusion and hydrodynamic transport models within the practical range of voltages.
2. Device and approaches The 22 nm template transistor we considered is shown in Fig. 1. The 22 nm DG MOSFET with a gate length of 22 nm, a gate stack consisting of 2.4 nm of HfO2 on top of 0.7 nm of SiO2 (EOT¼1.1 nm). The silicon film thickness is 10 nm. The channel is undoped (1015 cm 3). We have considered both n-channel and p-channel DG MOSFETs with these dimensions. The main features of each transport models (represented with the acronym of the main developer) are presented. The modeling approaches can range from modifications of the conventional drift-diffusion (DD) model used in commercial TCAD tools to advanced Monte Carlo (MC) models. The numerical models used by the different groups [13–22] differ in terms of scattering models, simulation approaches, etc. For comparison, all simulators have been first calibrated to reproduce the characteristics curves as in silicon devices.
2.1. BO-DD 1D drift-diffusion (DD) solver for SOI-MOSFETs combined with ¨ the solution of the coupled Schrodinger-Poisson equations on the device cross-section normal to the transport direction [15]. The mobility model [16] is also used in the DD solver.
2.2. UD Multi-subband ensemble Monte Carlo (MSMC) simulator as described in [17,18]. A first order approach to include quantum effects in the transport direction has been implemented. Scattering mechanisms such as SR and phonons are also included [19].
2.3. SNPS Self-consistent semiclassical full-band Monte Carlo device simulator as described in [20]. Self-consistency is obtained by iterating single-particle simulations with solutions of the nonlinear Poisson equation until convergence. The scattering mechanisms comprise phonon, impurity and SR scattering.
Fig. 1. Structure of the 22 nm template DG MOSFET considered in the work. One half of the symmetric structure is shown. All dimensions are in nm.
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2.4. TUBS Self-consistent solution of 6 6 k.p SE, PE and multi-subband BTE as described in [21,22]. Scattering due to phonons and surface roughness are also included [23,24].
3. DG MOSFET model Our model presented in [11] for n-channel devices has been shown to reproduce 2D advanced transport simulations of nanoscale n-channel devices by means of the hydrodynamic transport formulation explained in [12]. Here, we extend it to p-channel devices. The potentials at the surface js and in the center jo of the silicon layer can be calculated analytically as shown in [2]. The surface potentials in the subthreshold jsBT and in the above threshold jsAT regimes are calculated analytically using the Lambert function. Finally, the overall surface potential in all regions can be calculated as [11]: 1 1tanh 710 V gs V T V ch 2 1 1þ tanh 7 10 V gs V T V ch þ jsAT 2
js ¼ jsBT
ð1Þ
where ‘ þ’ for n-channel, ‘ ’ for p-channel, Vgs is the applied gate voltage, VT is the threshold voltage and Vch is the channel voltage. The Lambert function is represented in Verilog-A language as a built-in function conserving the requirements of a compact model. This analytical surface potential calculation gives the possibility of writing charge carrier calculation at source, qs, and at the drain qd as explicit functions of the applied voltages. The drain current in a p-channel DG MOSFET is calculated as a function of the mobile charge densities at the source qs and at the drain qd as (qs and qd are in absolute value) [11], assuming a driftdiffusion transport: " " ## 2 q2s q2d qd þ qdep WC ox ft ms 2 qs qd þ þ qdep ln IDS ¼ 7 2 ð2Þ L 2 qs þqdep where W and L are width and length of the device respectively. Cox is the gate capacitance; ft is the thermal voltage, qdep ¼qNatsi/ Coxft is the normalized fixed charge concentration in the silicon layer of thickness tsi, q the electron charge, Na is the doping concentration; ms is the surface mobility. The expression for the drain current in Eq. (2) is used as the core model for DG MOSFET. In the complete model, the effects of velocity saturation, channel length modulation, threshold voltage roll-off, DIBL and subthreshold swing degradation are all included. In extremely short channel devices, the transport regime is quasi-ballistic; thus, an important overshoot velocity is expected. The velocity overshoot is included in the model using a one dimensional energy-balance model [12]. The velocity overshoot is modeled assuming a hydrodynamic transport model which is included in the core drain current model. The final drain current expression accounting for the hydrodynamic transport model is given as: " " ## 2 q2s q2d qd þ qdep WC ox ft ms 2 qs qd þ IDS ¼ 7 2 þqdep ln ð3Þ 2 qs þ qdep L 1þ gn V dss m where, gn ¼ vsatef fL 1 þ 21lw =L takes into account both the velocity saturation effect and the hydrodynamic transport [12], through which the velocity overshoot is also modeled, lw ¼ 2vsat tw being the energy relaxation length, tw the energy relaxation time constant, vsat the saturation velocity and Vdss is the effective drainsource voltage. The charge and capacitances expression are developed following the procedure presented in [6] for undoped devices, but considering the doping in the charge control model.
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4. CMOS circuits
0.4
BO-DD TUBS UD SNPS Model
0.3 IDS (mA/µm)
We have studied the behavior of a CMOS inverter based on DG MOSFETs with the technological features given in Fig. 2. The supply voltage is set to 1 V. The load capacitance used for this inverter is 3.0fF. The aspect ratios are (W/L)p ¼(100 nm/22 nm)p and (W/L)n ¼ (50 nm/22 nm)n. A five stage CMOS ring oscillator based on DG MOSFETs is shown in Fig. 3. The load capacitance used for this ring oscillator is 7.5fF.
0.2
VDS = 100 mV
0.1
5. Results and discussions
0.0 0.5
0.6
0.7
0.8
0.9
1.0
0.8
0.9
1.0
VGS (V) BO-DD TUBS UD SNPS Model
0.8
0.6 IDS(mA/µm)
We have used SMASH circuit simulator [25] to carry out the circuit simulations presented in this work. The model has been implemented in Verilog-A code for both n-channel and p-channel DG MOSFETs and compiled to include the DG devices as new active components of the circuit simulator. We consider DG MOSFET devices with parameters as shown in Fig. 1. In [12] it was shown that our hydrodynamic compact model agreed very well with Monte Carlo (MC) simulations of these 22 nm n-channel devices, including the same template device we are considering in this paper. The results of the compact model for p-channel have been validated in this work. Here we show the comparisons between the numerical simulation data obtained by several research groups using advanced transport models [15–24]. Fig. 4 shows the transfer characteristics of the 22 nm DG p-channel MOSFETs at low and high VDS. A good agreement between the compact model and the numerical simulations [15–24] is obtained by
VDS = 1 V 0.4
0.2
0.0 0.5
0.6
0.7 VGS (V)
Fig. 4. Transfer characteristics of 22 nm DG p-channel MOSFETs for low (top) and high (bottom) VDS. 2D numerical simulation data by Univ. of Bologna (BO-DD) [15,16], Tech. Univ. Braunschweig (TUBS) [21–24], Univ. of Udine (UD) [17–19], Synopsys (SNPS) [20]. Table 1 Parameters used in the proposed analytical model in order to fit the pMOS simulations obtained using different transport models. Models
22 nm DG p-channel MOSFET Tsi ¼10 nm EOT ¼1.1 nm
Fig. 2. Simulated CMOS inverter.
VDD=1.0V
BO-DD TUBS UD SNPS
VIN VOUT 7.0 fF
7.0 fF
7.0 fF
7.0 fF
Fig. 3. Five stage CMOS ring oscillator.
7.0 fF
vsat ( 107 cm s 1)
tw
m0
y1
y2
(ps)
(cm2 V 1 sec 1)
(V 1)
(V 2)
1.01 0.95 0.90 1.05
– 0.5 0.3 0.3
95 76 75 75
0.4 0.9 0.7 0.5
3.9 1.15 1.15 0.15
considering the low field mobility and for a fitted saturation velocity. Table 1 indicates the velocity saturation, energy relaxation time constant, low field mobility and mobility degradation parameters considered in the model. From the table parameters it can be seen that strong mobility degradation is observed with the drift-diffusion model. It can be seen that low mobility degradation is observed with the SNPS simulations. Table 2 indicates the velocity saturation, energy relaxation time constant, low field mobility and mobility degradation parameters considered in the model for nMOS [12]. We have used the extracted parameters of n-channel and p-channel 22 nm DG MOSFETs to simulate the transfer and output
M. Cheralathan et al. / Microelectronics Journal 44 (2013) 80–85
Table 2 Parameters used in the proposed analytical model in order to fit the nMOS simulations obtained using different transport models. Models
DG n-channel MOSFET 22 nm Tsi¼ 10 nm EOT¼ 1.1 nm device parameters
BO-DD UD UPS SNPS BO-MC MSB-EMC (UGR)
vsat ( 107 cm s 1)
tw
m0
y1
y2
(ps)
(cm2 V 1 sec 1)
(V 1)
(V 2)
1.1 1.02 0.9 0.9 1.01 0.8
– 0.12 0.12 0.12 0.15 0.3
150 150 150 150 220 220
0.8 0.1 0.14 0.14 0.1 0.01
1.93 0.58 0.039 0.039 0.039 0.05
2.5x10-3
Drift diffusion model(BO-DD) Hydrodynamic model(UD)
IDS (A)
2.0x10-3 VDS =1.0V
1.5x10-3 1.0x10-3
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Fig. 6 shows the output characteristics of drift-diffusion and hydrodynamic transport model at high VGS. As expected, (because of the velocity overshoot effect) it can be seen from the curves that the hydrodynamic transport model has higher drain current than the DD model in the saturation region. Fig. 7 shows the voltage transfer of a CMOS inverter obtained using our DG MOSFET model in SMASH by Verilog-A. The channel width of the p-channel device is twice the one of the n-channel device. The curves show the DD and hydrodynamic model. It can be seen that the switching voltage is higher using the hydrodynamic model than the DD model. Fig. 8 shows the transient response of a CMOS inverter with DD and hydrodynamic model. It can be seen that the rise time is much shorter in the hydrodynamic model than in the DD model. The hydrodynamic model gives a therefore a smaller delay than the DD model. Fig. 9 shows the transient response of a five stage CMOS ring oscillator with DD and hydrodynamic model. It can be seen that the oscillation starts with much smaller delay in the hydrodynamic model than in the DD model. Fig. 10 shows capacitance characteristics for the DG MOSFET as a function of gate voltage. We show that the approximation considered in the calculation of capacitances in the Verilog-A code using SMASH gives practically the same result as the values directly obtained from the capacitance model (Fig. 10).
VDS =0.1V 5.0x10-4 0.0
2.0x10-3
0.0
0.2
0.4
0.6
0.8
8.0x10-4
IDS (A)
IDS (A)
Drift diffusion model(BO-DD) Hydrodynamic model(UD)
VGS =1.5V
1.5x10-3
1.0
VGS (V) 1.0x10-3
Drift Diffusion model Hydrodynamic model
1.0x10-3
VGS =1.0V
5.0x10-4 VDS =1.0V 0.0
6.0x10-4
0.0
0.4
0.8
1.2
1.6
2.0
VDS (V)
4.0x10-4
Fig. 6. Output characteristics obtained for an n-channel DG MOSFET Lg ¼22 nm Ts¼ 10 nm EOT¼ 1.1 nm.
VDS =0.1V 2.0x10-4
Drift-Diffusion model Hydrodynamic model
1.0
0.0 0.0
0.2
0.4
0.6
0.8
1.0
0.8
Fig. 5. Transfer characteristics obtained for an n-channel (top) and p-channel (bottom) DG MOSFET Lg ¼22 nm Ts ¼10 nm and EOT ¼ 1.1 nm.
characteristics using SMASH simulator. For the DD model, extracted parameters from BO-DD simulations were used. For the hydrodynamic transport model, extracted parameters from UD simulations were used. For this specific case, the quantum mechanical effects are not considered for thicknesses greater than 10 nm in the Verilog-A code. Fig. 5 shows the transfer characteristics of drift-diffusion and hydrodynamic transport model at low and high VDS. From the curves it can seen that the hydrodynamic transport model included in the core model gives higher drain current than the DD model, due to the velocity overshoot. This can be clearly seen at higher drain bias.
VOUT (V)
VGS (V)
0.6 0.4 0.2 0.0 0.0
0.2
0.4
0.6
0.8
1.0
VIN (V) Fig. 7. Voltage transfer characteristics of a 22 nm CMOS inverter using the DG MOSFET model in Verilog-A with SMASH.
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M. Cheralathan et al. / Microelectronics Journal 44 (2013) 80–85
-15
1.2
x 10
Drift-Diffusion model Hydrodynamic model
7
0.8
CGD
6
0.6
Capacitances
VOUT (V)
CGS
8
1.0
0.4 0.2
5 4 3
0.0 0.00
150.00n
300.00n
450.00n
Time (ns)
2 1
Fig. 8. Transient response of a 22 nm CMOS inverter using our DG MOSFET model in SMASH by means of Verilog-A.
0
0 0.1
0.3
0.5
0.7
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 VGS (V)
Drift-diffusion model Fig. 10. Gate-to-source capacitance (Cgs) and gate-to-drain capacitance (Cgd), for VDS ¼0.5 V, obtained using the method implemented in Verilog-A with SMASH (Symbols) and the entire capacitance model developed (lines).
Hydrodynamic model
1.0
The simulator then obtains the charging/discharging currents by differentiating of charges with respect to the time. This modeling is used to obtain the capacitances Cgs and Cgd in Verilog-A with SMASH, shown in Fig. 10.
VOUT (V)
0.8
0.6
6. Conclusions
0.4
0.2
0.0 0.0
20.0n
40.0n 60.0n Time (ns)
80.0n
100.0n
Fig. 9. Transient response of a 22 nm five stage CMOS ring oscillator using our DG MOSFET model in SMASH by means of Verilog-A.
To use the capacitance model in Verilog-A with SMASH, we have to calculate the charges called Qgs and Qgd from the numerical integration of the device capacitances Cgs and Cgd, obtained from the model, from Vgs ¼0 to VGS, and from Vgd ¼0 to VGD, respectively, where VGS and VGD are the applied gate-source and gate-drain voltages: 9 8 n X > > > > > > C ðiÞ n V ði V ð i1 ÞÞ > > gs gs gs > > > > > > = > > > > > V gs ði ¼ 0Þ ¼ 0 > > > > > > > > ; : V gs ði ¼ nÞ ¼ V gs 9 8 n X > > > > > > ð ÞÞ C ðiÞ n V ði V i1 > > gd gd gd > > > > > > = > > > > > V gd ði ¼ 0Þ ¼ 0 > > > > > > > > ; : V gd ði ¼ nÞ ¼ V gd
In this paper, we present the implementation of compact nanoscale n-channel and p-channel DG MOSFET models accounting for hydrodynamic transport model, in Verilog-A for circuit simulation. We have carried out a comparison of the simulated performance of a 22 nm CMOS inverter and a ring oscillator using both the hydrodynamic transport model and the drift diffusion model for nanoscale DG MOSFETs with model parameters extracted from 2D advanced transport simulations of n-channel and p-channel devices. As expected, smaller delays are obtained with the hydrodynamic model.
Acknowledgment This work was supported by the Ministerio de Ciencia e Innovacion under project TEC2011-28357-C02-01, by the European Commission under contract FP7-PEOPLE-2007-3-1-IAPP No. 218255 ‘‘Compact Modelling Network (COMON)’’, by the ICREA Academia Award and by the PGIR Grant from URV, the project Contract no. 5646 and by the project 2010 CONE2 00061 from Catalan Government. J. Alvarado thanks to CONACYT for its support by the program ‘‘Programa de Apoyo Complementario para la Consolidacio´n Institucional (Fondo Institucional) Repatriacio´n y Retencio´n’’. Authors would like to thank, Dr. Gilles Depeyrot, Fre´de´ric Poullet and Ce´dric Valla of Dolphin Integration for their advice. References [1] International Technology Roadmap for Semiconductor 2009 and the 2010 update, /http://public.itrs.netS. ˜ iguez, M. Estrada, Modeling of potentials and [2] A. Cerdeira, O. Moldovan, B. In threshold voltage for symmetric doped double-gate MOSFETs, Solid State Electron. 52 (2008) 830–837.
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Implementation of nanoscale double-gate CMOS circuits using compact advanced transport models Muthupandian Cheralathan a,n, Esteban Contreras b, Joaquı´n Alvarado c, Antonio Cerdeira b, ˜ iguez a Giuseppe Iannaccone d, Enrico Sangiorgi e, Benjamin In a
DEEEA, Universitat Rovira i Virgili, 26 Av. Paisos Catalans, Tarragona 43007, Spain SEES, CINVESTAV, Av. IPN No.2508, Apto. Postal 14-740, 07360 DF, Mexico c ´noma de Puebla, 72570 Puebla, Me´xico CIDS, Beneme´rita Universidad Auto d Department of Information Engineering, University of Pisa-IU.NET, Pisa, Italy e ARCES, University of Bologna-IU.NET, Cesena, Italy b
a r t i c l e i n f o
a b s t r a c t
Article history: Received 6 July 2012 Received in revised form 2 November 2012 Accepted 14 November 2012 Available online 31 December 2012
In this paper we present the results of the implementation of a nanoscale double-gate (DG) MOSFET compact model, which includes hydrodynamic transport model, in Verilog-A in order to carry out circuit simulation. The model in Verilog-A is used with the SMASH circuit simulator for the analysis of the DC and transient behavior electrical CMOS circuits. Template devices representative for a downscaled symmetric double-gate MOSFET was used to validate the models for n-channel and p-channel. A CMOS inverter and a ring oscillator have been analyzed. Comparison of its performance between the drift-diffusion (DD) and hydrodynamic transport model within the practical range of bias voltages has been highlighted. & 2012 Elsevier Ltd. All rights reserved.
Keywords: Double-gate MOSFET Hydrodynamic Verilog-A SMASH
1. Introduction The device-scaling concept has been the main guiding principle of the MOS-device engineering over the past few decades [1]. As the conventional bulk MOSFET technology is scaling down towards the practical limit, DG MOSFETs appeared as a promising technological alternative that has attracted substantial research interests due to superior short channel control, volume inversion, etc. There has been work dedicated to modeling and simulation of DG MOSFETs. Compact core models for undoped and doped symmetric DG MOSFETs have been presented, even using new artificial intelligence based approaches [2–7]. The development of models to simulate circuits containing new devices is an important task to allow the introduction of these devices in practical applications. Accurate and time computationally efficient compact models of DG MOSFETs are required to predict or simulate circuit performance. For a circuit simulation the main task is to have a precise transistor model to reproduce the transistor behavior, which is either already introduced or can be implemented in the commercial circuit simulators to be used. In
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Corresponding author. E-mail addresses: [email protected], [email protected] (M. Cheralathan). 0026-2692/$ - see front matter & 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2012.11.006
recent years, some work has been done on the implementation of DG MOSFET compact models in circuit simulators [8–11]. In this work, we present the implementation of a DG MOSFET compact model including hydrodynamic transport model in Verilog-A for circuit simulators. The model is based on an analytical expression that models the variation of surface potential as well as the difference of potential at the surface and at the middle of the silicon layer [2]. This model for the potentials is used in an analytical compact model for the drain current of a double-gate MOSFETs derived from a core charge control model which results from the solution of the 1D Poisson’s Eq. (3). Electrostatic short-channel effects (threshold voltage roll-off, DIBL, subthreshold swing degradation) were introduced in the core model using scalable and geometry dependent equations. This model is valid from lightly doped to highly doped devices [3]. We extended this model to include hydrodynamic transport model [12]. The extended model includes a gate dielectric thickness correction [13] and also a threshold voltage correction [14] through which the quantum effects are taken into account. Besides, charge and capacitance models consistent with the DC model were developed. In [12] we validated this model for n-channel DG MOSFETs by comparison with numerical simulations obtained using advanced transport models. In this paper, first of all, we extend this model to p-channel devices and we validate it by comparison with numerical simulations based on
M. Cheralathan et al. / Microelectronics Journal 44 (2013) 80–85
advanced transport models. The entire models for n-channel and p-channel devices is implemented in Verilog-A, which allows the use of the model in commercial circuit simulators for circuit design of both digital and analog applications. We have shown examples of DG MOSFET based CMOS circuits namely, an inverter and a ring oscillator. Finally, we compare results between driftdiffusion and hydrodynamic transport models within the practical range of voltages.
2. Device and approaches The 22 nm template transistor we considered is shown in Fig. 1. The 22 nm DG MOSFET with a gate length of 22 nm, a gate stack consisting of 2.4 nm of HfO2 on top of 0.7 nm of SiO2 (EOT¼1.1 nm). The silicon film thickness is 10 nm. The channel is undoped (1015 cm 3). We have considered both n-channel and p-channel DG MOSFETs with these dimensions. The main features of each transport models (represented with the acronym of the main developer) are presented. The modeling approaches can range from modifications of the conventional drift-diffusion (DD) model used in commercial TCAD tools to advanced Monte Carlo (MC) models. The numerical models used by the different groups [13–22] differ in terms of scattering models, simulation approaches, etc. For comparison, all simulators have been first calibrated to reproduce the characteristics curves as in silicon devices.
2.1. BO-DD 1D drift-diffusion (DD) solver for SOI-MOSFETs combined with ¨ the solution of the coupled Schrodinger-Poisson equations on the device cross-section normal to the transport direction [15]. The mobility model [16] is also used in the DD solver.
2.2. UD Multi-subband ensemble Monte Carlo (MSMC) simulator as described in [17,18]. A first order approach to include quantum effects in the transport direction has been implemented. Scattering mechanisms such as SR and phonons are also included [19].
2.3. SNPS Self-consistent semiclassical full-band Monte Carlo device simulator as described in [20]. Self-consistency is obtained by iterating single-particle simulations with solutions of the nonlinear Poisson equation until convergence. The scattering mechanisms comprise phonon, impurity and SR scattering.
Fig. 1. Structure of the 22 nm template DG MOSFET considered in the work. One half of the symmetric structure is shown. All dimensions are in nm.
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2.4. TUBS Self-consistent solution of 6 6 k.p SE, PE and multi-subband BTE as described in [21,22]. Scattering due to phonons and surface roughness are also included [23,24].
3. DG MOSFET model Our model presented in [11] for n-channel devices has been shown to reproduce 2D advanced transport simulations of nanoscale n-channel devices by means of the hydrodynamic transport formulation explained in [12]. Here, we extend it to p-channel devices. The potentials at the surface js and in the center jo of the silicon layer can be calculated analytically as shown in [2]. The surface potentials in the subthreshold jsBT and in the above threshold jsAT regimes are calculated analytically using the Lambert function. Finally, the overall surface potential in all regions can be calculated as [11]: 1 1tanh 710 V gs V T V ch 2 1 1þ tanh 7 10 V gs V T V ch þ jsAT 2
js ¼ jsBT
ð1Þ
where ‘ þ’ for n-channel, ‘ ’ for p-channel, Vgs is the applied gate voltage, VT is the threshold voltage and Vch is the channel voltage. The Lambert function is represented in Verilog-A language as a built-in function conserving the requirements of a compact model. This analytical surface potential calculation gives the possibility of writing charge carrier calculation at source, qs, and at the drain qd as explicit functions of the applied voltages. The drain current in a p-channel DG MOSFET is calculated as a function of the mobile charge densities at the source qs and at the drain qd as (qs and qd are in absolute value) [11], assuming a driftdiffusion transport: " " ## 2 q2s q2d qd þ qdep WC ox ft ms 2 qs qd þ þ qdep ln IDS ¼ 7 2 ð2Þ L 2 qs þqdep where W and L are width and length of the device respectively. Cox is the gate capacitance; ft is the thermal voltage, qdep ¼qNatsi/ Coxft is the normalized fixed charge concentration in the silicon layer of thickness tsi, q the electron charge, Na is the doping concentration; ms is the surface mobility. The expression for the drain current in Eq. (2) is used as the core model for DG MOSFET. In the complete model, the effects of velocity saturation, channel length modulation, threshold voltage roll-off, DIBL and subthreshold swing degradation are all included. In extremely short channel devices, the transport regime is quasi-ballistic; thus, an important overshoot velocity is expected. The velocity overshoot is included in the model using a one dimensional energy-balance model [12]. The velocity overshoot is modeled assuming a hydrodynamic transport model which is included in the core drain current model. The final drain current expression accounting for the hydrodynamic transport model is given as: " " ## 2 q2s q2d qd þ qdep WC ox ft ms 2 qs qd þ IDS ¼ 7 2 þqdep ln ð3Þ 2 qs þ qdep L 1þ gn V dss m where, gn ¼ vsatef fL 1 þ 21lw =L takes into account both the velocity saturation effect and the hydrodynamic transport [12], through which the velocity overshoot is also modeled, lw ¼ 2vsat tw being the energy relaxation length, tw the energy relaxation time constant, vsat the saturation velocity and Vdss is the effective drainsource voltage. The charge and capacitances expression are developed following the procedure presented in [6] for undoped devices, but considering the doping in the charge control model.
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4. CMOS circuits
0.4
BO-DD TUBS UD SNPS Model
0.3 IDS (mA/µm)
We have studied the behavior of a CMOS inverter based on DG MOSFETs with the technological features given in Fig. 2. The supply voltage is set to 1 V. The load capacitance used for this inverter is 3.0fF. The aspect ratios are (W/L)p ¼(100 nm/22 nm)p and (W/L)n ¼ (50 nm/22 nm)n. A five stage CMOS ring oscillator based on DG MOSFETs is shown in Fig. 3. The load capacitance used for this ring oscillator is 7.5fF.
0.2
VDS = 100 mV
0.1
5. Results and discussions
0.0 0.5
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1.0
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1.0
VGS (V) BO-DD TUBS UD SNPS Model
0.8
0.6 IDS(mA/µm)
We have used SMASH circuit simulator [25] to carry out the circuit simulations presented in this work. The model has been implemented in Verilog-A code for both n-channel and p-channel DG MOSFETs and compiled to include the DG devices as new active components of the circuit simulator. We consider DG MOSFET devices with parameters as shown in Fig. 1. In [12] it was shown that our hydrodynamic compact model agreed very well with Monte Carlo (MC) simulations of these 22 nm n-channel devices, including the same template device we are considering in this paper. The results of the compact model for p-channel have been validated in this work. Here we show the comparisons between the numerical simulation data obtained by several research groups using advanced transport models [15–24]. Fig. 4 shows the transfer characteristics of the 22 nm DG p-channel MOSFETs at low and high VDS. A good agreement between the compact model and the numerical simulations [15–24] is obtained by
VDS = 1 V 0.4
0.2
0.0 0.5
0.6
0.7 VGS (V)
Fig. 4. Transfer characteristics of 22 nm DG p-channel MOSFETs for low (top) and high (bottom) VDS. 2D numerical simulation data by Univ. of Bologna (BO-DD) [15,16], Tech. Univ. Braunschweig (TUBS) [21–24], Univ. of Udine (UD) [17–19], Synopsys (SNPS) [20]. Table 1 Parameters used in the proposed analytical model in order to fit the pMOS simulations obtained using different transport models. Models
22 nm DG p-channel MOSFET Tsi ¼10 nm EOT ¼1.1 nm
Fig. 2. Simulated CMOS inverter.
VDD=1.0V
BO-DD TUBS UD SNPS
VIN VOUT 7.0 fF
7.0 fF
7.0 fF
7.0 fF
Fig. 3. Five stage CMOS ring oscillator.
7.0 fF
vsat ( 107 cm s 1)
tw
m0
y1
y2
(ps)
(cm2 V 1 sec 1)
(V 1)
(V 2)
1.01 0.95 0.90 1.05
– 0.5 0.3 0.3
95 76 75 75
0.4 0.9 0.7 0.5
3.9 1.15 1.15 0.15
considering the low field mobility and for a fitted saturation velocity. Table 1 indicates the velocity saturation, energy relaxation time constant, low field mobility and mobility degradation parameters considered in the model. From the table parameters it can be seen that strong mobility degradation is observed with the drift-diffusion model. It can be seen that low mobility degradation is observed with the SNPS simulations. Table 2 indicates the velocity saturation, energy relaxation time constant, low field mobility and mobility degradation parameters considered in the model for nMOS [12]. We have used the extracted parameters of n-channel and p-channel 22 nm DG MOSFETs to simulate the transfer and output
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Table 2 Parameters used in the proposed analytical model in order to fit the nMOS simulations obtained using different transport models. Models
DG n-channel MOSFET 22 nm Tsi¼ 10 nm EOT¼ 1.1 nm device parameters
BO-DD UD UPS SNPS BO-MC MSB-EMC (UGR)
vsat ( 107 cm s 1)
tw
m0
y1
y2
(ps)
(cm2 V 1 sec 1)
(V 1)
(V 2)
1.1 1.02 0.9 0.9 1.01 0.8
– 0.12 0.12 0.12 0.15 0.3
150 150 150 150 220 220
0.8 0.1 0.14 0.14 0.1 0.01
1.93 0.58 0.039 0.039 0.039 0.05
2.5x10-3
Drift diffusion model(BO-DD) Hydrodynamic model(UD)
IDS (A)
2.0x10-3 VDS =1.0V
1.5x10-3 1.0x10-3
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Fig. 6 shows the output characteristics of drift-diffusion and hydrodynamic transport model at high VGS. As expected, (because of the velocity overshoot effect) it can be seen from the curves that the hydrodynamic transport model has higher drain current than the DD model in the saturation region. Fig. 7 shows the voltage transfer of a CMOS inverter obtained using our DG MOSFET model in SMASH by Verilog-A. The channel width of the p-channel device is twice the one of the n-channel device. The curves show the DD and hydrodynamic model. It can be seen that the switching voltage is higher using the hydrodynamic model than the DD model. Fig. 8 shows the transient response of a CMOS inverter with DD and hydrodynamic model. It can be seen that the rise time is much shorter in the hydrodynamic model than in the DD model. The hydrodynamic model gives a therefore a smaller delay than the DD model. Fig. 9 shows the transient response of a five stage CMOS ring oscillator with DD and hydrodynamic model. It can be seen that the oscillation starts with much smaller delay in the hydrodynamic model than in the DD model. Fig. 10 shows capacitance characteristics for the DG MOSFET as a function of gate voltage. We show that the approximation considered in the calculation of capacitances in the Verilog-A code using SMASH gives practically the same result as the values directly obtained from the capacitance model (Fig. 10).
VDS =0.1V 5.0x10-4 0.0
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IDS (A)
IDS (A)
Drift diffusion model(BO-DD) Hydrodynamic model(UD)
VGS =1.5V
1.5x10-3
1.0
VGS (V) 1.0x10-3
Drift Diffusion model Hydrodynamic model
1.0x10-3
VGS =1.0V
5.0x10-4 VDS =1.0V 0.0
6.0x10-4
0.0
0.4
0.8
1.2
1.6
2.0
VDS (V)
4.0x10-4
Fig. 6. Output characteristics obtained for an n-channel DG MOSFET Lg ¼22 nm Ts¼ 10 nm EOT¼ 1.1 nm.
VDS =0.1V 2.0x10-4
Drift-Diffusion model Hydrodynamic model
1.0
0.0 0.0
0.2
0.4
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0.8
1.0
0.8
Fig. 5. Transfer characteristics obtained for an n-channel (top) and p-channel (bottom) DG MOSFET Lg ¼22 nm Ts ¼10 nm and EOT ¼ 1.1 nm.
characteristics using SMASH simulator. For the DD model, extracted parameters from BO-DD simulations were used. For the hydrodynamic transport model, extracted parameters from UD simulations were used. For this specific case, the quantum mechanical effects are not considered for thicknesses greater than 10 nm in the Verilog-A code. Fig. 5 shows the transfer characteristics of drift-diffusion and hydrodynamic transport model at low and high VDS. From the curves it can seen that the hydrodynamic transport model included in the core model gives higher drain current than the DD model, due to the velocity overshoot. This can be clearly seen at higher drain bias.
VOUT (V)
VGS (V)
0.6 0.4 0.2 0.0 0.0
0.2
0.4
0.6
0.8
1.0
VIN (V) Fig. 7. Voltage transfer characteristics of a 22 nm CMOS inverter using the DG MOSFET model in Verilog-A with SMASH.
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-15
1.2
x 10
Drift-Diffusion model Hydrodynamic model
7
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CGD
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Capacitances
VOUT (V)
CGS
8
1.0
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5 4 3
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150.00n
300.00n
450.00n
Time (ns)
2 1
Fig. 8. Transient response of a 22 nm CMOS inverter using our DG MOSFET model in SMASH by means of Verilog-A.
0
0 0.1
0.3
0.5
0.7
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 VGS (V)
Drift-diffusion model Fig. 10. Gate-to-source capacitance (Cgs) and gate-to-drain capacitance (Cgd), for VDS ¼0.5 V, obtained using the method implemented in Verilog-A with SMASH (Symbols) and the entire capacitance model developed (lines).
Hydrodynamic model
1.0
The simulator then obtains the charging/discharging currents by differentiating of charges with respect to the time. This modeling is used to obtain the capacitances Cgs and Cgd in Verilog-A with SMASH, shown in Fig. 10.
VOUT (V)
0.8
0.6
6. Conclusions
0.4
0.2
0.0 0.0
20.0n
40.0n 60.0n Time (ns)
80.0n
100.0n
Fig. 9. Transient response of a 22 nm five stage CMOS ring oscillator using our DG MOSFET model in SMASH by means of Verilog-A.
To use the capacitance model in Verilog-A with SMASH, we have to calculate the charges called Qgs and Qgd from the numerical integration of the device capacitances Cgs and Cgd, obtained from the model, from Vgs ¼0 to VGS, and from Vgd ¼0 to VGD, respectively, where VGS and VGD are the applied gate-source and gate-drain voltages: 9 8 n X > > > > > > C ðiÞ n V ði V ð i1 ÞÞ > > gs gs gs > > > > > > = > > > > > V gs ði ¼ 0Þ ¼ 0 > > > > > > > > ; : V gs ði ¼ nÞ ¼ V gs 9 8 n X > > > > > > ð ÞÞ C ðiÞ n V ði V i1 > > gd gd gd > > > > > > = > > > > > V gd ði ¼ 0Þ ¼ 0 > > > > > > > > ; : V gd ði ¼ nÞ ¼ V gd
In this paper, we present the implementation of compact nanoscale n-channel and p-channel DG MOSFET models accounting for hydrodynamic transport model, in Verilog-A for circuit simulation. We have carried out a comparison of the simulated performance of a 22 nm CMOS inverter and a ring oscillator using both the hydrodynamic transport model and the drift diffusion model for nanoscale DG MOSFETs with model parameters extracted from 2D advanced transport simulations of n-channel and p-channel devices. As expected, smaller delays are obtained with the hydrodynamic model.
Acknowledgment This work was supported by the Ministerio de Ciencia e Innovacion under project TEC2011-28357-C02-01, by the European Commission under contract FP7-PEOPLE-2007-3-1-IAPP No. 218255 ‘‘Compact Modelling Network (COMON)’’, by the ICREA Academia Award and by the PGIR Grant from URV, the project Contract no. 5646 and by the project 2010 CONE2 00061 from Catalan Government. J. Alvarado thanks to CONACYT for its support by the program ‘‘Programa de Apoyo Complementario para la Consolidacio´n Institucional (Fondo Institucional) Repatriacio´n y Retencio´n’’. Authors would like to thank, Dr. Gilles Depeyrot, Fre´de´ric Poullet and Ce´dric Valla of Dolphin Integration for their advice. References [1] International Technology Roadmap for Semiconductor 2009 and the 2010 update, /http://public.itrs.netS. ˜ iguez, M. Estrada, Modeling of potentials and [2] A. Cerdeira, O. Moldovan, B. In threshold voltage for symmetric doped double-gate MOSFETs, Solid State Electron. 52 (2008) 830–837.
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