Increasing Encoding Efficiency of LFSR Reseeding ... - IEEE Xplore
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 5, MAY 2006
of the metal path P1 -to-P2 (black) and P3 -to-P4 (gray) are 0.5 and 0.3 nH, respectively, and the coupling coefficient between these two inductances is 0.8. The transformer is unbalanced by the asymmetrical coupling coefficient of a nearby inductance of 0.2 nH (white), where the coupling coefficients to the upper spiral structure (k) is five times larger than that of the lower spiral structure (k ). The resistances associated with the inductance account for the finite Q of 10 at 5 GHz, and the parasitic capacitances are omitted for simplicity. The extracted response [∆s], as shown in Figs. 7 and 8, has an identical response, proving that the proposed method is accurate and free from any approximation or assumption. The elements of [∆s]4 that are not shown in Fig. 7 are the ones with magnitudes below −120 dB, where the simulation’s numerical errors became predominant. V. C ONCLUSION A new method for extracting mixed-mode s-parameters is presented based on attaching additional circuits to the four-port or three-port circuit. The results are calculated using SPICE. Verification shows that this method is accurate and free from any restrictions or approximations. Furthermore, this new method can provide intuitive information on the relations between the extracted [∆s] and the circuit’s operation. The proposed SPICE-based extraction method will be of practical value for IC and circuit designers who are tied to the SPICE programs by reason of IC CAD tool flow or prior simulation expertise. R EFERENCES [1] K. Kurokawa, “Power waves and the scattering matrix,” IEEE Trans. Microw. Theory Tech., vol. MTT-13, no. 2, pp. 194–202, Mar. 1965. [2] G. Gonzalez, Microwave Transistor Amplifiers; Analysis and Design, Sec. 1.6, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 1997. [3] D. E. Bockelman and W. R. Eisenstadt, “Combined differential-and common mode scattering parameters: Theory and simulation,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 7, pp. 1530–1539, Jul. 1995. [4] K. Jung and W. R. Eisenstadt, “SPICE-based mixed-mode S-parameter calculations for four port circuits,” in Proc. 62nd ARFTG Microwave Measurements Conf.—Differential Measurements, Boulder, CO, Dec. 2003, pp. 181–186. [5] R. Goyal, “S-parameter output from the SPICE program,” IEEE Circuit and Device Magazine—Section: Circuit Simulation and Modeling, vol. 4, no. 2, pp. 28–29, Mar. 1988. [6] S. Kodali and D. J. Allstot, “A symmetric miniature 3D inductor,” in Proc. Int. Symp. Circuits Systems, Bangkok, Thailand, May 2003, vol. 1, pp. 89–92.
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Increasing Encoding Efficiency of LFSR Reseeding-Based Test Compression Hong-Sik Kim and Sungho Kang
Abstract—A new methodology to increase the encoding efficiency of test compression based on linear feedback shift registers (LFSRs) is proposed. The proposed method combines LFSR reseeding and bit fixing. Deterministic test patterns tend to have a biased probability of the logic value 1 or 0 at each primary input. If such biased inputs are fixed to the logic value 1 or 0 with some combinational logic, then the amount of data to be encoded by the LFSR will be considerably reduced. Additionally, in order to reduce the encoded data volume much further, a variable degree of the LFSR polynomial is employed. In the variable-degree LFSR scheme, a test cube with less specified bits is encoded with an LFSR polynomial of lower degree, while a test cube with more specified bits is encoded with an LFSR polynomial of higher degree. Experimental results for the larger ISCAS 89 benchmark circuits show that the proposed scheme can increase the encoding efficiency with little hardware overhead compared to previous schemes. Index Terms—Built-in self-test, linear feedback shift register (LFSR) reseeding, scan testing, test compression.
I. I NTRODUCTION Highly developed deep submicron technology has enabled the implementation of large very large scale integrated (VLSI) systems like systems on a chip (SOCs). In those large SOC designs, intellectual property (IP) cores such as processor cores, a large size embedded memories, and mixed signal, analog, as well as radio frequency (RF) cores are integrated into a single chip. The more IP cores are used, the larger test data volumes are required. Therefore, in order to apply the large volume of test patterns to a chip under test, the automatic test equipment (ATE) requires large memory storage, and this increases the cost of the tester. In addition, since the number of external input–output (IO) ports of a chip and the number of ATE channel are limited, test is a very time-consuming task. Built-in self-test (BIST) is widely known as a good solution for testing the individual IP cores [1]–[3]. As a BIST pattern generator, a pseudorandom test pattern generator like a linear feedback shift register (LFSR) is widely adopted due to its low hardware overhead. However, in case that there are many random-pattern-resistive faults in the circuit under test (CUT), it is difficult to achieve a high fault coverage with an adequate number of test patterns. To overcome this problem, several solutions have been proposed [4]–[11]. Test point insertion can reduce the test set or the test time while providing high fault coverage [4], [5]. This design for testability (DFT) technique is used to modify the CUT to be more random pattern testable, but this kind of DFT application can exert timing impact on the designed circuit by inserting redundant logic on the critical path. Weighted random test is also a good solution to reduce the test set and guarantee high fault coverage [6]–[8]. In weighted random tests, logic is added to change the probability of the logic value 1 or 0 occurring at each primary input. In [9]–[11], novel deterministic BIST schemes using bit flipping or bit fixing have been proposed. In these schemes, the sequence of pseudorandom test patterns is modified
Manuscript received October 4, 2004; revised January 7, 2005 and March 25, 2005. This paper was recommended by Associate Editor S. Hellebrand. The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TCAD.2005.855977 0278-0070/$20.00 © 2006 IEEE
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 5, MAY 2006
by embedding deterministic test patterns in the sequence with some sequence-modifying logic. Other solution is the compression of deterministic test sets. One class of test compression schemes is by using a variety of codes to encode the original test cubes. Theses include run-length codes [12], statistical codes [13], Golomb codes [14], and packet-based compression [15]. Another class is to use some counters such as folding counters [16], [17] and twisted-ring counters [18] in order to embed deterministic test patterns into a longer BIST pattern sequence. The next class is using LFSR reseeding [19]–[25]. The original test compression methodology using LFSR reseeding was proposed in [19]. A seed is loaded into an LFSR, and, then, the LFSR is run in an autonomous mode to fill a set of scan chains with a deterministic test pattern. If the maximum length of each scan chain is L, then the LFSR is run for L cycles to fill the scan chains. Different seeds generate different test patterns, and for a given set of deterministic test cubes [test patterns where bits unassigned by automatic test pattern generation (ATPG) are left as “don’t cares”], the corresponding seeds can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. In [19], in order to keep the probability of not finding a solution for the system of linear equations less than 10−6 , the LFSR degree should be larger than smax + 20,where smax is the largest number of specified bits in any test cube in the test set. In order to improve the encoding efficiency of the basic LFSR reseeding scheme, many methods have been proposed [20]–[25]. In [20], a reseeding methodology based on multiple-polynomial linear feedback shift registers (MP-LFSR) has been proposed. This method requires degree smax of the MP-LFSR. In [21], a variable length reseeding methodology has been proposed to optimize the memory allocation for seeds. In [22], a partial reseeding scheme using smaller size seeds than the LFSR degree has been proposed. In [23], a two-stage compression scheme combining LFSR reseeding and statistical coding has been proposed. In [24] and [25], techniques where the LFSR size does not rely on the maximum number of specified bits in the test cube set have been proposed. Krishna and Touba [24] proposed a three-stage continuous-flow linear decompression scheme that uses a variable number of bits to encode each cube. In [25], an LFSR reseeding scheme with variable length polynomials has been proposed. Here, the test cubes with a larger number of specified bits are encoded with LFSR polynomial of higher degree while test cubes with a smaller number of specified bits are encoded with LFSR polynomial of lower degree. This paper proposes a new compression technique to increase the encoding efficiency of test compression based on LFSR reseeding. The proposed scheme combines the previous reseeding scheme with variable-degree LFSRs and a bit-fixing technique in order to reduce the amount of data to be encoded. After a set of random tests, the deterministic test set in the LFSR reseeding stage tends to have a biased probability of the logic value 1 or 0 at each primary input [6]–[8]. Therefore, if such biased inputs are fixed to the logic value 1 or 0 with some combinational logic, then the amount of data to be encoded by the LFSR can be reduced. For the reduced test set, a variable-degree LFSR is applied for reseeding. This scheme encodes each test cube with an LFSR polynomial of different degree according to its number of specified bits [25]. Therefore, the size of the encoded data can be optimized according to the number of specified bits in each test cube. The variable-degree LFSR can be implemented by slightly modifying a traditional MP-LFSR, and the bit-fixing logic (BFL) can be implemented with little combinational logic. The experimental results based on the largest ISCAS 89 benchmark circuits show that the proposed compression method can provide better encoding efficiency than previous reseeding methods with adequate hardware overhead.
Fig. 1.
Bit-fixing scheme example.
Fig. 2.
Average ratio of fixed bits according to random tests.
II. P ROPOSED D ECOMPRESSION A RCHITECTURE A. Bit-Fixing Scheme Usually, the deterministic test set to be encoded by LFSR reseeding tends to have a biased probability for the logic value 1 or 0 at each primary input. The biased inputs are fixed to the logic value 1 or 0 with some combinational logic, so that the amount of data to be encoded by the LFSR can considerably be reduced. The combinational logic for bit fixing has to set some primary input to the logic value 0 (or 1), if the corresponding probability of the logic value 0 (or 1) is one. Otherwise, the test pattern from the pseudorandom test pattern generator, such as an LFSR, is directly applied to the CUT. Fig. 1 shows an example of applying the bit fixing scheme. In contrast to the original bit-fixing technique in [9], the bit-fixing scheme in this application fixes bits for the complete test set so that the bit-fixing sequence generator is controlled only by a bit counter. The bit positions 0 and 3 in Fig. 1(a) are biased to the logic values 0 and 1, respectively, so they can be fixed
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 5, MAY 2006
Fig. 3.
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Proposed test decompression scheme.
to these logic values to reduce the amount of data to be encoded. Since the logic values at the bit position 2 are all “don’t cares” for all the test cubes, this position can be used for logic optimization. The bit-fixing scheme can be implemented with a small combinational logic and can reduce the data space for encoding. Fig. 2 shows the experimental results for the ratio of the number of fixed bits in the deterministic test sets used for the ISCAS 89 benchmark circuits. According to the number of random tests applied, the average numbers of the fixed bits in the deterministic test cubes are calculated. For the larger ISCAS 89 benchmark circuits (s5378, s9234, s13207, s15850, s38417, and s38584), the average ratios of the fixed bits are represented by black bars. With the bit-fixing technique, about 20% of the data to be encoded could be reduced so that the final encoded data size could be optimized. B. Final Stage The proposed scheme consists of four subblocks, namely, a variabledegree polynomial LFSR (VD-LFSR), a polynomial decoder, a bitfixing sequence generator, and a test state controller (TSC) as shown in Fig. 3. The test patterns from the VD-LFSR are modified by fixing bits to adequate logic values, or by bypassing the bit-fixing sequence generator. Since the biased bit positions are fixed to the corresponding logic values through the bit-fixing sequence generator, the amount of data for encoding can be optimized. In the proposed scheme, polynomials are encoded so that the seeds are grouped together. The “next bit” is appended to the seed to indicate whether the polynomial is changed or not. Using polynomials of different degrees involves variable length seeds. This means that the number of clock cycles required to load a seed into the LFSR may vary according to the
length of the corresponding seed. It is obvious that the number of clock cycles needed to fill the LFSR with a seed depends on the corresponding feedback polynomial. In other words, the location of the least significant “1” bit of the polynomial decoder signal determines the number of clock cycles to fill the LFSR. For example, if the ith output signal of the decoder Pi is (p0 , p1 , . . . , pm−2 , 1, 0, . . . , 0), then m clock cycles are required to fill the LFSR, because the length of the corresponding seed is m. Therefore, if the most significant k − m + 1 bits of the LFSR are reset, and if the least significant m − 1 bits of the LFSR and the δ-register are set, then the seed can be loaded into the LFSR by shifting until the δ-register becomes zero. The TSC controls the flow of decompression states and can be implemented by a simple finite state machine. Fig. 4 shows the pseudocode for the above encoding process. In order to remove the easy-to-detect faults, pseudorandom test patterns are applied. Then the deterministic test cubes are generated for the remaining hard-to-detect faults. By applying the bit-fixing technique for the entire test set, the data size for encoding will be reduced. For a given deterministic test cube, the length of the LFSR is chosen as s − 10 (s is the number of specified bits in the given test cube), and, then, 16 polynomial candidates of degree polynomial_degree are generated. For each of those 16 polynomial candidates, the system of linear equations based on the selected feedback polynomial is formed. If the system of linear equations does not have any solutions for those polynomial candidates, polynomial_degree is increased, and the process is repeated. If more than one polynomials among the 16 candidates have solutions for the corresponding test cube, then the polynomial that differs in the minimum number of feedback connections from the previous polynomials is selected. This is repeated for all the remaining test cubes.
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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 5, MAY 2006
TABLE II COMPARISON OF ENCODING EFFICIENCY FOR DIFFERENT SCHEMES
TABLE III COMPARISON OF TEST STORAGES FOR DIFFERENT SCHEMES
Fig. 4. Encoding process. TABLE I HARDWARE OVERHEAD OF THE PROPOSED METHOD
III. E XPERIMENTAL R ESULTS The experiments were performed on the largest ISCAS 89 benchmark circuits. For each circuit, 10 000 pseudorandom patterns were applied to remove the easy-to-detect faults, and then ATPG was performed to generate the deterministic test cubes for the remaining hard faults targeting at 100% fault coverage. Each test cube was encoded into the corresponding seed. Table I presents the hardware overhead of the proposed reseeding scheme. The hardware overhead is given in terms of gate equivalents (GEs), assuming that a two-input NAND gate is one GE. The second column represents the GEs of ISCAS benchmark circuits. The third column shows the GEs of the proposed reseeding architecture. It includes the GEs of BFL and VD-LFSR. The proposed architecture is implemented by synthesizing with the design compiler from Synopsys. In order to compare the area of the proposed scheme, the areas of the VL-LFSR-based test decompressor [25] are presented in the second column from the right. The last column includes the comparison of the area overheads calculated by dividing the area of the proposed scheme by the area in [25]. The average area of the proposed scheme is smaller than the average area in [25] by about 1%. Therefore, the proposed
scheme can be implemented with almost the same area overhead as the VL-LFSR [25]. Table II shows the comparison of the results for the proposed scheme with a variety of other LFSR reseeding schemes in terms of encoding efficiency. The encoding efficiency can be calculated by dividing the total number of the specified bits in the test cubes by the total number of bits required to encode them. It can be seen that the proposed scheme results in the best encoding efficiencies for all the benchmark circuits. The proposed scheme is to combine the VD-LFSR and the bit-fixing technique. Therefore, with the bit-fixing technique, the encoding efficiency can be improved by about 0.66 points on average. Table III shows the comparison of test storages between the proposed method and two previous compression methods. Since the previous methods do not use random fault simulation to remove easy faults, the proposed method omitted the random fault simulation process in this experiment. In all the benchmark circuits, the proposed scheme requires the smallest storage size for the encoded data. IV. C ONCLUSION In this paper, a new test compression methodology using bit fixing and reseeding of variable-degree LFSRs has been proposed. Usually, each primary input tends to have different biased probabilities of the logic value 1 or 0 in deterministic test cubes for random-patternresistant faults. In the proposed scheme, a BFL is attached to reduce the size of the data to be encoded by generating logic values for the biased bit positions. Such a biased bit position covered by the BFL does not have to be encoded so that the application of the bit-fixing technique can reduce the amount of data to be encoded significantly.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 5, MAY 2006
In addition, a reseeding scheme for variable-degree LFSRs is applied in order to solve the problem of variance in the number of specified bits in the test cubes. In this scheme, a test cube with a larger number of specified bits is encoded with an LFSR polynomial of higher degree, while a test with a smaller number of specified bits with an LFSR polynomial of lower degree, so as to optimize the encoding efficiency. The variable-degree LFSR can be implemented by slightly modifying a conventional MP-LFSR. The experimental results based on the larger ISCAS 89 benchmark circuits show that the proposed scheme can provide much better encoding efficiency and less test data storage than the previous methods with adequate hardware overhead. ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their helpful comments to improve this paper. The authors would also like to thank S. Hellebrand for his suggestions and comments during the revision process.
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[19] B. Koenemann, “LFSR-coded test pattern for scan designs,” in Proc. Eur. Test Conf., Munich, Germany, 1991, pp. 237–242. [20] S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Coutois, “Built-in test for circuits with scan based on reseeding of multiplepolynomial linear feedback shift registers,” IEEE Trans. Comput., vol. 44, no. 2, pp. 223–233, Feb. 1995. [21] J. Rajski, J. Tyszer, and N. Zacharia, “Test data decompression for multiple scan designs with boundary scan,” IEEE Trans. Comput., vol. 47, no. 11, pp. 1188–1200, Nov. 1998. [22] C. V. Krishna, A. Jas, and N. A. Touba, “Test vector encoding using partial LFSR reseeding,” in Proc. Int. Test Conf., Baltimore, MD, 2001, pp. 885–893. [23] C. V. Krishna and N. A. Touba, “Reducing test data volume using LFSR reseeding with seed compression,” in Proc. Int. Test Conf., Baltimore, MD, 2002, pp. 321–330. [24] ——, “3-stage variable length continuous-flow scan vector decompression scheme,” in Proc. IEEE VLSI Test Symp., Napa Valley, CA, 2004, pp. 79–86. [25] H.-S. Kim, Y. J. Kim, and S. Kang, “Test-decompression mechanism using a variable-length multiple-polynomial LFSR,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 4, pp. 687–690, Aug. 2003.
R EFERENCES [1] P. H. Bardell, W. McAnney, and J. Savir, Built-in Test for VLSI: PseudoRandom Techniques. New York: Wiley, 1987. [2] V. D. Agrawal, C. R. Kime, and K. K. Saluja, “A tutorial on built-in self-test—Part 1: Principles,” IEEE Des. Test Comput., vol. 10, no. 1, pp. 73–82, Mar. 1993. [3] ——, “A tutorial on built-in self-test—Part 2: Applications,” IEEE Des. Test Comput., vol. 10, no. 2, pp. 69–77, Jun. 1993. [4] V. S. Iyengar and D. Brand, “Synthesis and pseudo-random pattern testable designs,” in Proc. Int. Test Conf., Washington, DC, 1989, pp. 501–508. [5] N. A. Touba and E. J. McCluskey, “Test point insertion based on path tracing,” in Proc. VLSI Test Symp., Princeton, NJ, 1996, pp. 2–8. [6] F. Brglez, C. Gloster, and G. Kedem, “Hardware-based weighted random pattern generation for boundary scan,” in Proc. Design Automation Conf., Las Vegas, NV, 1989, pp. 264–274. [7] H.-J. Wunderlich, “Multiple distributions for biased random test patterns,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, no. 6, pp. 584–593, Jun. 1990. [8] H.-S. Kim, J.-K. Lee, and S. Kang, “A new multiple weight set calculation algorithm,” in Proc. Int. Test Conf., Baltimore, MD, 2001, pp. 878–894. [9] N. A. Touba and E. J. McCluskey, “Altering a pseudo-random bit sequence for scan-based BIST,” in Proc. Int. Test Conf., Washington, DC, 1996, pp. 167–175. [10] H.-J. Wunderlich and G. Kiefer, “Bit-flipping BIST,” in Proc. IEEE Int. Conf. Computer Aided Design, San Jose, CA, 1996, pp. 337–343. [11] G. Kiefer, H. Vranken, E. J. Marinissen, and H.-J. Wunderlich, “Application of deterministic logic BIST on industrial circuits,” in Proc. Int. Test Conf., Washington, DC, 2000, pp. 105–114. [12] A. Jas and N. A. Touba, “Test vector decompression via cyclical scan chains and its application to testing core-based design,” in Proc. Int. Test Conf., Washington, DC, 1998, pp. 458–464. [13] A. Jas, B. Pouya, and N. A. Touba, “Scan vector compression/ decompression using statistical coding,” in Proc. IEEE VLSI Test Symp., Dana Point, CA, 1999, pp. 114–120. [14] A. Chandra and K. Chakrabarty, “Test data compression for system-ona-chip using Golomb codes,” in Proc. VLSI Test Symp., Montreal, Canada, 2000, pp. 113–120. [15] E. H. Volkerink, A. Khoche, and S. Mitra, “Packet-based input test data compression techniques,” in Proc. Int. Test Conf., Baltimore, MD, 2002, pp. 154–163. [16] S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A mixed mode BIST scheme based on reseeding of folding counters,” in Proc. Int. Test Conf., Washington, DC, 2000, pp. 778–784. [17] H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Two-dimensional test data compression for scan-based deterministic BIST,” in Proc. Int. Test Conf., Baltimore, MD, 2001, pp. 894–902. [18] A. Chandra, K. Chakrabarty, and S. R. Das, “On using twisted-ring counters for testing embedded cores in system-on-a-chip-design,” in Proc. IEEE Instrumentation and Measurement Technology Conf., Budapest, Hungary, 2001, pp. 216–220.
Practical Repeater Insertion for Low Power: What Repeater Library Do We Need? Xun Liu, Yuantao Peng, and Marios C. Papaefthymiou Abstract—This paper investigates the problem of repeater insertion for low power under a given timing budget. A novel repeater insertion algorithm is proposed to compute the optimal repeater number and width in the discrete solution space, as defined by a given repeater library. Using the proposed algorithm, two practical and highly important questions are addressed. Given a certain tolerance to the degradation of repeater power dissipation, 1) how coarse could the repeater size granularity be? 2) What range should repeater widths be in? The experimental results provide valuable insights into repeater library design. Specifically, the investigation reveals that coarse repeater size granularities can be used to reduce the library size by more than 87% with merely a 4% power degradation. Moreover, for two-pin interconnects with various wire lengths and timing targets, the range of optimal repeater sizes for low power is limited, indicating that a low-cost small-size repeater library, if well designed, is adequate to provide high-quality repeater insertion solutions. The proposed scheme can be used in early design stages to generate a compact repeater library that is passed on to other repeater insertion algorithms. Index Terms—Interconnect, repeater insertion low power.
I. I NTRODUCTION Due to the ever increasing chip dimensions and the decreasing transistor feature size, global interconnects have become the dominant performance limitation for current very large scale integration (VLSI) chip designs. Repeaters are often inserted into global interconnects to reduce signal delays. Consequently, the number of repeaters is
Manuscript received November 20, 2004; revised February 28, 2005. This paper was recommended by Associate Editor J. Lillis. X. Liu and Y. Peng are with the Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695 USA (e-mail: [email protected]; [email protected]). M. C. Papaefthymiou is with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TCAD.2005.855968
0278-0070/$20.00 © 2006 IEEE
of the metal path P1 -to-P2 (black) and P3 -to-P4 (gray) are 0.5 and 0.3 nH, respectively, and the coupling coefficient between these two inductances is 0.8. The transformer is unbalanced by the asymmetrical coupling coefficient of a nearby inductance of 0.2 nH (white), where the coupling coefficients to the upper spiral structure (k) is five times larger than that of the lower spiral structure (k ). The resistances associated with the inductance account for the finite Q of 10 at 5 GHz, and the parasitic capacitances are omitted for simplicity. The extracted response [∆s], as shown in Figs. 7 and 8, has an identical response, proving that the proposed method is accurate and free from any approximation or assumption. The elements of [∆s]4 that are not shown in Fig. 7 are the ones with magnitudes below −120 dB, where the simulation’s numerical errors became predominant. V. C ONCLUSION A new method for extracting mixed-mode s-parameters is presented based on attaching additional circuits to the four-port or three-port circuit. The results are calculated using SPICE. Verification shows that this method is accurate and free from any restrictions or approximations. Furthermore, this new method can provide intuitive information on the relations between the extracted [∆s] and the circuit’s operation. The proposed SPICE-based extraction method will be of practical value for IC and circuit designers who are tied to the SPICE programs by reason of IC CAD tool flow or prior simulation expertise. R EFERENCES [1] K. Kurokawa, “Power waves and the scattering matrix,” IEEE Trans. Microw. Theory Tech., vol. MTT-13, no. 2, pp. 194–202, Mar. 1965. [2] G. Gonzalez, Microwave Transistor Amplifiers; Analysis and Design, Sec. 1.6, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 1997. [3] D. E. Bockelman and W. R. Eisenstadt, “Combined differential-and common mode scattering parameters: Theory and simulation,” IEEE Trans. Microw. Theory Tech., vol. 43, no. 7, pp. 1530–1539, Jul. 1995. [4] K. Jung and W. R. Eisenstadt, “SPICE-based mixed-mode S-parameter calculations for four port circuits,” in Proc. 62nd ARFTG Microwave Measurements Conf.—Differential Measurements, Boulder, CO, Dec. 2003, pp. 181–186. [5] R. Goyal, “S-parameter output from the SPICE program,” IEEE Circuit and Device Magazine—Section: Circuit Simulation and Modeling, vol. 4, no. 2, pp. 28–29, Mar. 1988. [6] S. Kodali and D. J. Allstot, “A symmetric miniature 3D inductor,” in Proc. Int. Symp. Circuits Systems, Bangkok, Thailand, May 2003, vol. 1, pp. 89–92.
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Increasing Encoding Efficiency of LFSR Reseeding-Based Test Compression Hong-Sik Kim and Sungho Kang
Abstract—A new methodology to increase the encoding efficiency of test compression based on linear feedback shift registers (LFSRs) is proposed. The proposed method combines LFSR reseeding and bit fixing. Deterministic test patterns tend to have a biased probability of the logic value 1 or 0 at each primary input. If such biased inputs are fixed to the logic value 1 or 0 with some combinational logic, then the amount of data to be encoded by the LFSR will be considerably reduced. Additionally, in order to reduce the encoded data volume much further, a variable degree of the LFSR polynomial is employed. In the variable-degree LFSR scheme, a test cube with less specified bits is encoded with an LFSR polynomial of lower degree, while a test cube with more specified bits is encoded with an LFSR polynomial of higher degree. Experimental results for the larger ISCAS 89 benchmark circuits show that the proposed scheme can increase the encoding efficiency with little hardware overhead compared to previous schemes. Index Terms—Built-in self-test, linear feedback shift register (LFSR) reseeding, scan testing, test compression.
I. I NTRODUCTION Highly developed deep submicron technology has enabled the implementation of large very large scale integrated (VLSI) systems like systems on a chip (SOCs). In those large SOC designs, intellectual property (IP) cores such as processor cores, a large size embedded memories, and mixed signal, analog, as well as radio frequency (RF) cores are integrated into a single chip. The more IP cores are used, the larger test data volumes are required. Therefore, in order to apply the large volume of test patterns to a chip under test, the automatic test equipment (ATE) requires large memory storage, and this increases the cost of the tester. In addition, since the number of external input–output (IO) ports of a chip and the number of ATE channel are limited, test is a very time-consuming task. Built-in self-test (BIST) is widely known as a good solution for testing the individual IP cores [1]–[3]. As a BIST pattern generator, a pseudorandom test pattern generator like a linear feedback shift register (LFSR) is widely adopted due to its low hardware overhead. However, in case that there are many random-pattern-resistive faults in the circuit under test (CUT), it is difficult to achieve a high fault coverage with an adequate number of test patterns. To overcome this problem, several solutions have been proposed [4]–[11]. Test point insertion can reduce the test set or the test time while providing high fault coverage [4], [5]. This design for testability (DFT) technique is used to modify the CUT to be more random pattern testable, but this kind of DFT application can exert timing impact on the designed circuit by inserting redundant logic on the critical path. Weighted random test is also a good solution to reduce the test set and guarantee high fault coverage [6]–[8]. In weighted random tests, logic is added to change the probability of the logic value 1 or 0 occurring at each primary input. In [9]–[11], novel deterministic BIST schemes using bit flipping or bit fixing have been proposed. In these schemes, the sequence of pseudorandom test patterns is modified
Manuscript received October 4, 2004; revised January 7, 2005 and March 25, 2005. This paper was recommended by Associate Editor S. Hellebrand. The authors are with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TCAD.2005.855977 0278-0070/$20.00 © 2006 IEEE
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by embedding deterministic test patterns in the sequence with some sequence-modifying logic. Other solution is the compression of deterministic test sets. One class of test compression schemes is by using a variety of codes to encode the original test cubes. Theses include run-length codes [12], statistical codes [13], Golomb codes [14], and packet-based compression [15]. Another class is to use some counters such as folding counters [16], [17] and twisted-ring counters [18] in order to embed deterministic test patterns into a longer BIST pattern sequence. The next class is using LFSR reseeding [19]–[25]. The original test compression methodology using LFSR reseeding was proposed in [19]. A seed is loaded into an LFSR, and, then, the LFSR is run in an autonomous mode to fill a set of scan chains with a deterministic test pattern. If the maximum length of each scan chain is L, then the LFSR is run for L cycles to fill the scan chains. Different seeds generate different test patterns, and for a given set of deterministic test cubes [test patterns where bits unassigned by automatic test pattern generation (ATPG) are left as “don’t cares”], the corresponding seeds can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. In [19], in order to keep the probability of not finding a solution for the system of linear equations less than 10−6 , the LFSR degree should be larger than smax + 20,where smax is the largest number of specified bits in any test cube in the test set. In order to improve the encoding efficiency of the basic LFSR reseeding scheme, many methods have been proposed [20]–[25]. In [20], a reseeding methodology based on multiple-polynomial linear feedback shift registers (MP-LFSR) has been proposed. This method requires degree smax of the MP-LFSR. In [21], a variable length reseeding methodology has been proposed to optimize the memory allocation for seeds. In [22], a partial reseeding scheme using smaller size seeds than the LFSR degree has been proposed. In [23], a two-stage compression scheme combining LFSR reseeding and statistical coding has been proposed. In [24] and [25], techniques where the LFSR size does not rely on the maximum number of specified bits in the test cube set have been proposed. Krishna and Touba [24] proposed a three-stage continuous-flow linear decompression scheme that uses a variable number of bits to encode each cube. In [25], an LFSR reseeding scheme with variable length polynomials has been proposed. Here, the test cubes with a larger number of specified bits are encoded with LFSR polynomial of higher degree while test cubes with a smaller number of specified bits are encoded with LFSR polynomial of lower degree. This paper proposes a new compression technique to increase the encoding efficiency of test compression based on LFSR reseeding. The proposed scheme combines the previous reseeding scheme with variable-degree LFSRs and a bit-fixing technique in order to reduce the amount of data to be encoded. After a set of random tests, the deterministic test set in the LFSR reseeding stage tends to have a biased probability of the logic value 1 or 0 at each primary input [6]–[8]. Therefore, if such biased inputs are fixed to the logic value 1 or 0 with some combinational logic, then the amount of data to be encoded by the LFSR can be reduced. For the reduced test set, a variable-degree LFSR is applied for reseeding. This scheme encodes each test cube with an LFSR polynomial of different degree according to its number of specified bits [25]. Therefore, the size of the encoded data can be optimized according to the number of specified bits in each test cube. The variable-degree LFSR can be implemented by slightly modifying a traditional MP-LFSR, and the bit-fixing logic (BFL) can be implemented with little combinational logic. The experimental results based on the largest ISCAS 89 benchmark circuits show that the proposed compression method can provide better encoding efficiency than previous reseeding methods with adequate hardware overhead.
Fig. 1.
Bit-fixing scheme example.
Fig. 2.
Average ratio of fixed bits according to random tests.
II. P ROPOSED D ECOMPRESSION A RCHITECTURE A. Bit-Fixing Scheme Usually, the deterministic test set to be encoded by LFSR reseeding tends to have a biased probability for the logic value 1 or 0 at each primary input. The biased inputs are fixed to the logic value 1 or 0 with some combinational logic, so that the amount of data to be encoded by the LFSR can considerably be reduced. The combinational logic for bit fixing has to set some primary input to the logic value 0 (or 1), if the corresponding probability of the logic value 0 (or 1) is one. Otherwise, the test pattern from the pseudorandom test pattern generator, such as an LFSR, is directly applied to the CUT. Fig. 1 shows an example of applying the bit fixing scheme. In contrast to the original bit-fixing technique in [9], the bit-fixing scheme in this application fixes bits for the complete test set so that the bit-fixing sequence generator is controlled only by a bit counter. The bit positions 0 and 3 in Fig. 1(a) are biased to the logic values 0 and 1, respectively, so they can be fixed
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 5, MAY 2006
Fig. 3.
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Proposed test decompression scheme.
to these logic values to reduce the amount of data to be encoded. Since the logic values at the bit position 2 are all “don’t cares” for all the test cubes, this position can be used for logic optimization. The bit-fixing scheme can be implemented with a small combinational logic and can reduce the data space for encoding. Fig. 2 shows the experimental results for the ratio of the number of fixed bits in the deterministic test sets used for the ISCAS 89 benchmark circuits. According to the number of random tests applied, the average numbers of the fixed bits in the deterministic test cubes are calculated. For the larger ISCAS 89 benchmark circuits (s5378, s9234, s13207, s15850, s38417, and s38584), the average ratios of the fixed bits are represented by black bars. With the bit-fixing technique, about 20% of the data to be encoded could be reduced so that the final encoded data size could be optimized. B. Final Stage The proposed scheme consists of four subblocks, namely, a variabledegree polynomial LFSR (VD-LFSR), a polynomial decoder, a bitfixing sequence generator, and a test state controller (TSC) as shown in Fig. 3. The test patterns from the VD-LFSR are modified by fixing bits to adequate logic values, or by bypassing the bit-fixing sequence generator. Since the biased bit positions are fixed to the corresponding logic values through the bit-fixing sequence generator, the amount of data for encoding can be optimized. In the proposed scheme, polynomials are encoded so that the seeds are grouped together. The “next bit” is appended to the seed to indicate whether the polynomial is changed or not. Using polynomials of different degrees involves variable length seeds. This means that the number of clock cycles required to load a seed into the LFSR may vary according to the
length of the corresponding seed. It is obvious that the number of clock cycles needed to fill the LFSR with a seed depends on the corresponding feedback polynomial. In other words, the location of the least significant “1” bit of the polynomial decoder signal determines the number of clock cycles to fill the LFSR. For example, if the ith output signal of the decoder Pi is (p0 , p1 , . . . , pm−2 , 1, 0, . . . , 0), then m clock cycles are required to fill the LFSR, because the length of the corresponding seed is m. Therefore, if the most significant k − m + 1 bits of the LFSR are reset, and if the least significant m − 1 bits of the LFSR and the δ-register are set, then the seed can be loaded into the LFSR by shifting until the δ-register becomes zero. The TSC controls the flow of decompression states and can be implemented by a simple finite state machine. Fig. 4 shows the pseudocode for the above encoding process. In order to remove the easy-to-detect faults, pseudorandom test patterns are applied. Then the deterministic test cubes are generated for the remaining hard-to-detect faults. By applying the bit-fixing technique for the entire test set, the data size for encoding will be reduced. For a given deterministic test cube, the length of the LFSR is chosen as s − 10 (s is the number of specified bits in the given test cube), and, then, 16 polynomial candidates of degree polynomial_degree are generated. For each of those 16 polynomial candidates, the system of linear equations based on the selected feedback polynomial is formed. If the system of linear equations does not have any solutions for those polynomial candidates, polynomial_degree is increased, and the process is repeated. If more than one polynomials among the 16 candidates have solutions for the corresponding test cube, then the polynomial that differs in the minimum number of feedback connections from the previous polynomials is selected. This is repeated for all the remaining test cubes.
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TABLE II COMPARISON OF ENCODING EFFICIENCY FOR DIFFERENT SCHEMES
TABLE III COMPARISON OF TEST STORAGES FOR DIFFERENT SCHEMES
Fig. 4. Encoding process. TABLE I HARDWARE OVERHEAD OF THE PROPOSED METHOD
III. E XPERIMENTAL R ESULTS The experiments were performed on the largest ISCAS 89 benchmark circuits. For each circuit, 10 000 pseudorandom patterns were applied to remove the easy-to-detect faults, and then ATPG was performed to generate the deterministic test cubes for the remaining hard faults targeting at 100% fault coverage. Each test cube was encoded into the corresponding seed. Table I presents the hardware overhead of the proposed reseeding scheme. The hardware overhead is given in terms of gate equivalents (GEs), assuming that a two-input NAND gate is one GE. The second column represents the GEs of ISCAS benchmark circuits. The third column shows the GEs of the proposed reseeding architecture. It includes the GEs of BFL and VD-LFSR. The proposed architecture is implemented by synthesizing with the design compiler from Synopsys. In order to compare the area of the proposed scheme, the areas of the VL-LFSR-based test decompressor [25] are presented in the second column from the right. The last column includes the comparison of the area overheads calculated by dividing the area of the proposed scheme by the area in [25]. The average area of the proposed scheme is smaller than the average area in [25] by about 1%. Therefore, the proposed
scheme can be implemented with almost the same area overhead as the VL-LFSR [25]. Table II shows the comparison of the results for the proposed scheme with a variety of other LFSR reseeding schemes in terms of encoding efficiency. The encoding efficiency can be calculated by dividing the total number of the specified bits in the test cubes by the total number of bits required to encode them. It can be seen that the proposed scheme results in the best encoding efficiencies for all the benchmark circuits. The proposed scheme is to combine the VD-LFSR and the bit-fixing technique. Therefore, with the bit-fixing technique, the encoding efficiency can be improved by about 0.66 points on average. Table III shows the comparison of test storages between the proposed method and two previous compression methods. Since the previous methods do not use random fault simulation to remove easy faults, the proposed method omitted the random fault simulation process in this experiment. In all the benchmark circuits, the proposed scheme requires the smallest storage size for the encoded data. IV. C ONCLUSION In this paper, a new test compression methodology using bit fixing and reseeding of variable-degree LFSRs has been proposed. Usually, each primary input tends to have different biased probabilities of the logic value 1 or 0 in deterministic test cubes for random-patternresistant faults. In the proposed scheme, a BFL is attached to reduce the size of the data to be encoded by generating logic values for the biased bit positions. Such a biased bit position covered by the BFL does not have to be encoded so that the application of the bit-fixing technique can reduce the amount of data to be encoded significantly.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 5, MAY 2006
In addition, a reseeding scheme for variable-degree LFSRs is applied in order to solve the problem of variance in the number of specified bits in the test cubes. In this scheme, a test cube with a larger number of specified bits is encoded with an LFSR polynomial of higher degree, while a test with a smaller number of specified bits with an LFSR polynomial of lower degree, so as to optimize the encoding efficiency. The variable-degree LFSR can be implemented by slightly modifying a conventional MP-LFSR. The experimental results based on the larger ISCAS 89 benchmark circuits show that the proposed scheme can provide much better encoding efficiency and less test data storage than the previous methods with adequate hardware overhead. ACKNOWLEDGMENT The authors would like to thank the anonymous reviewers for their helpful comments to improve this paper. The authors would also like to thank S. Hellebrand for his suggestions and comments during the revision process.
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[19] B. Koenemann, “LFSR-coded test pattern for scan designs,” in Proc. Eur. Test Conf., Munich, Germany, 1991, pp. 237–242. [20] S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, and B. Coutois, “Built-in test for circuits with scan based on reseeding of multiplepolynomial linear feedback shift registers,” IEEE Trans. Comput., vol. 44, no. 2, pp. 223–233, Feb. 1995. [21] J. Rajski, J. Tyszer, and N. Zacharia, “Test data decompression for multiple scan designs with boundary scan,” IEEE Trans. Comput., vol. 47, no. 11, pp. 1188–1200, Nov. 1998. [22] C. V. Krishna, A. Jas, and N. A. Touba, “Test vector encoding using partial LFSR reseeding,” in Proc. Int. Test Conf., Baltimore, MD, 2001, pp. 885–893. [23] C. V. Krishna and N. A. Touba, “Reducing test data volume using LFSR reseeding with seed compression,” in Proc. Int. Test Conf., Baltimore, MD, 2002, pp. 321–330. [24] ——, “3-stage variable length continuous-flow scan vector decompression scheme,” in Proc. IEEE VLSI Test Symp., Napa Valley, CA, 2004, pp. 79–86. [25] H.-S. Kim, Y. J. Kim, and S. Kang, “Test-decompression mechanism using a variable-length multiple-polynomial LFSR,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 11, no. 4, pp. 687–690, Aug. 2003.
R EFERENCES [1] P. H. Bardell, W. McAnney, and J. Savir, Built-in Test for VLSI: PseudoRandom Techniques. New York: Wiley, 1987. [2] V. D. Agrawal, C. R. Kime, and K. K. Saluja, “A tutorial on built-in self-test—Part 1: Principles,” IEEE Des. Test Comput., vol. 10, no. 1, pp. 73–82, Mar. 1993. [3] ——, “A tutorial on built-in self-test—Part 2: Applications,” IEEE Des. Test Comput., vol. 10, no. 2, pp. 69–77, Jun. 1993. [4] V. S. Iyengar and D. Brand, “Synthesis and pseudo-random pattern testable designs,” in Proc. Int. Test Conf., Washington, DC, 1989, pp. 501–508. [5] N. A. Touba and E. J. McCluskey, “Test point insertion based on path tracing,” in Proc. VLSI Test Symp., Princeton, NJ, 1996, pp. 2–8. [6] F. Brglez, C. Gloster, and G. Kedem, “Hardware-based weighted random pattern generation for boundary scan,” in Proc. Design Automation Conf., Las Vegas, NV, 1989, pp. 264–274. [7] H.-J. Wunderlich, “Multiple distributions for biased random test patterns,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 9, no. 6, pp. 584–593, Jun. 1990. [8] H.-S. Kim, J.-K. Lee, and S. Kang, “A new multiple weight set calculation algorithm,” in Proc. Int. Test Conf., Baltimore, MD, 2001, pp. 878–894. [9] N. A. Touba and E. J. McCluskey, “Altering a pseudo-random bit sequence for scan-based BIST,” in Proc. Int. Test Conf., Washington, DC, 1996, pp. 167–175. [10] H.-J. Wunderlich and G. Kiefer, “Bit-flipping BIST,” in Proc. IEEE Int. Conf. Computer Aided Design, San Jose, CA, 1996, pp. 337–343. [11] G. Kiefer, H. Vranken, E. J. Marinissen, and H.-J. Wunderlich, “Application of deterministic logic BIST on industrial circuits,” in Proc. Int. Test Conf., Washington, DC, 2000, pp. 105–114. [12] A. Jas and N. A. Touba, “Test vector decompression via cyclical scan chains and its application to testing core-based design,” in Proc. Int. Test Conf., Washington, DC, 1998, pp. 458–464. [13] A. Jas, B. Pouya, and N. A. Touba, “Scan vector compression/ decompression using statistical coding,” in Proc. IEEE VLSI Test Symp., Dana Point, CA, 1999, pp. 114–120. [14] A. Chandra and K. Chakrabarty, “Test data compression for system-ona-chip using Golomb codes,” in Proc. VLSI Test Symp., Montreal, Canada, 2000, pp. 113–120. [15] E. H. Volkerink, A. Khoche, and S. Mitra, “Packet-based input test data compression techniques,” in Proc. Int. Test Conf., Baltimore, MD, 2002, pp. 154–163. [16] S. Hellebrand, H.-G. Liang, and H.-J. Wunderlich, “A mixed mode BIST scheme based on reseeding of folding counters,” in Proc. Int. Test Conf., Washington, DC, 2000, pp. 778–784. [17] H.-G. Liang, S. Hellebrand, and H.-J. Wunderlich, “Two-dimensional test data compression for scan-based deterministic BIST,” in Proc. Int. Test Conf., Baltimore, MD, 2001, pp. 894–902. [18] A. Chandra, K. Chakrabarty, and S. R. Das, “On using twisted-ring counters for testing embedded cores in system-on-a-chip-design,” in Proc. IEEE Instrumentation and Measurement Technology Conf., Budapest, Hungary, 2001, pp. 216–220.
Practical Repeater Insertion for Low Power: What Repeater Library Do We Need? Xun Liu, Yuantao Peng, and Marios C. Papaefthymiou Abstract—This paper investigates the problem of repeater insertion for low power under a given timing budget. A novel repeater insertion algorithm is proposed to compute the optimal repeater number and width in the discrete solution space, as defined by a given repeater library. Using the proposed algorithm, two practical and highly important questions are addressed. Given a certain tolerance to the degradation of repeater power dissipation, 1) how coarse could the repeater size granularity be? 2) What range should repeater widths be in? The experimental results provide valuable insights into repeater library design. Specifically, the investigation reveals that coarse repeater size granularities can be used to reduce the library size by more than 87% with merely a 4% power degradation. Moreover, for two-pin interconnects with various wire lengths and timing targets, the range of optimal repeater sizes for low power is limited, indicating that a low-cost small-size repeater library, if well designed, is adequate to provide high-quality repeater insertion solutions. The proposed scheme can be used in early design stages to generate a compact repeater library that is passed on to other repeater insertion algorithms. Index Terms—Interconnect, repeater insertion low power.
I. I NTRODUCTION Due to the ever increasing chip dimensions and the decreasing transistor feature size, global interconnects have become the dominant performance limitation for current very large scale integration (VLSI) chip designs. Repeaters are often inserted into global interconnects to reduce signal delays. Consequently, the number of repeaters is
Manuscript received November 20, 2004; revised February 28, 2005. This paper was recommended by Associate Editor J. Lillis. X. Liu and Y. Peng are with the Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC 27695 USA (e-mail: [email protected]; [email protected]). M. C. Papaefthymiou is with the Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TCAD.2005.855968
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