interleaved analog to digital converters
An offset and gain calibration method for timeinterleaved analog to digital converters M. Jridi, D. Dallet, G. Monnerie and L. Bossuet Laboratoire IXL – UMR CNRS 5818 – ENSEIRB – Univeristé Bordeaux 1, 351 cours de la libération, 33405 Talence CEDEX – France, tel : 33 5 4000 8391, [email protected] , [email protected], [email protected] and [email protected] . Abstract—This paper deals with the problem of static error mismatch in Time-Interleaved Analog to Digital Converter (TIADC). These deterministic errors between channels degrade the performances of the whole system. Mathematical method is proposed for offset and gain compensation of two TIADCs. Numerical simulation results are exposed to validate the theory and the proposed model.
I.
INTRODUCTION
To increase the sampling rate of analog to digital converter (ADC) without using expensive process technology, the use of Time-Interleaved Analog to Digital Converter (TIADC) has been proposed in [1]. This concept offers a method to increase the sample rate: a TIADC has a parallel structure, where the input analog signal is successively sampled by each ADC (demultiplexer). The digital output is taken from each ADC and reconstructed by means of a multiplexer. Fig. 1 shows the TIADC principle using two ADCs. Nevertheless, the most serious drawback of this technique is that any mismatch between the digitizing channels will degrade badly the performances of the whole system. Consequently, the performances of TIADCs are sensitive to offset and gain mismatches as well as aperture errors between the interleaved channels [2-6]. Much more work has been done on digital or analog calibration method to correct offset and gain mismatches [7-17]. Each method presents its advantages compared to the previous work. Criticisms of many correction algorithms are published in [11] and [12]. In a previous work, we were interested on modeling timing errors in TIADC structure [2] and we were proposed a material environment and methodology for TIADC modeling and calibration [18]. In this paper, we develop a new method to compensate static errors
In section II, we analyze the static error mismatching and we express their influence to spectral parameters. In section III, we study some correction methods and give their advantage and drawback. We expose the Simulink model, detail the principle of our method and present some numerical simulation results to compensate offset and gain effects in the next section. II. STATIC ERRORS ANALYSIS In this section, we study the influence of offset and gain errors mismatching in terms of spectral parameters. A, ω0 , T0 , f 0 represent respectively the input signal amplitude, pulsation, period and frequency. Ts , f s are the sampling period and frequency, as well as res is the ADC resolution. The offset and gain errors are represented by the following terms: O1 ,O 2 , G1 ,G 2 . We will treat, without loss of generality, the case of two time-interleaved ADCs. A. Offset mismatch Considering the TIADC input fed by a pure cosine wave, defined by x ( t ) = A cos ( ω t ) . In case of offset error mismatching, the TIADC data output is [2-6]: 0
y [n ] = A cos ( ω0 nTs ) + O + ∆ O cos ( ωs nTs 2 )
(1)
where O = (O + O ) 2 and ∆O = ( O − O ) 2 . From this relation it will be easy to show that a periodic additive pattern appears at f ( noise ) = f 2 1
2
1
2
s
Now, considering the theoretical signal to noise plus distortion ratio (SNDR) due to the quantization noise
ADC1 sam ple r
INPUT
CK 1
SNDRth = 6,02 res + 1, 76 qu antizer
sam ple r
CK 2
qu antizer
(2)
OUTPUT
Taking into account the offset error mismatch, it can be shown that the resulting SNDR is expressed by :
ADC2 CK 1
(
Figure 1.
)
SNDRoff = 6,02 res + 1, 76 − 10 log10 3 * 22 res −1 ∆O 2 + 1 (3)
CK 2
Time-interleaved ADC structure
The SNDR loss is presented in next equation
∆SNDR = 10log10 (3* 22*res −1 ∆O 2 + 1)
(4)
SNDR loss 25 Theoritical Computed by FF T
To validate these formulas, we compute the SNDR by means of FFT applied to the output signal of a two channel TIADC for different offset error values. The results are summarized in Fig. 2 which contains SNDR loss versus normalized magnitude.
20
SND R loss (dB)
15
B. Gain mismatch In case of gain errors mismatch, the TIADC data output is:
10 5 4.5
4
5
3.5
3 2.5
2 1.5
0
y [ n ] = GA cos ( ω0 nTs ) + ∆G 2 cos ( ( ω0 − ωs 2 ) nTs )
(5)
2
1
s
SNDRgain = 6, 02 res + 1.76 + 20 log10 G
(6)
−10 log10 (3* 22 res −1 ∆G 2 + 1) The SNDR loss is presented in the next equation 2 res −1
(7)
2
∆G + 1)
As in offset mismatch case, we validate the effect of gain mismatch in TIADC performances (see Fig. 3). Fig. 4 contains the TIADC output spectrum using 2048 points FFT with 5e-2 of offset mismatch and 7e-2 of gain mismatch. The spurs due to static error mismatch are shown. III.
-8
PREVIOUS WORK
In this section are summarized some previous works related to the TIADC post digital calibration. SNDR loss 30
-4
-2
0
2
4
6
8 -3
-0.06
- 0.04
-0.02
0 0.02 Gain diff rence
0.04
0.06
0.08
0.1
Theoritical Computed by FF T
Figure 3. SNDR loss versus gain evolution
In [16], a method to improve SFDR with random interleaved sampling method is presented. The idea is to receive the data output without a cyclic way. This method is only applied in case of more than two ADCs to interleave. The resulting sample rate is, in the best case, less than M-1 times the sampling rate of one ADC. In [14], an Hybrid filter bank solution is presented. All mismatching components are attenuated except in the filter transition bands. A further disadvantages is related to the monolithic implementation which need high performance passive component. A LMS algorithm is presented in [19]. This method is applied only for over sampling ADCs. In addition, it can only reduce the non harmonic component magnitude without deleting them. The material implementation is not presented. A FFT based method to evaluate and compensate gain and offset errors of interleaved ADC systems is presented in [8]. However, no hardware description was given and the drawbacks of the FFT implementation are multiple. TIADC withour correction
25
0
Gain mismatch spurs
20
-20 15
-40 SND R loss
10
Magnitude (dB)
SND R loss (dB)
-6
x 10
-0.08
2
0
∆SNDR = 20log10 G − 10 log10 (32
0
-5 -0.1
where ∆G = ( G − G ) 2 , G = ( G + G ) 2 . From this relation it will be easy to show that a periodic additive pattern appears at f ( noise ) = ± f + f 2 . These spurs degrade the resulting SNDR of the output system. 1
1 0.5
3.5
3
2.5
5 2
1.5
1
0
-60
-80
0.5
0 -3
-2
-1
0
1
2
3 -3
x 10
-5 -0.1
-0.08
-0.06
- 0.04
-0.02
0 0.02 Offset dif frence
0.04
0.06
0.08
Figure 2. SNDR loss versus offset evolution
0.1
-100
-120
Offset mismatch 0
0.05
0.1
0.15
0.2 0.25 0.3 0.35 Normalized frequency
Figure 4. TIADC output spectrum
0.4
0.45
0.5
An entirely digital method, is presented in [9-11]. A prototype for two TIADC channels was fabricated. The main drawbacks for this is the time consumption due to the recursive algorithms, the limitation to two TIADC channels and the dc component magnitude increasing.
TIADC with offset correction 0
a
-20
-60
-80
-100
(8)
A. Offset calibration The most commonly way to avoid offset error is to average the output data. The average of the signal presented in (8) is equal to the offset value. Then we subtract this value from the ADC output. The resulting signal is without offset. Fig. 5(a) shows the offset calibrated spectrum. The spurs at f s / 2 is eliminated and the dc component is decreased. B. Gain calibration The gain error is a multiplicative constant noise to the input signal. So the average of this signal is equal to zero and it will be impossible to calibrate using the same way of the offset compensation. The solution consists to square the signal compensated for offset error as shown in the bloc circled in red in Fig. 8. The resulting output is :
-120
2
2
The average return the first term of (9). The function the gain value G . Finally we divide the wrong signal with the extracted gain. Fig. 5(b) shows the offset calibrated spectrum of the two TIADC channels. We note that the spurs located at f s / 2 − f in is eliminated and the noise floor is decreased.
0.1
0.15
0.2 0.25 0.3 Normalized frequency
0.35
0.4
0.45
0.5
b
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110
2
f ( u ) extract
0.05
TIADC with offset and gain correction
y ( n ) = { A (1 + G ) + A (1 + G ) cos ( 2ω0 nTs )} / 2 (9) 2
0
-10
Magnitude (dB)
x ( t ) = O + A(1 + G ) cos ( ω0t )
Magnitude (dB)
-40
IV. STATIC ERRORS CALIBRATION In this section, is presented a method to compensate static errors of TIADC structure. This method described with only two TIADC channels, can be extended to any number of channels. Offset and gain are modeled as follow:
0
0.05
0.1
0.15
0.2 0.25 0.3 Normalized frequency
0.35
0.4
0.45
0.5
Figure 5. Output spectrum after : (a)offset calibration, (b) gain calibration SFDR evolution 55 W ithout c orrection W ith offset corr ection W ith offset and gain c orrection
50
45
40
SFD R (dB)
C. Model validation To validate our method, a TIADC structure is modeled using Simulink. The model details are presented in [2]. An embedded function to determine the average is developed. The SFDR is computed using ECT standard (see Fig. 7). We make the input signal magnitude varied from small values to the full-scale. The SFDR improvement is about 7dB to 20dB with offset calibration and 15dB to 30dB with offset and gain correction.
35
30
25
20
15
10 -18
-16
-14
-12 -10 -8 -6 Nor malized input magnitude(dB)
-4
Figure 6. SFDR versus normalized magnitude
-2
0
Gain compensation
Offset compensation
Figure 7. TIADC model with offset and gain calibration
V. CONCLUSION In this paper a new method to compensate static errors in TIADC structures is presented. The simulation results are conform with the theatrical equations. The SFDR evolution shows the importance of the post digital calibration. As a future work, we have to correct timing and nonlinearity errors in order to implement a complete solution for TIADC post digital compensation.. REFERENCES [1] [2]
[3] [4]
[5]
[6]
[7]
[8]
W.C.Black and D.A,Hodges,” Time interleaved data arrays”, IEEE Journal of solid state circuit, VOL SC15,No6, December 1980. M. Jridi, R. Shirakawa and D. Dallet, “ Aperture jitter and timing skew analyses in ADC structures”, in 4th Imeko Symposium on new technologies in measurement and instrumentation and 10th Workshop on ADC modelling and testing. A. Montijo and K. Rush, “Accuracy in interleaved ADC system,” Hewlett-Packard J., pp. 38–46, 1993. A. Petraglia and S.K.Mitra “Analysis of mismatch effects among A/D converter in a time interleaved waveform digitizer”, IEEE trans on instrumentation and measurement, VOL 40, N 5, October 1991 N.Kurosawa, H KOBAYASHI, K Maryouma, H.Sugawara and K.Kobayashi, “ Explicit analysis of channel mismatch effects in time interleaved ADC systems”, IEEE Trans on circuit and systems-I: Fundamental theory and application, VOL48, No 3, Marsh 2001. G.Léger, E.J.Peralias, A.rueda and J.L.Huertas, “ Impact of random channel mismatch on the SNR and SFDR of time Interleaved ADCs”,IEEE Trans on circuit and systems –I : Regular paper, VOL51, No 1 January 2004. J. Elbomsson and J.-E. Ekliind, “Blind estimation of timing errors in interleaved AD converters,” in Proc. ICASSP 2001, VOL. 6, 2001, pp. 3913–3916. J.M.D. Pareira, P.M.B.Sgirao and A.M.Cruz Serra, “An FFT based method to evaluate and compensate gain and offset errors of interleaved ADC systems”, IEEE Trans on instrumentation and measurement, VOL 53 NO 2 April 2004.
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
Daihung Fu, Kenneth C. Dyer, Stephen H. Lewis and Paul J. Hurst, “A digital background calibration technique for time interleaved analog to digital converters“, in IEEE journal of Solid-States Circuits, Vol. 33, NO. 12, December 1998 S. M. Jamal, Daihung Fu, Kenneth C. Dyer, Stephen H. Lewis, “ A 10-bit 120MS/s Time interleaved analog to digital converters with digital background calibration” ISSCC, Feb. 2002, papier number 10.4. S. M. Jamal, Daihung Fu, Mahendra P. Singh, Kenneth C. Dyer, Paul J. Hurst and Stephen H. Lewis ,“ Calibration of sample-time error in two-channel time interleaved analog-to-digital converters“ DRAFT, October 8 2003. David Camarero, Jean. F Naviner and Patrick Loumeau, « Digital background and blind calibration for clock skew error in time interleaved analog –to-digital converters »SBCCI’04 September 7, 2004. Christian Vogel and Heinz Koeppl, “ Behavioral modeling of time interleaved ADCs using MATALB”, Proceedings of the Austrochip 2003, October 2003. Christian Vogel and Gernot Kubin, “ Analysis and compensation of nonlinearity mismatches in time interleaved ADC arrays” ISCAS 2004 Vincenzo Ferragina, Andrea Fornasari, Umberti Gatti Piero Malcovati and Franco Maloberti, “ Gain and offset mismatch calibration in time-interleaved multipath A/D Sigma Delta modulators”, IEEE Transaction on circuits and systems, regular paper. Mamoru Tamba, Atsushi Shimizu, Hideharu Munakata, Takanori Komuro, “ A method to improve SFDR with random interleaved sampling method”, ITC 20001. F. Maloberti, P; Estrada, P. Malcovati, A. Valero, « Behavioral modelind and simulation of data converter » BMAS, October 8, 2002. M. Jridi, G. Monnerie, L. Bossuet, D. Dallet, « Two time-interleaved ADC channel structure : analysis and modeling » IEEE IMTC, Sorrecnto, Italy 24-27 April 2006 pp 781-785. A. Ibukic, D. Hummels, “ Continuous gain calibration of parallel Delta Sigma A/D converters” IEEE IMTC, Sorrecnto, Italy 24-27 April 2006 pp 905-909.
I.
INTRODUCTION
To increase the sampling rate of analog to digital converter (ADC) without using expensive process technology, the use of Time-Interleaved Analog to Digital Converter (TIADC) has been proposed in [1]. This concept offers a method to increase the sample rate: a TIADC has a parallel structure, where the input analog signal is successively sampled by each ADC (demultiplexer). The digital output is taken from each ADC and reconstructed by means of a multiplexer. Fig. 1 shows the TIADC principle using two ADCs. Nevertheless, the most serious drawback of this technique is that any mismatch between the digitizing channels will degrade badly the performances of the whole system. Consequently, the performances of TIADCs are sensitive to offset and gain mismatches as well as aperture errors between the interleaved channels [2-6]. Much more work has been done on digital or analog calibration method to correct offset and gain mismatches [7-17]. Each method presents its advantages compared to the previous work. Criticisms of many correction algorithms are published in [11] and [12]. In a previous work, we were interested on modeling timing errors in TIADC structure [2] and we were proposed a material environment and methodology for TIADC modeling and calibration [18]. In this paper, we develop a new method to compensate static errors
In section II, we analyze the static error mismatching and we express their influence to spectral parameters. In section III, we study some correction methods and give their advantage and drawback. We expose the Simulink model, detail the principle of our method and present some numerical simulation results to compensate offset and gain effects in the next section. II. STATIC ERRORS ANALYSIS In this section, we study the influence of offset and gain errors mismatching in terms of spectral parameters. A, ω0 , T0 , f 0 represent respectively the input signal amplitude, pulsation, period and frequency. Ts , f s are the sampling period and frequency, as well as res is the ADC resolution. The offset and gain errors are represented by the following terms: O1 ,O 2 , G1 ,G 2 . We will treat, without loss of generality, the case of two time-interleaved ADCs. A. Offset mismatch Considering the TIADC input fed by a pure cosine wave, defined by x ( t ) = A cos ( ω t ) . In case of offset error mismatching, the TIADC data output is [2-6]: 0
y [n ] = A cos ( ω0 nTs ) + O + ∆ O cos ( ωs nTs 2 )
(1)
where O = (O + O ) 2 and ∆O = ( O − O ) 2 . From this relation it will be easy to show that a periodic additive pattern appears at f ( noise ) = f 2 1
2
1
2
s
Now, considering the theoretical signal to noise plus distortion ratio (SNDR) due to the quantization noise
ADC1 sam ple r
INPUT
CK 1
SNDRth = 6,02 res + 1, 76 qu antizer
sam ple r
CK 2
qu antizer
(2)
OUTPUT
Taking into account the offset error mismatch, it can be shown that the resulting SNDR is expressed by :
ADC2 CK 1
(
Figure 1.
)
SNDRoff = 6,02 res + 1, 76 − 10 log10 3 * 22 res −1 ∆O 2 + 1 (3)
CK 2
Time-interleaved ADC structure
The SNDR loss is presented in next equation
∆SNDR = 10log10 (3* 22*res −1 ∆O 2 + 1)
(4)
SNDR loss 25 Theoritical Computed by FF T
To validate these formulas, we compute the SNDR by means of FFT applied to the output signal of a two channel TIADC for different offset error values. The results are summarized in Fig. 2 which contains SNDR loss versus normalized magnitude.
20
SND R loss (dB)
15
B. Gain mismatch In case of gain errors mismatch, the TIADC data output is:
10 5 4.5
4
5
3.5
3 2.5
2 1.5
0
y [ n ] = GA cos ( ω0 nTs ) + ∆G 2 cos ( ( ω0 − ωs 2 ) nTs )
(5)
2
1
s
SNDRgain = 6, 02 res + 1.76 + 20 log10 G
(6)
−10 log10 (3* 22 res −1 ∆G 2 + 1) The SNDR loss is presented in the next equation 2 res −1
(7)
2
∆G + 1)
As in offset mismatch case, we validate the effect of gain mismatch in TIADC performances (see Fig. 3). Fig. 4 contains the TIADC output spectrum using 2048 points FFT with 5e-2 of offset mismatch and 7e-2 of gain mismatch. The spurs due to static error mismatch are shown. III.
-8
PREVIOUS WORK
In this section are summarized some previous works related to the TIADC post digital calibration. SNDR loss 30
-4
-2
0
2
4
6
8 -3
-0.06
- 0.04
-0.02
0 0.02 Gain diff rence
0.04
0.06
0.08
0.1
Theoritical Computed by FF T
Figure 3. SNDR loss versus gain evolution
In [16], a method to improve SFDR with random interleaved sampling method is presented. The idea is to receive the data output without a cyclic way. This method is only applied in case of more than two ADCs to interleave. The resulting sample rate is, in the best case, less than M-1 times the sampling rate of one ADC. In [14], an Hybrid filter bank solution is presented. All mismatching components are attenuated except in the filter transition bands. A further disadvantages is related to the monolithic implementation which need high performance passive component. A LMS algorithm is presented in [19]. This method is applied only for over sampling ADCs. In addition, it can only reduce the non harmonic component magnitude without deleting them. The material implementation is not presented. A FFT based method to evaluate and compensate gain and offset errors of interleaved ADC systems is presented in [8]. However, no hardware description was given and the drawbacks of the FFT implementation are multiple. TIADC withour correction
25
0
Gain mismatch spurs
20
-20 15
-40 SND R loss
10
Magnitude (dB)
SND R loss (dB)
-6
x 10
-0.08
2
0
∆SNDR = 20log10 G − 10 log10 (32
0
-5 -0.1
where ∆G = ( G − G ) 2 , G = ( G + G ) 2 . From this relation it will be easy to show that a periodic additive pattern appears at f ( noise ) = ± f + f 2 . These spurs degrade the resulting SNDR of the output system. 1
1 0.5
3.5
3
2.5
5 2
1.5
1
0
-60
-80
0.5
0 -3
-2
-1
0
1
2
3 -3
x 10
-5 -0.1
-0.08
-0.06
- 0.04
-0.02
0 0.02 Offset dif frence
0.04
0.06
0.08
Figure 2. SNDR loss versus offset evolution
0.1
-100
-120
Offset mismatch 0
0.05
0.1
0.15
0.2 0.25 0.3 0.35 Normalized frequency
Figure 4. TIADC output spectrum
0.4
0.45
0.5
An entirely digital method, is presented in [9-11]. A prototype for two TIADC channels was fabricated. The main drawbacks for this is the time consumption due to the recursive algorithms, the limitation to two TIADC channels and the dc component magnitude increasing.
TIADC with offset correction 0
a
-20
-60
-80
-100
(8)
A. Offset calibration The most commonly way to avoid offset error is to average the output data. The average of the signal presented in (8) is equal to the offset value. Then we subtract this value from the ADC output. The resulting signal is without offset. Fig. 5(a) shows the offset calibrated spectrum. The spurs at f s / 2 is eliminated and the dc component is decreased. B. Gain calibration The gain error is a multiplicative constant noise to the input signal. So the average of this signal is equal to zero and it will be impossible to calibrate using the same way of the offset compensation. The solution consists to square the signal compensated for offset error as shown in the bloc circled in red in Fig. 8. The resulting output is :
-120
2
2
The average return the first term of (9). The function the gain value G . Finally we divide the wrong signal with the extracted gain. Fig. 5(b) shows the offset calibrated spectrum of the two TIADC channels. We note that the spurs located at f s / 2 − f in is eliminated and the noise floor is decreased.
0.1
0.15
0.2 0.25 0.3 Normalized frequency
0.35
0.4
0.45
0.5
b
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110
2
f ( u ) extract
0.05
TIADC with offset and gain correction
y ( n ) = { A (1 + G ) + A (1 + G ) cos ( 2ω0 nTs )} / 2 (9) 2
0
-10
Magnitude (dB)
x ( t ) = O + A(1 + G ) cos ( ω0t )
Magnitude (dB)
-40
IV. STATIC ERRORS CALIBRATION In this section, is presented a method to compensate static errors of TIADC structure. This method described with only two TIADC channels, can be extended to any number of channels. Offset and gain are modeled as follow:
0
0.05
0.1
0.15
0.2 0.25 0.3 Normalized frequency
0.35
0.4
0.45
0.5
Figure 5. Output spectrum after : (a)offset calibration, (b) gain calibration SFDR evolution 55 W ithout c orrection W ith offset corr ection W ith offset and gain c orrection
50
45
40
SFD R (dB)
C. Model validation To validate our method, a TIADC structure is modeled using Simulink. The model details are presented in [2]. An embedded function to determine the average is developed. The SFDR is computed using ECT standard (see Fig. 7). We make the input signal magnitude varied from small values to the full-scale. The SFDR improvement is about 7dB to 20dB with offset calibration and 15dB to 30dB with offset and gain correction.
35
30
25
20
15
10 -18
-16
-14
-12 -10 -8 -6 Nor malized input magnitude(dB)
-4
Figure 6. SFDR versus normalized magnitude
-2
0
Gain compensation
Offset compensation
Figure 7. TIADC model with offset and gain calibration
V. CONCLUSION In this paper a new method to compensate static errors in TIADC structures is presented. The simulation results are conform with the theatrical equations. The SFDR evolution shows the importance of the post digital calibration. As a future work, we have to correct timing and nonlinearity errors in order to implement a complete solution for TIADC post digital compensation.. REFERENCES [1] [2]
[3] [4]
[5]
[6]
[7]
[8]
W.C.Black and D.A,Hodges,” Time interleaved data arrays”, IEEE Journal of solid state circuit, VOL SC15,No6, December 1980. M. Jridi, R. Shirakawa and D. Dallet, “ Aperture jitter and timing skew analyses in ADC structures”, in 4th Imeko Symposium on new technologies in measurement and instrumentation and 10th Workshop on ADC modelling and testing. A. Montijo and K. Rush, “Accuracy in interleaved ADC system,” Hewlett-Packard J., pp. 38–46, 1993. A. Petraglia and S.K.Mitra “Analysis of mismatch effects among A/D converter in a time interleaved waveform digitizer”, IEEE trans on instrumentation and measurement, VOL 40, N 5, October 1991 N.Kurosawa, H KOBAYASHI, K Maryouma, H.Sugawara and K.Kobayashi, “ Explicit analysis of channel mismatch effects in time interleaved ADC systems”, IEEE Trans on circuit and systems-I: Fundamental theory and application, VOL48, No 3, Marsh 2001. G.Léger, E.J.Peralias, A.rueda and J.L.Huertas, “ Impact of random channel mismatch on the SNR and SFDR of time Interleaved ADCs”,IEEE Trans on circuit and systems –I : Regular paper, VOL51, No 1 January 2004. J. Elbomsson and J.-E. Ekliind, “Blind estimation of timing errors in interleaved AD converters,” in Proc. ICASSP 2001, VOL. 6, 2001, pp. 3913–3916. J.M.D. Pareira, P.M.B.Sgirao and A.M.Cruz Serra, “An FFT based method to evaluate and compensate gain and offset errors of interleaved ADC systems”, IEEE Trans on instrumentation and measurement, VOL 53 NO 2 April 2004.
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
Daihung Fu, Kenneth C. Dyer, Stephen H. Lewis and Paul J. Hurst, “A digital background calibration technique for time interleaved analog to digital converters“, in IEEE journal of Solid-States Circuits, Vol. 33, NO. 12, December 1998 S. M. Jamal, Daihung Fu, Kenneth C. Dyer, Stephen H. Lewis, “ A 10-bit 120MS/s Time interleaved analog to digital converters with digital background calibration” ISSCC, Feb. 2002, papier number 10.4. S. M. Jamal, Daihung Fu, Mahendra P. Singh, Kenneth C. Dyer, Paul J. Hurst and Stephen H. Lewis ,“ Calibration of sample-time error in two-channel time interleaved analog-to-digital converters“ DRAFT, October 8 2003. David Camarero, Jean. F Naviner and Patrick Loumeau, « Digital background and blind calibration for clock skew error in time interleaved analog –to-digital converters »SBCCI’04 September 7, 2004. Christian Vogel and Heinz Koeppl, “ Behavioral modeling of time interleaved ADCs using MATALB”, Proceedings of the Austrochip 2003, October 2003. Christian Vogel and Gernot Kubin, “ Analysis and compensation of nonlinearity mismatches in time interleaved ADC arrays” ISCAS 2004 Vincenzo Ferragina, Andrea Fornasari, Umberti Gatti Piero Malcovati and Franco Maloberti, “ Gain and offset mismatch calibration in time-interleaved multipath A/D Sigma Delta modulators”, IEEE Transaction on circuits and systems, regular paper. Mamoru Tamba, Atsushi Shimizu, Hideharu Munakata, Takanori Komuro, “ A method to improve SFDR with random interleaved sampling method”, ITC 20001. F. Maloberti, P; Estrada, P. Malcovati, A. Valero, « Behavioral modelind and simulation of data converter » BMAS, October 8, 2002. M. Jridi, G. Monnerie, L. Bossuet, D. Dallet, « Two time-interleaved ADC channel structure : analysis and modeling » IEEE IMTC, Sorrecnto, Italy 24-27 April 2006 pp 781-785. A. Ibukic, D. Hummels, “ Continuous gain calibration of parallel Delta Sigma A/D converters” IEEE IMTC, Sorrecnto, Italy 24-27 April 2006 pp 905-909.
