Logic Circuits Operating in Subthreshold Voltages - Semantic Scholar
Logic Circuits Operating in Subthreshold Voltages Jabulani Nyathi and Brent Bero
School of EECS Washington State University 102 Spokane St, Pullman, WA 99164-2752 Phone: 509-335-1157
{jabu,bbero}@eecs.wsu .edu low power aspect of this regime treating speed as a very secondary metric. There have not been significant efforts toward establishing what logic styles are ideal for subthreshold, what optimizations need to be made for both power and speed, in addition noise margin issues have not been analyzed. This study is a first step at addressing these issues. In [I] two logic families are discussed anid methods for keeping the subthreshold currents stable under temperature and process variations are presented. Section 2 of this paper presents the transistor (pMOS/nMOS) configuration that provides more current in subthreshold. In Section 3 a comparison of body biasing schemes in different logic styles is presented, offering designers a choice of improved speed, ultra-low power or a good speed-power trade-off. Section 4 discusses noise margins while in Section 5 the impacts of fan-in and fan-out on subthreshold logic circuits are evaluated and some concluding remarks appear in Section 6.
ABSTRACT
In this paper different logic circuit families operating in the subthreshold region are analyzed. Their performance in terms of power and speed are of particular interest. The study complements existing work that has reported static CMOS circuit performance under different body biasing schemes in the subthreshold region. Further it offers assurances on noise margins with scaling going beyond the 100 nm technology node. Simulations have been performed at the 180 nm technology node using a 6 metal layer TSMC process. A tunable body biasing scheme that allows bulk CMOS circuits to operate efficiently at subthreshold as well as above threshold voltages is introduced. The scheme improves a five-stage NAND ring oscillator switching speed 6X better than the static CMOS configuration while dissipating 18 % less power.
Categories and Subject Descriptors
2. MOS OPERATION IN SUBTHRESHOLD
D.3.3 [Low Power High-speed Subthreshold CMOS Design]: Suitable Logic families and body biasing techniques - swapped body biasing, tunable body biasing and dynamic threshold CMOS
In this study the SPICE device parameters used were extracted from MOSIS and these measured values represent an average from a fabrication lot. These parameters are dependable and previous work has shown a good correlation between systems' simulated results and their measured values.
General Terms
Perfornance, Design, and Theory.
Device leakage currents have been extensively studied primarily with a view of identifying leakage current sources and being able to keep these currents at a minimum [2], [3]. The focus on leakage currents is beginning to shift from this view of minimization to actually using these currents to drive logic [1], [4]. Digital circuits tend to simplify transistor operation, allowing devices to be viewed as switches. When the devices are operated at power supply voltages exceeding the threshold voltages they already exhibit some ill-effects. They do not operate as ideal switches and these effects cannot be viewed differently in subthreshold. In fact the problems are more pronounced in the subthreshold region since these leakage currents are relied upon to drive logic. The leakage currents that are expected to drive logic are present in the devices' OFF state and must be minimized in order to maintain the ultra-low power benefits. There are a number of variables that influence device response and in this study the bulk terminal voltage is the variable of choice. Varying the bulk terminals' potentials provides further insights into device response to changes at the gate and drain/source terminals. The standard configuration has the bulk of the nMOS tied to the ground terminal, while that of the pMOS is tied to the power supply voltage (VDD) for an inverter. This prevents forward biasing the source/drain-to-bulk p/n+ junctions. If the bulk terminal of the nMOS device is raised above ground
Keywords
Subthreshold, ultra-low power, medium-to-high speed, logic styles, noise margins, body biasing, off current.
1. INTRODUCTION
Logic gates are the fundamental building block for high performance data path circuits and they continue to be a topic of interest especially as technologies are scaled to the nanometer regime. However increased leakage currents have led to the design of subthreshold circuits that use these currents to drive the logic [1]. Considerable work on limiting leakage currents has been performed for above threshold systems [2], [3] and there is a distinct difference between designing for ultra-low power and designing for high speed. Much of the work on subthreshold has focused only on the ultraPermission to make digital or hard copies of all or pad of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED'06, October 4-6, 2006, Tegemsee, Germany. Copyright 2006 ACM 1-59593-462-6/06/00 10... $5.00.
131
threshold CMOS circuit has the bulk of the transistor tied to its gate allowing the threshold voltage of the device to change dynamically with the gate input voltage. Increasing the power supply voltage to above threshold with this configuration in effect leads to the device turning OFF.
and the power supply voltage is below threshold, there is a noticeable increase of the drain current. Similarly lowering the bulk voltage of the pMOS device leads to increased drain current. The bulk voltage (VB) allows the p/ni junction to be forward biased thus allowing current flow from the bulk into the source/drain regions. Figure 1 compares the drain currents of a device (nMOS) whose bulk is raised to that of a device whose bulk terminal is at logic 0. With increasing gate-to-source voltage and the bulk voltage at 600 mV the drain current increases by at least an order of magnitude particularly at voltages below the threshold. Above the threshold voltage the drain current is dominated by the saturation current and is thus comparable to the drain current when the bulk is at ground for nMOS and VDO for pMOS. The increase in current in the subthreshold region could lead to increased switching speeds while potentially dissipating less power. Simulations performed at 350, 250 and 180 nm with the bulk terminal of the nMOS at a voltage above 0 V show an increase in the drain-to-source current (IDs) as shown in Figure 1. The pMOS yields similar increases in current when its bulk is tied to ground instead of the standard configuration (bulk tied to VDD). The ability to increase subthreshold currents in this manner calls for the examination of the OFF current (IOFF) with the modified bulk potential. The devices do not effectively turn OFF and would thus dissipate power even when there is no useful work being performed. A configuration that increases the subthreshold currents when the devices are turned ON and reduces these currents when the devices are in their OFF states requires that the bulk of each transistor be tied to its gate. The approach is termed subthreshold dynamic threshold voltage (Sub-DTMOS) and is presented in detail [1].
In this study an adaptive body biasing scheme that selects between operation in the subthreshold or above threshold regions and offers significant performance improvements over a range of power supply voltages (VDD0=0.5*V110 through VDD=1.8 V in a 180 nm TSMC process) has been experimented with. Control of the bulk terminal in this manner offers an option of having tunable circuits that can operate in the ultra-low power range (at voltages below threshold) or at high speed (at voltages above threshold). The approach is termed tunable body biasing (TBB). No simulations have been performed with MTCMOS configuration in this study since this approach is intended for designs that need to limit leakages for above threshold operations. The following section of this paper presents different logic families operating in subthreshold under different body biasing schemes and details the gates' performance evaluations.
3. LOGIC FAMILIES IN SUBTHRESHOLD
Analysis of different logic styles operating in the subthreshold region is essential. This could provide a designer with a meaningful choice depending on what the design calls for: speed, power, reliability (based on noise margins), or a good compromise between high speed and ultra-low power. The study Provides some insights on different logic style performance in the subthreshold region. In this study static CMOS with standard body biasing (nMOS devices' bulk at ground and pMOS devices' bulk terminals at VDD) is considered as reference. Admittedly there are more logic families than discussed here, but these are the most representative ones and results obtained can easily be extended to other logic families. It would also be important to ensure that the work covers the effects of paramnetric variations (environmental as well as process variations) at these low voltages and an interested reader is referred to [1].
1.00E-03 .00E.04 I .00E.05
IDS With VB = 600 mVt
= 1.00E-06
LG)I.OE-07-
.OOE-08
; Region. . of Intere -
/
/
/N
with VB- 0 mnV ID~~~~~S
......
Q 1.00E-09 1lODE-t I I ODE-12
3.1 Performance Evaluation for Differing Body Biasing Schemes with Static CMOS
0
0.1
0.2
0.4 0.5 0.6 0.7 Gate-to-Source Voltage (V)
0.3
0.8
Before examining the different logic style performance attributes under subthreshold voltages, it is instructive to present performnance evaluations of static CMOS under different body biasing schemes. The propagation delay simulation results appear in the bar chart displayed in Figure 2. The results show that swapped body biasing, dynamic threshold CMOS and the tunable body biasing schemes all lead to shorter propagation delays. Propagation delays of Figure 2 are those of static CMOS transmission gate, inverter, NAND2, NOR2 and a two input XOR under the different body biasing conditions. Figure 3 shows the transistor configurations for each of the body biasing schemes that have been simulated to produce the results displayed in Figure 2. In subthreshold voltages DTMOS, SBB and TBB outperform the traditional body biasing technique by approximately a factor of six-to-ten in terms of propagation delay. The tunable body biasing (TBB) scheme is a result of the observation that in subthreshold swapping the bulk connections yields improved delays while above threshold swapping the bulk terminal connections degrades the delays significantly. In order to successfully bridge the speed-
0.9
Figure 1. 180 nm nMOS operation with standard body biasing compared to a configuration with VB=600 mV. Both the nNMOS and pMOS devices show increased OFF current when their bulk terminals are tied to VDD and ground respectively. These observations have led to several body biasing schemes some of which include (i) swapped body biasing (SBB), (ii) dynamic threshold CMOS (DTMOS), (iii) adaptive body biasing (ABB) and (iv) multi-threshold CMOS (MTCMOS) just to name a few. The SBB scheme allows the pMOS devices' well to be connected to ground while the bulks of the nMOS devices are connected to the power supply voltage (VDD). Simulations show that swapped body biasing has diminishing returns past the threshold voltage as a result the technique has been used at low power supply voltages for energy efficient designs. The dynamic
132
power gap the bulk terminals have to be controlled such that the Vcontroi signals of Figure 3(c) reflect these findings. It is an accepted fact that circuits operating in the subthreshold region run at significantly low frequencies (e.g. 200 kHz to 500 kHz at 50 % Vtho) since the target metric is ultra-low power. It is the intention in this work to explore the possibilities of bridging the powerspeed gap between ultra-low power circuits/systems and that of high speed systems.
Very little attention has been paid to the influence of logic style on performance in this regime. Extensive simulations at the 180 nm technology node have been performed for static CMOS, pseudo-nMOS, Domino and pass transistor logic styles. Of interest are the signal propagation delays and Figure 4 shows a comparison of a two input NAND gate's propagation delays under the different logic styles and biasing schemes. The simulations have been performed only at subthreshold voltages with power supply voltages ranging from 0.5*V,1,o to Vtho. Circuit behavior is such that the propagation delays improve with increasing power supply voltage irrespective of biasing scheme nor logic style. The simulation results depicted in Figure 4 are those obtained with a power supply voltage of 0.75*Vtho.
2500
Je 2000 1.2 t50 Z;
-.
( 1500
V
.v--.......
-.
1az
M Transmission Gate M InveTter E Two Input NAND E Two Input NOR O Two linput XOR
n&, 1000
> 500
0
TRADITIONAL
SBB
TBB
DTMIOS
Figure 2. Static CMOS delays under different biasing conditions (standard, SBB, TBB and DTMOS). CMOS NAND2
Pseudo-nMOS NAND2
Domino NAND2
Figure 4. Comparison of propagation delays of a two input NAND gate in different logic styles under different biasing techniques (standard, SBB, TBB and DTMOS). Simulations on inverters, NAND, NOR, XOR and XNOR gates have been performed but only the propagation delays of the NAND gate are shown since all the other gates show similar performance pattems. It is apparent from the graph that Domino logic has significantly longer delays and static CMOS is the better of the three logic styles under any of the bias conditions. Domino logic has longer delays owing to the additional transistor of the pull-down network driven by a clock input. Pseudo-nMOS on the other hand suffers longer delays due to the need to overcome the pull-up device in the event there is a path from the output node to the ground terminal. Pass Transistor Logic will always be fast however this logic style's delays exhibits heavy dependence on the input pattern. A two-input AND gate experiencing switching activity on both inputs simultaneously will see a slow output response compared to a static CMOS AND gate that has the majority of its devices closer to the power supply rails. These reasons therefore leave static CMOS being the logic style to offer better performance. It must be noted that as is the case at above threshold operation the other logic styles can still find wide spread usage in subthreshold operation.
Vcontrol (a) Traditional (b) Swapped (c) Tunable (d) DTMOS configuration body biasing body biasing
Figure 3. Different body biasing schemes' configurations. A more direct way of achieving such performance gains is to increase the power supply voltage to as close to the threshold voltage as possible. At 75 % of the threshold voltage the speed is improved significantly (achieving 8X the frequencies recorded at a VOD that is 0.5*Vtl10) DTMOS, SBB and TBB all have comparable delays however DTMOS and SBB are only good for power supply voltages below threshold. If operation has to span the entire power supply voltage scale from 0V to VDD, it is better to use the TBB approach. The additional circuits required to provide the control voltages (Vcontroi) leads to a 9 % increase in power dissipation for a 32-bit linear feedback shift register and an area overhead of 4 %. In the following delay characteristics of different logic styles configured in the traditional manner are presented and the findings compared to the results of the same logic gates using the swapped body biasing scheme, dynamic threshold CMOS and tunable body biasing schemes.
4. NOISE MARGINS
A subject of importance as power supply voltages are scaled further into subthreshold is that of noise margins. At such small voltages it is possible that a slight change at the input might be misinterpreted by the circuit resulting in an incorrect output. The voltage levels that define the three regions of a digital circuit namely logic 0, the undefined region and logic 1 are examined. Simulations of an inverter under the three body biasing schemes
3.2 Logic Family Gate Delays Under the Various Biasing Schemes
Research on subthreshold circuit operation has focused on device
sizing, the ultra-low power gains and most importantly the best configuration (i.e. how to bias the bulk terminals for best results).
133
five and above is impractical since the RC delay of the series devices significantly increases the propagation delays. These results do not reveal anything new but the exercise remains valuable in that it eliminates the need for speculative evaluation regarding gate performance in subthreshold.
that have been studied with static CMOS used as a reference point once again are recorded. This exercise has been extended to examine a NAND gate's noise margins.
Figure 5 represents the inverter input signal and the corresponding outputs for both the traditional and TBB inverters. The stair step representation of the input allows for better observation of the circuit response to each defined voltage level (the stair). The circuit response to the input can be analyzed using a ramp as an input, but the start of the transition region becomes less distinct with such an input. The power supply voltage is at 376.2 mV and from Figure 5 it can be determined the regions at which the output voltage reaches steady state and the transition region is clear. It has been determined that the logic 0 is valid for an input range of 0-175 mV while a logic 1 is valid for the 200-376.2 mV range with the uncertain region occupying the 175-200 mV range. The nMOS' bulk terminal is at the ground terminal and that of the pMOS at VDD for these results. When the bulk terminals' connections are swapped (SBB or TBB) the ranges are as follows: logic 0 is defined in the range 0-200 mV, logic 1 is in the 225376.2 mV range and the uncertain region occupies the 200-225 mV range. Tunable body biasing has skewed noise margins due to the fact that the inverter is forward biased, causing it to identify a logic 1 more easily. The analysis has been performed only on the static CMOS logic style since it is a foregone conclusion that the pseudo-nMOS logic style degrades noise margins considerably. The static CMOS configuration definitely offers better noise margins. The swapped body biasing scheme gives improved propagation delays but has poor noise margins. The analysis shows that scaling to 90 nm and beyond would still guarantee proper logic levels with full signal swing.
1600
1400
t200 >, 1000 0
c 800
e 600 400 200
OTwo
~
~
~
~
~
!1
*.
,,, ,, .. I
6. CONCLUDING REMARKS
.s v
7. REFERENCES
TR^eD_ut
0we u (uv)
brne
I.2
w_,
Four
This paper has explored the relevance of different logic styles operating in the subthreshold region, concluding that static CMOS outperforms both Domino and pseudo-nMOS in all aspects (except area). The pass transistor logic style though better than static CMOS is limited by the heavy dependence of delays on the input pattems. It has been shown that a newly introduced TBB NAND gate improves propagation delays 6 times better than the standard biased CMOS NAND. Noise margins for devices operating in subthreshold have also been analyzed and the conclusion drawn is that even with scaling beyond 90 nm gate lengths valid logic levels are attainable. The TBB configured circuits have a smaller range of the undefined region and could thus be more sensitive to small fluctuations of the gate signals.
.
,
Three Number of Inputs
Figure 6. Effects of fan-in on propagation delay.
/'RAD o-a
~
-Traditional NAND -:-TBB NAND --- Traditional NOR -TOB NOR
[1] Soeleman, H., Roy, K. and Paul, B. C. "Robust Subthreshold Logic for Ultra-Low Power Operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No 1, February 2001, pp. 90-99. [2] Kao, J., Narenda, S. and Chandrakasan, A., "Subthreshold Leakage Modeling and Reduction Techniques," IEEE/ACM International Conference on Computer Aided Design (ICCAD), November 10-14, 2002, pp.141-148. [3] S. Yang, W. Wolf, N. Vijaykrishnan, T. Xie and W. Wang, "Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100 nm Circuits," 18"' International Conference on VLSI Design, 2005, pp. 165-170. [4] C. Hyung-II Kim, H. Soeleman and K. Roy, "Ultra-LowPower DLMS Adaptive Filter for Hearing Aid Applications," IEEE Transactions on Very Large Scale Integration (VILSI) Systems, Vol. I1, No. 6, December 2003, pp. 1058-1067.
.5 .n
Figure 5. Traditional and TBB inverter input and output signals showing how noise margins are determined.
5. FAN-IN-FAN-OUT CONSIDERATIONS
At such low operating voltages it is highly likely that stacking devices could lead to erroneous results. It is thus instIuctive to evaluate circuit behavior under different fan-in conditions. All the gates analyzed in this study have a fan-out of four (FO4) achieved by having each gate drive four unit sized inverters. The simulation results displayed in Figure 6 are those of the NAND and NOR gates simulated in static CMOS. The swapped body biasing scheme is compared to the standard configuration as the fan-in increases while each gate maintains a constant fan-out (F04). The NOR gate has longer propagation delays owing to the series ptype devices. The swapped body biasing scheme allows for fast switching hence improved/shorter delays. Increasing the fan-in to
134
School of EECS Washington State University 102 Spokane St, Pullman, WA 99164-2752 Phone: 509-335-1157
{jabu,bbero}@eecs.wsu .edu low power aspect of this regime treating speed as a very secondary metric. There have not been significant efforts toward establishing what logic styles are ideal for subthreshold, what optimizations need to be made for both power and speed, in addition noise margin issues have not been analyzed. This study is a first step at addressing these issues. In [I] two logic families are discussed anid methods for keeping the subthreshold currents stable under temperature and process variations are presented. Section 2 of this paper presents the transistor (pMOS/nMOS) configuration that provides more current in subthreshold. In Section 3 a comparison of body biasing schemes in different logic styles is presented, offering designers a choice of improved speed, ultra-low power or a good speed-power trade-off. Section 4 discusses noise margins while in Section 5 the impacts of fan-in and fan-out on subthreshold logic circuits are evaluated and some concluding remarks appear in Section 6.
ABSTRACT
In this paper different logic circuit families operating in the subthreshold region are analyzed. Their performance in terms of power and speed are of particular interest. The study complements existing work that has reported static CMOS circuit performance under different body biasing schemes in the subthreshold region. Further it offers assurances on noise margins with scaling going beyond the 100 nm technology node. Simulations have been performed at the 180 nm technology node using a 6 metal layer TSMC process. A tunable body biasing scheme that allows bulk CMOS circuits to operate efficiently at subthreshold as well as above threshold voltages is introduced. The scheme improves a five-stage NAND ring oscillator switching speed 6X better than the static CMOS configuration while dissipating 18 % less power.
Categories and Subject Descriptors
2. MOS OPERATION IN SUBTHRESHOLD
D.3.3 [Low Power High-speed Subthreshold CMOS Design]: Suitable Logic families and body biasing techniques - swapped body biasing, tunable body biasing and dynamic threshold CMOS
In this study the SPICE device parameters used were extracted from MOSIS and these measured values represent an average from a fabrication lot. These parameters are dependable and previous work has shown a good correlation between systems' simulated results and their measured values.
General Terms
Perfornance, Design, and Theory.
Device leakage currents have been extensively studied primarily with a view of identifying leakage current sources and being able to keep these currents at a minimum [2], [3]. The focus on leakage currents is beginning to shift from this view of minimization to actually using these currents to drive logic [1], [4]. Digital circuits tend to simplify transistor operation, allowing devices to be viewed as switches. When the devices are operated at power supply voltages exceeding the threshold voltages they already exhibit some ill-effects. They do not operate as ideal switches and these effects cannot be viewed differently in subthreshold. In fact the problems are more pronounced in the subthreshold region since these leakage currents are relied upon to drive logic. The leakage currents that are expected to drive logic are present in the devices' OFF state and must be minimized in order to maintain the ultra-low power benefits. There are a number of variables that influence device response and in this study the bulk terminal voltage is the variable of choice. Varying the bulk terminals' potentials provides further insights into device response to changes at the gate and drain/source terminals. The standard configuration has the bulk of the nMOS tied to the ground terminal, while that of the pMOS is tied to the power supply voltage (VDD) for an inverter. This prevents forward biasing the source/drain-to-bulk p/n+ junctions. If the bulk terminal of the nMOS device is raised above ground
Keywords
Subthreshold, ultra-low power, medium-to-high speed, logic styles, noise margins, body biasing, off current.
1. INTRODUCTION
Logic gates are the fundamental building block for high performance data path circuits and they continue to be a topic of interest especially as technologies are scaled to the nanometer regime. However increased leakage currents have led to the design of subthreshold circuits that use these currents to drive the logic [1]. Considerable work on limiting leakage currents has been performed for above threshold systems [2], [3] and there is a distinct difference between designing for ultra-low power and designing for high speed. Much of the work on subthreshold has focused only on the ultraPermission to make digital or hard copies of all or pad of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED'06, October 4-6, 2006, Tegemsee, Germany. Copyright 2006 ACM 1-59593-462-6/06/00 10... $5.00.
131
threshold CMOS circuit has the bulk of the transistor tied to its gate allowing the threshold voltage of the device to change dynamically with the gate input voltage. Increasing the power supply voltage to above threshold with this configuration in effect leads to the device turning OFF.
and the power supply voltage is below threshold, there is a noticeable increase of the drain current. Similarly lowering the bulk voltage of the pMOS device leads to increased drain current. The bulk voltage (VB) allows the p/ni junction to be forward biased thus allowing current flow from the bulk into the source/drain regions. Figure 1 compares the drain currents of a device (nMOS) whose bulk is raised to that of a device whose bulk terminal is at logic 0. With increasing gate-to-source voltage and the bulk voltage at 600 mV the drain current increases by at least an order of magnitude particularly at voltages below the threshold. Above the threshold voltage the drain current is dominated by the saturation current and is thus comparable to the drain current when the bulk is at ground for nMOS and VDO for pMOS. The increase in current in the subthreshold region could lead to increased switching speeds while potentially dissipating less power. Simulations performed at 350, 250 and 180 nm with the bulk terminal of the nMOS at a voltage above 0 V show an increase in the drain-to-source current (IDs) as shown in Figure 1. The pMOS yields similar increases in current when its bulk is tied to ground instead of the standard configuration (bulk tied to VDD). The ability to increase subthreshold currents in this manner calls for the examination of the OFF current (IOFF) with the modified bulk potential. The devices do not effectively turn OFF and would thus dissipate power even when there is no useful work being performed. A configuration that increases the subthreshold currents when the devices are turned ON and reduces these currents when the devices are in their OFF states requires that the bulk of each transistor be tied to its gate. The approach is termed subthreshold dynamic threshold voltage (Sub-DTMOS) and is presented in detail [1].
In this study an adaptive body biasing scheme that selects between operation in the subthreshold or above threshold regions and offers significant performance improvements over a range of power supply voltages (VDD0=0.5*V110 through VDD=1.8 V in a 180 nm TSMC process) has been experimented with. Control of the bulk terminal in this manner offers an option of having tunable circuits that can operate in the ultra-low power range (at voltages below threshold) or at high speed (at voltages above threshold). The approach is termed tunable body biasing (TBB). No simulations have been performed with MTCMOS configuration in this study since this approach is intended for designs that need to limit leakages for above threshold operations. The following section of this paper presents different logic families operating in subthreshold under different body biasing schemes and details the gates' performance evaluations.
3. LOGIC FAMILIES IN SUBTHRESHOLD
Analysis of different logic styles operating in the subthreshold region is essential. This could provide a designer with a meaningful choice depending on what the design calls for: speed, power, reliability (based on noise margins), or a good compromise between high speed and ultra-low power. The study Provides some insights on different logic style performance in the subthreshold region. In this study static CMOS with standard body biasing (nMOS devices' bulk at ground and pMOS devices' bulk terminals at VDD) is considered as reference. Admittedly there are more logic families than discussed here, but these are the most representative ones and results obtained can easily be extended to other logic families. It would also be important to ensure that the work covers the effects of paramnetric variations (environmental as well as process variations) at these low voltages and an interested reader is referred to [1].
1.00E-03 .00E.04 I .00E.05
IDS With VB = 600 mVt
= 1.00E-06
LG)I.OE-07-
.OOE-08
; Region. . of Intere -
/
/
/N
with VB- 0 mnV ID~~~~~S
......
Q 1.00E-09 1lODE-t I I ODE-12
3.1 Performance Evaluation for Differing Body Biasing Schemes with Static CMOS
0
0.1
0.2
0.4 0.5 0.6 0.7 Gate-to-Source Voltage (V)
0.3
0.8
Before examining the different logic style performance attributes under subthreshold voltages, it is instructive to present performnance evaluations of static CMOS under different body biasing schemes. The propagation delay simulation results appear in the bar chart displayed in Figure 2. The results show that swapped body biasing, dynamic threshold CMOS and the tunable body biasing schemes all lead to shorter propagation delays. Propagation delays of Figure 2 are those of static CMOS transmission gate, inverter, NAND2, NOR2 and a two input XOR under the different body biasing conditions. Figure 3 shows the transistor configurations for each of the body biasing schemes that have been simulated to produce the results displayed in Figure 2. In subthreshold voltages DTMOS, SBB and TBB outperform the traditional body biasing technique by approximately a factor of six-to-ten in terms of propagation delay. The tunable body biasing (TBB) scheme is a result of the observation that in subthreshold swapping the bulk connections yields improved delays while above threshold swapping the bulk terminal connections degrades the delays significantly. In order to successfully bridge the speed-
0.9
Figure 1. 180 nm nMOS operation with standard body biasing compared to a configuration with VB=600 mV. Both the nNMOS and pMOS devices show increased OFF current when their bulk terminals are tied to VDD and ground respectively. These observations have led to several body biasing schemes some of which include (i) swapped body biasing (SBB), (ii) dynamic threshold CMOS (DTMOS), (iii) adaptive body biasing (ABB) and (iv) multi-threshold CMOS (MTCMOS) just to name a few. The SBB scheme allows the pMOS devices' well to be connected to ground while the bulks of the nMOS devices are connected to the power supply voltage (VDD). Simulations show that swapped body biasing has diminishing returns past the threshold voltage as a result the technique has been used at low power supply voltages for energy efficient designs. The dynamic
132
power gap the bulk terminals have to be controlled such that the Vcontroi signals of Figure 3(c) reflect these findings. It is an accepted fact that circuits operating in the subthreshold region run at significantly low frequencies (e.g. 200 kHz to 500 kHz at 50 % Vtho) since the target metric is ultra-low power. It is the intention in this work to explore the possibilities of bridging the powerspeed gap between ultra-low power circuits/systems and that of high speed systems.
Very little attention has been paid to the influence of logic style on performance in this regime. Extensive simulations at the 180 nm technology node have been performed for static CMOS, pseudo-nMOS, Domino and pass transistor logic styles. Of interest are the signal propagation delays and Figure 4 shows a comparison of a two input NAND gate's propagation delays under the different logic styles and biasing schemes. The simulations have been performed only at subthreshold voltages with power supply voltages ranging from 0.5*V,1,o to Vtho. Circuit behavior is such that the propagation delays improve with increasing power supply voltage irrespective of biasing scheme nor logic style. The simulation results depicted in Figure 4 are those obtained with a power supply voltage of 0.75*Vtho.
2500
Je 2000 1.2 t50 Z;
-.
( 1500
V
.v--.......
-.
1az
M Transmission Gate M InveTter E Two Input NAND E Two Input NOR O Two linput XOR
n&, 1000
> 500
0
TRADITIONAL
SBB
TBB
DTMIOS
Figure 2. Static CMOS delays under different biasing conditions (standard, SBB, TBB and DTMOS). CMOS NAND2
Pseudo-nMOS NAND2
Domino NAND2
Figure 4. Comparison of propagation delays of a two input NAND gate in different logic styles under different biasing techniques (standard, SBB, TBB and DTMOS). Simulations on inverters, NAND, NOR, XOR and XNOR gates have been performed but only the propagation delays of the NAND gate are shown since all the other gates show similar performance pattems. It is apparent from the graph that Domino logic has significantly longer delays and static CMOS is the better of the three logic styles under any of the bias conditions. Domino logic has longer delays owing to the additional transistor of the pull-down network driven by a clock input. Pseudo-nMOS on the other hand suffers longer delays due to the need to overcome the pull-up device in the event there is a path from the output node to the ground terminal. Pass Transistor Logic will always be fast however this logic style's delays exhibits heavy dependence on the input pattern. A two-input AND gate experiencing switching activity on both inputs simultaneously will see a slow output response compared to a static CMOS AND gate that has the majority of its devices closer to the power supply rails. These reasons therefore leave static CMOS being the logic style to offer better performance. It must be noted that as is the case at above threshold operation the other logic styles can still find wide spread usage in subthreshold operation.
Vcontrol (a) Traditional (b) Swapped (c) Tunable (d) DTMOS configuration body biasing body biasing
Figure 3. Different body biasing schemes' configurations. A more direct way of achieving such performance gains is to increase the power supply voltage to as close to the threshold voltage as possible. At 75 % of the threshold voltage the speed is improved significantly (achieving 8X the frequencies recorded at a VOD that is 0.5*Vtl10) DTMOS, SBB and TBB all have comparable delays however DTMOS and SBB are only good for power supply voltages below threshold. If operation has to span the entire power supply voltage scale from 0V to VDD, it is better to use the TBB approach. The additional circuits required to provide the control voltages (Vcontroi) leads to a 9 % increase in power dissipation for a 32-bit linear feedback shift register and an area overhead of 4 %. In the following delay characteristics of different logic styles configured in the traditional manner are presented and the findings compared to the results of the same logic gates using the swapped body biasing scheme, dynamic threshold CMOS and tunable body biasing schemes.
4. NOISE MARGINS
A subject of importance as power supply voltages are scaled further into subthreshold is that of noise margins. At such small voltages it is possible that a slight change at the input might be misinterpreted by the circuit resulting in an incorrect output. The voltage levels that define the three regions of a digital circuit namely logic 0, the undefined region and logic 1 are examined. Simulations of an inverter under the three body biasing schemes
3.2 Logic Family Gate Delays Under the Various Biasing Schemes
Research on subthreshold circuit operation has focused on device
sizing, the ultra-low power gains and most importantly the best configuration (i.e. how to bias the bulk terminals for best results).
133
five and above is impractical since the RC delay of the series devices significantly increases the propagation delays. These results do not reveal anything new but the exercise remains valuable in that it eliminates the need for speculative evaluation regarding gate performance in subthreshold.
that have been studied with static CMOS used as a reference point once again are recorded. This exercise has been extended to examine a NAND gate's noise margins.
Figure 5 represents the inverter input signal and the corresponding outputs for both the traditional and TBB inverters. The stair step representation of the input allows for better observation of the circuit response to each defined voltage level (the stair). The circuit response to the input can be analyzed using a ramp as an input, but the start of the transition region becomes less distinct with such an input. The power supply voltage is at 376.2 mV and from Figure 5 it can be determined the regions at which the output voltage reaches steady state and the transition region is clear. It has been determined that the logic 0 is valid for an input range of 0-175 mV while a logic 1 is valid for the 200-376.2 mV range with the uncertain region occupying the 175-200 mV range. The nMOS' bulk terminal is at the ground terminal and that of the pMOS at VDD for these results. When the bulk terminals' connections are swapped (SBB or TBB) the ranges are as follows: logic 0 is defined in the range 0-200 mV, logic 1 is in the 225376.2 mV range and the uncertain region occupies the 200-225 mV range. Tunable body biasing has skewed noise margins due to the fact that the inverter is forward biased, causing it to identify a logic 1 more easily. The analysis has been performed only on the static CMOS logic style since it is a foregone conclusion that the pseudo-nMOS logic style degrades noise margins considerably. The static CMOS configuration definitely offers better noise margins. The swapped body biasing scheme gives improved propagation delays but has poor noise margins. The analysis shows that scaling to 90 nm and beyond would still guarantee proper logic levels with full signal swing.
1600
1400
t200 >, 1000 0
c 800
e 600 400 200
OTwo
~
~
~
~
~
!1
*.
,,, ,, .. I
6. CONCLUDING REMARKS
.s v
7. REFERENCES
TR^eD_ut
0we u (uv)
brne
I.2
w_,
Four
This paper has explored the relevance of different logic styles operating in the subthreshold region, concluding that static CMOS outperforms both Domino and pseudo-nMOS in all aspects (except area). The pass transistor logic style though better than static CMOS is limited by the heavy dependence of delays on the input pattems. It has been shown that a newly introduced TBB NAND gate improves propagation delays 6 times better than the standard biased CMOS NAND. Noise margins for devices operating in subthreshold have also been analyzed and the conclusion drawn is that even with scaling beyond 90 nm gate lengths valid logic levels are attainable. The TBB configured circuits have a smaller range of the undefined region and could thus be more sensitive to small fluctuations of the gate signals.
.
,
Three Number of Inputs
Figure 6. Effects of fan-in on propagation delay.
/'RAD o-a
~
-Traditional NAND -:-TBB NAND --- Traditional NOR -TOB NOR
[1] Soeleman, H., Roy, K. and Paul, B. C. "Robust Subthreshold Logic for Ultra-Low Power Operation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No 1, February 2001, pp. 90-99. [2] Kao, J., Narenda, S. and Chandrakasan, A., "Subthreshold Leakage Modeling and Reduction Techniques," IEEE/ACM International Conference on Computer Aided Design (ICCAD), November 10-14, 2002, pp.141-148. [3] S. Yang, W. Wolf, N. Vijaykrishnan, T. Xie and W. Wang, "Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100 nm Circuits," 18"' International Conference on VLSI Design, 2005, pp. 165-170. [4] C. Hyung-II Kim, H. Soeleman and K. Roy, "Ultra-LowPower DLMS Adaptive Filter for Hearing Aid Applications," IEEE Transactions on Very Large Scale Integration (VILSI) Systems, Vol. I1, No. 6, December 2003, pp. 1058-1067.
.5 .n
Figure 5. Traditional and TBB inverter input and output signals showing how noise margins are determined.
5. FAN-IN-FAN-OUT CONSIDERATIONS
At such low operating voltages it is highly likely that stacking devices could lead to erroneous results. It is thus instIuctive to evaluate circuit behavior under different fan-in conditions. All the gates analyzed in this study have a fan-out of four (FO4) achieved by having each gate drive four unit sized inverters. The simulation results displayed in Figure 6 are those of the NAND and NOR gates simulated in static CMOS. The swapped body biasing scheme is compared to the standard configuration as the fan-in increases while each gate maintains a constant fan-out (F04). The NOR gate has longer propagation delays owing to the series ptype devices. The swapped body biasing scheme allows for fast switching hence improved/shorter delays. Increasing the fan-in to
134
