Low Power Design for Wireless Sensor Networks - Semantic Scholar
Low Power Design for Wireless Sensor Networks Aki Happonen
Abstract—Wireless sensor networks have several challenges and one of those challenges is power efficiency. Almost in all cases in wireless sensor network’s nodes get their energy from batteries without having capability for charging. One design constraint is long operating time so efficient energy management in all levels play key role. This paper briefly introduces power management concept in different design levels – VLSI design techniques for low power designs, energy efficient protocols and energy efficient topologies.
Reference design for radio part is OKI’s ML7050LA [2] single chip RF having for example following blocks integrated: Low noise amplifier (LNA), power amplifier (PA), image rejection mixer (IMR). Block diagram of ML7050LA is in Figure 1. By assuming to use 3 V supply voltage Tx power dissipation is 102mW and Rx power dissipation is 165mW.
Index Terms—Low power, Wireless sensor network, VLSI, protocol, topology
I. INTRODUCTION Wireless sensor networks (WSN) have got researchers attention in resent years because those can be used in wide range of applications. Wireless Sensor Network could contain hundreds of sensors that collect and some cases preprocess data before it is send to central node for final processing. In the most cases sensors are deployed to remote location without capability to replace battery. This means that one of the key elements for distributed sensors is long lifetime covering both reliability and energy efficiency because the battery limits lifetime of the sensors. Energy efficiency should be taken account is all design phases starting from system design e.g. topology down to physical implementation constrains. In the literature has shown that energy efficiency can be improved in various areas when designing wireless sensor network e.g. VLSI design, protocols and network topology. This paper is collection from several papers related to chip implementation. Main focus is in digital design.
Figure 1.Oki’s ML7050LA single chip RF for Bluetooth. For the signal processing OKI’s single chip baseband ML70511LA [2] is used as a reference. Block diagram of ML70511LA is shown in Figure 2 having ARM7TDMI® processor and related peripherals. Figure 2 shows also interfaces to memories and RF modules. Estimated power dissipation for this device is 210mW in operation and 2.4uW in stand-by.
II. REFERENCE DESIGN AND ASSUMPTIONS In order to make some sense to proposed power efficient design methods we should have reference design. The reference design in this case is commercial Bluetooth chips. Unfortunately not so many power consumption figures are disclosed in public sources. Bluetooth was selected to be reference because it is close to sensor networks’ radios and lot of design exists in commercial and academic field. Also it gives reference point to requirements and makes comparison easier. The power consumption of Bluetooth chips is much higher than WSN chips but target of this paper is to introduce methods to save power by selecting right implementation. Figure 2. Oki’s ML70511LA block diagram. MAIN AUTHOR AFFILIATION INFORMATION GOES HERE.
III.
PHYSICAL IMPLEMENTATION
This section covers some implementation methods to get low power implementation to wireless sensors and it is divided two parts: data processing and transceiver. The data processing part covers mainly digital signal processing means and transceiver covers both receiver and transmitter. Sensors itself are left out from this paper and we can assume that sensors develop towards low power. As we can see from Figure 3 battery technology develops much slower than processing capacity i.e. Moore’s law. This keeps efficient power management urgent also in the future research.
same as supply voltage Vdd. In the second term Isc is short circuit current that arises when both NMOS and PMOS transistors are active at the same time, conduction current directly from supply to ground. In the third term Ileakage is leakage current. The first term dominates and if we assume that V is equal to Vdd then we can reduce power by decreasing supply voltage. In this paper we introduce asynchronous design techniques and dynamic voltage scaling to reduce energy. By combining those two we can select the optimum operating voltage and reach the lowest power consumption. 1) Asynchronous design This section introduces asynchronous design schemes. Whole section is based on [7] if otherwise mentioned. An additional power reduction method is asynchronous design without global clock. This leads metric of interest to be total energy of computation having following formula Penergy of computation = ½nCLV2dd
Figure 3. Battery capacity vs. processing power [1]. A. Digital design We can see from Figure 4 that Application Specific Integrated Circuit (ASIC) implementation is the most energy efficient solution but it does not provide as much flexibility as processor. By assuming that there is no need for flexibility after sensors deployment the ASIC implementation is preferred solution.
(2)
where n is total number of transitions in computation, CL is the load capacitance being (dis)charged, and Vdd is the power supply voltage. As seen from equation the energy depends on power of two of supply voltage the voltage scaling is attractive method for energy reduction. Asynchronous design can be split to two parts control signaling and data processing. In control signaling two blocks use hand shaking to request and acknowledge signals to control actual data processing. Data processing could be split to two schemes: single-rail and dual-rail. Both of those are introduced below. In single-rail design controller generates initial request signal and on that time data is ready in input latches. Request signal goes through delay that is matched to processing delay and it is also latching signal for output. Acknowledge is generated by delaying request signal by the time latching the output takes. Figure 5 shows block diagram of one data path stage implemented using single rail scheme.
MIPS, MOPS, Benchmarks / mW,
Energy Efficiency
ASIC Reconfigurable Logic DSP & ASIP Synthesizable RISC Flexibility
Figure 4. Energy-Flexibility Tradeoff [1] In CMOS there is three major power dissipation sources that can be summarizes by following equation [4]: Ptotal = pt(CL V Vdd fclk) + IscVdd +Ileakage Vdd
( 1)
In the first term CL is loading capacity, fclk is clock frequency and pt is the probability that a power consuming transition occurs. V is voltage swing and it is most cases
Figure 5. Block diagram of single-rail datapath stage. An advantage of single rail design is that synchronous designs’ blocks could be used so data paths have good area
constraints. A disadvantage is that design is less robust compared to for example dual-rail design scheme. In dual-rail design data is encoded using two wires for each bit. Codes “01” and “10” present “1” and “0” data values respectively and code “00” represents spacer or idle state. This is robust method that guarantees correct operation with arbitrary delays in the circuit or logic. A disadvantage of dual-rail logic is larger area due the two wires per bit encoding. In the operation read request signal is generated to input latches. After processing acknowledge signal is generated to indicate that output is latched. Figure 6 shows block diagram of one data path stage implemented using dual rail scheme. Figure 7. Program current consumption as a function of operating point [9]. System level software (SW) power management can be done for both active and idle modes. In active mode we can reduce 53% of system power by DVS [9]. By implementing that to reference design, OKIs baseband chip, power consumption decreases about 100mW. One important issue in power management is to minimize processing activity variation [10]. This is illustrated in Figure 8 where we can see that battery lifetime decreases as a function of increase in workload variance even if the average workload remains fixed. Figure 6. Block diagram of dual-rail datapath stage. Authors in [7] have concluded that dual rail scheme with voltage scaling and sequencer lowers power by factor 2.4 compared to only sequencer approach. In the sequencer approach computing is based on finite number of consecutive sequences having interprocess latency between sequences to lower the computation speed. An other method is so called concurrent protocol that allows to start next sequence even if the previous one is not completed it’s return-to-zero phase. That speeds up the processing time. Authors in [8] have shown benefits of asynchronous design to achieve low power circuits. Their study case was adder and they have concluded that asynchronous design can save energy from 14% to 24% compared to statistical carry look-ahead adder (SCLA). B. Dynamic voltage scaling (DVS) In dynamic voltage scaling operating voltage is scaled during the operation to fit required processing needs. In Figure 7 is illustrated current consumption as a function of voltage and clock frequency for StrongARM microprocessor. In this benchmark six different functions was used and we can see that current variation between relative low between programs so current consumption is not dependent of the code but depends only on operating voltage and clock frequency.
Figure 8.Degradation in DVS savings with increase in workload variance. In idle mode shutting down each of the components can totally save energy about 97% in system level combined with DVS [9]. In Figure 9 is shown power management hooks and their share. This information should be available for system engineers and application programmers to achieve energy efficient design.
Figure 9.System level power savings distribution. In paper [5] authors have shown up to 70% power saving using supply voltage scaling and allowing some degree of errors in signal processing phase. They have introduced proposed method to applications where algorithms perform a large number of computation steps per data sample. C. Radio design In WSN radio design power amplifier dominates total power budged if the transmission range is more than 10 meters [11]. After 10 meters required transmission power starts to increase exponentially. But short-range communication having gigahertz carrier frequency the radio the frequency synthesizer dominates power rather than the actual transmit power [12]. In packet based communication the start-up time of radios start to dominate in energy consumption because in high data rates and short packets the actual transmission time will be relative short: This effect is illustrated in Figure 10.
either by time division i.e. each sensor sniffs periodically if there is transmission or specific low power equipment that detects transmission starts. Issues in time division systems are related to clocks and their inaccuracy. To keep sensors low cost system clock generator will have jitter, frequency errors and roaming over the time. This roaming and frequency errors causes margins to receivers i.e. receiver must be on well before actual transmission starts. This extra time when receiver is on wastes energy. Other possibility is having special equipment to detect transmission and after signal is detected the receiver is put on. This is will cause more HW but on the other hand it will consume less energy than useless time when receiver is on. The lowest implementation to detect transmission is Microelectromechanical Systems (MEMS). MEMS will emerge to wireless sensor networks to further reduce size and power consumption. There is already some proposal how to utilize MEMS technology in WSN. In [13] authors have shown that using MEMS they can develop RF power detector without burning energy during the detection. IV.
Figure 10.Effects of start-up time on short packet transmission [12]. In literature improvements for Bluetooth radios have been listed in Table 1. We can see from that table that lot of improvements have happen in radio design by decreasing operating voltage down to 1V [23].
PROTOCOLS
This section discusses how to manage energy in protocol level and also it covers media access control (MAC) issues. The primary goal to develop protocols to wireless sensor networks is to keep it as simple as possible to maintain power consumption. In the wireless sensor networks MAC has two main functions. The first function is to map communication services to hardware available and the second is to minimize power consumption. In this section author’s focus is in the latter one. Inefficient MAC consumes over 90% of its energy to monitor channel. In low power MACs radios are set on either pre-scheduled times or asynchronous in need basis [11]. This reduction in duty cycle can be seen directly in battery lifetime as illustrated in Figure 11 and we can see that 10% duty cycle improves battery lifetime about 10 times.
Table 1. Bluetooth radios’ power consumption. Publication
Tx current consumption
Rx current consumption
Supply voltage
OKI’s reference Darabi et. al. [19] Chang et. al. [20] Byun et al. [21] Komurasaki et. al. [22] Ugajin et al. [23] Cojocaru et al. [24]
34mA 47mA 37mA 25mA 26mA 33mA 18mA
55mA 46mA 39mA 33mA 34mA 53mA 24mA
2.7-3.3V 2.7V 2.7V 3V 1.8V 1V 1.8V
In radio design improvements can be achieved if the focus is on energy efficiency rather than bandwidth efficiency [11]. The key focus in research will be power amplifier efficiency and frequency synthesizer. For the radios one key system level issue is to set radios on only when needed and challenge here is to detect right timing for example to receive data. This can be managed
Figure 11. Battery lifetime improvement in the sensor node compared to a node with no power management as a function of duty cycle and active workload [9].
V.
DISCUSSION AND SUMMARY
In this paper design implications to power dissipation in sensor networks is presented. In digital signal processing there exists design techniques that reduces power consumption. The most attractive technology is dynamic voltage scaling that reduces power consumption noticeably but at the same time processing performance in terms of clock speed decreases. To compensate reduced operating voltage methods to adopt variable processing time is presented: asynchronous design with single- and dual-rail techniques. This can be applied in WSN by scaling voltage as low as possible to get lowest processing speed that fulfills system requirements. Also we should keep workload’s variation as small as possible. In digital design energy per operation scales with technology but communication energy per transmitted bit does not scale at the same rate. Se we can set general rule from implementation point of view is: Compute do not communicate. In the end implementation selections will be minor issue if the system level constraints are wrong. In the system level decision and MAC level optimization leads longer lifetime than implementation optimization. That is illustrated in Figure 11 by as a function of duty cycle.
[13]
[14]
[15]
[16]
[17]
[18]
[19]
VI. REFERENCES [1]
http://bwrc.eecs.berkeley.edu/People/Faculty/jan/presentations/hot chips1.pdf (May 2004) [2] http://www.oki.com/semi/english/t-blue.htm [3] Rabaey J. M., “Low-Power Silicon Architectures for Wireless Communications”, Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific, 25-28 Jan. 2000, Page(s): 377 –380 [4] Chandrakasan, A.P.; Sheng, S.; Brodersen, R.W.;”Low-power CMOS digital design”, Solid-State Circuits, IEEE Journal of , Volume: 27 , Issue: 4 , April 1992, Pages:473 – 484 [5] Kuang, W.; Yuan, J.S.; Ejnioui, A.;” Supply voltage scalable system design using self-timed circuits”, VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on , 20-21 Feb. 2003, Pages:161 - 166 [6] Salhieh, A.; Weinmann, J.; Kochha, M.; Schwiebert, L.;” Power efficient topologies for wireless sensor networks”, Parallel Processing, International Conference on, 2001. , Sep. 3-7, 2001, Pages:156 – 163 [7] Plana, L.A.; Nowick, S.M.;”Architectural optimization for lowpower nonpipelined asynchronous systems”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 6 , Issue: 1 , March 1998, Pages:56 - 65 [8] Perri, S.; Corsonello, P.; Cocorullo, G.; “VLSI circuits for lowpower high-speed asynchronous addition”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 10 , Issue: 5 , Oct. 2002, Pages:608 – 613 [9] Sinha, A.; Ickes, N.; Chandrakasan, A.P.; ”Instruction level and operating system profiling for energy exposed software”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 11 , Issue: 6 , Dec. 2003, Pages:1044 – 1057 [10] Sinha, A.; Chandrakasan, A.P.; “Dynamic voltage scheduling using adaptive filtering of workload traces”, VLSI Design, 2001. Fourteenth International Conference on , 3-7 Jan. 2001, Pages:221 226 [11] Rabaey, J.M.; Ammer, J.; Karalar, T.; Suetfei Li; Otis, B.; Sheets, M.; Tuan, T.;”PicoRadios for wireless sensor networks: the next challenge in ultra-low power design”, Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International , Volume: 1 , 3-7 Feb. 2002, Pages:200 - 201 vol.1 [12] Min, R.; Bhardwaj, M.; Seong-Hwan Cho; Shih, E.; Sinha, A.; Wang, A.; Chandrakasan, A.; “Low-power wireless sensor
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networks”, VLSI Design, 2001. Fourteenth International Conference on , 3-7 Jan. 2001, Pages:205 - 210 Fernandez, L.J.; Visser, E.; Sese, J.; Wiegerink, R.; Flokstra, J.; Jansen, H.; Elwenspoek, M.; “Radio frequency power sensor based on MEMS technology”, Sensors, 2003. Proceedings of IEEE , Volume: 1 , Oct. 22-24, 2003, Pages:549 – 552 Heinzelman, W.B.; Chandrakasan, A.P.; Balakrishnan, H.;” An application-specific protocol architecture for wireless microsensor networks”, Wireless Communications, IEEE Transactions on , Volume: 1 , Issue: 4 , Oct. 2002, Pages:660 – 670 El-Hoiydi, A.; "Spatial TDMA and CSMA with preamble sampling for low power ad hoc wireless sensor networks”,Computers and Communications, 2002. Proceedings. ISCC 2002. Seventh International Symposium on , 1-4 July 2002, Pages:685 – 692 Guangyu Pei; Chien, C.; "Low power TDMA in large wireless sensor networks”, Military Communications Conference, 2001. MILCOM 2001. Communications for Network-Centric Operations: Creating the Information Force. IEEE , Volume: 1 , 28-31 Oct. 2001, Pages:347 - 351 vol.1 Kubisch, M.; Karl, H.; Wolisz, A.; Zhong, L.C.; Rabaey, J.; “Distributed algorithms for transmission power control in wireless sensor networks”, Wireless Communications and Networking, 2003. WCNC 2003. 2003 IEEE , Volume: 1 , 16-20 March 2003, Pages:558 - 563 vol.1 Girling, G.; Wa, J.L.K.; Osborn, P.; Stefanova, R.; “The design and implementation of a low power ad hoc protocol stack”,Wireless Communications and Networking Conference, 2000. WCNC. 2000 IEEE , Volume: 3 , 23-28 Sept. 2000, Pages:1521 - 1529 vol.3 Darabi, H.; Khorram, S.; Hung-Ming Chien; Meng-An Pan; Wu, S.; Moloudi, S.; Leete, J.C.; Rael, J.J.; Syed, M.; Lee, R.; Ibrahim, B.; Rofougaran, M.; Rofougaran, A.; ”A 2.4-GHz CMOS transceiver for Bluetooth”, Solid-State Circuits, IEEE Journal of , Volume: 36 , Issue: 12 , Dec. 2001, Pages:2016 – 2024 Chang, G.; Jansson, L.; Wang, K.; Grilo, J.; Montemayor, R.; Hull, C.; Lane, M.; Estrada, A.X.; Anderson, M.; Galton, I.; Kishore, S.V.;”A direct-conversion single-chip radio-modem for Bluetooth”, Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International , Volume: 1 , 3-7 Feb. 2002 , Pages:88 - 448 vol.1 Sangjin Byun; Chan-Hong Park; Yongchul Song; Sungho Wang; Conroy, C.S.G.; Beomsup Kim; “A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator”, Solid-State Circuits, IEEE Journal of , Volume: 38 , Issue: 10 , Oct. 2003, Pages:1609 – 1618 Komurasaki, H.; Heima, T.; Miwa, T.; Yamamoto, K.; Wakada, H.; Yasui, I.; Ono, M.; Sano, T.; Sato, H.; Miki, T.; Kato, N.;”A 1.8V operation RFCMOS transceiver for Bluetooth”, VLSI Circuits Digest of Technical Papers, 2002. Symposium on , 13-15 June 2002, Pages:230 – 233 Ugajin, M.; Yamagishi, A.; Kodate, J.; Harada, M.; Tsukahara, T.;”A 1-V CMOS/SOI bluetooth RF transceiver for compact mobile applications”, VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on , 12-14 June 2003, Pages:123 – 126 Cojocaru, C.; Pamir, T.; Balteanu, F.; Namdar, A.; Payer, D.; Gheorghe, I.; Lipan, T.; Sheikh, K.; Pingot, J.; Paananen, H.; Littow, M.; Cloutier, M.; MacRobbie, E.;”A 43mW Bluetooth transceiver with -91dBm sensitivity”, Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International , 2003, Pages:90 - 480 vol.1
Abstract—Wireless sensor networks have several challenges and one of those challenges is power efficiency. Almost in all cases in wireless sensor network’s nodes get their energy from batteries without having capability for charging. One design constraint is long operating time so efficient energy management in all levels play key role. This paper briefly introduces power management concept in different design levels – VLSI design techniques for low power designs, energy efficient protocols and energy efficient topologies.
Reference design for radio part is OKI’s ML7050LA [2] single chip RF having for example following blocks integrated: Low noise amplifier (LNA), power amplifier (PA), image rejection mixer (IMR). Block diagram of ML7050LA is in Figure 1. By assuming to use 3 V supply voltage Tx power dissipation is 102mW and Rx power dissipation is 165mW.
Index Terms—Low power, Wireless sensor network, VLSI, protocol, topology
I. INTRODUCTION Wireless sensor networks (WSN) have got researchers attention in resent years because those can be used in wide range of applications. Wireless Sensor Network could contain hundreds of sensors that collect and some cases preprocess data before it is send to central node for final processing. In the most cases sensors are deployed to remote location without capability to replace battery. This means that one of the key elements for distributed sensors is long lifetime covering both reliability and energy efficiency because the battery limits lifetime of the sensors. Energy efficiency should be taken account is all design phases starting from system design e.g. topology down to physical implementation constrains. In the literature has shown that energy efficiency can be improved in various areas when designing wireless sensor network e.g. VLSI design, protocols and network topology. This paper is collection from several papers related to chip implementation. Main focus is in digital design.
Figure 1.Oki’s ML7050LA single chip RF for Bluetooth. For the signal processing OKI’s single chip baseband ML70511LA [2] is used as a reference. Block diagram of ML70511LA is shown in Figure 2 having ARM7TDMI® processor and related peripherals. Figure 2 shows also interfaces to memories and RF modules. Estimated power dissipation for this device is 210mW in operation and 2.4uW in stand-by.
II. REFERENCE DESIGN AND ASSUMPTIONS In order to make some sense to proposed power efficient design methods we should have reference design. The reference design in this case is commercial Bluetooth chips. Unfortunately not so many power consumption figures are disclosed in public sources. Bluetooth was selected to be reference because it is close to sensor networks’ radios and lot of design exists in commercial and academic field. Also it gives reference point to requirements and makes comparison easier. The power consumption of Bluetooth chips is much higher than WSN chips but target of this paper is to introduce methods to save power by selecting right implementation. Figure 2. Oki’s ML70511LA block diagram. MAIN AUTHOR AFFILIATION INFORMATION GOES HERE.
III.
PHYSICAL IMPLEMENTATION
This section covers some implementation methods to get low power implementation to wireless sensors and it is divided two parts: data processing and transceiver. The data processing part covers mainly digital signal processing means and transceiver covers both receiver and transmitter. Sensors itself are left out from this paper and we can assume that sensors develop towards low power. As we can see from Figure 3 battery technology develops much slower than processing capacity i.e. Moore’s law. This keeps efficient power management urgent also in the future research.
same as supply voltage Vdd. In the second term Isc is short circuit current that arises when both NMOS and PMOS transistors are active at the same time, conduction current directly from supply to ground. In the third term Ileakage is leakage current. The first term dominates and if we assume that V is equal to Vdd then we can reduce power by decreasing supply voltage. In this paper we introduce asynchronous design techniques and dynamic voltage scaling to reduce energy. By combining those two we can select the optimum operating voltage and reach the lowest power consumption. 1) Asynchronous design This section introduces asynchronous design schemes. Whole section is based on [7] if otherwise mentioned. An additional power reduction method is asynchronous design without global clock. This leads metric of interest to be total energy of computation having following formula Penergy of computation = ½nCLV2dd
Figure 3. Battery capacity vs. processing power [1]. A. Digital design We can see from Figure 4 that Application Specific Integrated Circuit (ASIC) implementation is the most energy efficient solution but it does not provide as much flexibility as processor. By assuming that there is no need for flexibility after sensors deployment the ASIC implementation is preferred solution.
(2)
where n is total number of transitions in computation, CL is the load capacitance being (dis)charged, and Vdd is the power supply voltage. As seen from equation the energy depends on power of two of supply voltage the voltage scaling is attractive method for energy reduction. Asynchronous design can be split to two parts control signaling and data processing. In control signaling two blocks use hand shaking to request and acknowledge signals to control actual data processing. Data processing could be split to two schemes: single-rail and dual-rail. Both of those are introduced below. In single-rail design controller generates initial request signal and on that time data is ready in input latches. Request signal goes through delay that is matched to processing delay and it is also latching signal for output. Acknowledge is generated by delaying request signal by the time latching the output takes. Figure 5 shows block diagram of one data path stage implemented using single rail scheme.
MIPS, MOPS, Benchmarks / mW,
Energy Efficiency
ASIC Reconfigurable Logic DSP & ASIP Synthesizable RISC Flexibility
Figure 4. Energy-Flexibility Tradeoff [1] In CMOS there is three major power dissipation sources that can be summarizes by following equation [4]: Ptotal = pt(CL V Vdd fclk) + IscVdd +Ileakage Vdd
( 1)
In the first term CL is loading capacity, fclk is clock frequency and pt is the probability that a power consuming transition occurs. V is voltage swing and it is most cases
Figure 5. Block diagram of single-rail datapath stage. An advantage of single rail design is that synchronous designs’ blocks could be used so data paths have good area
constraints. A disadvantage is that design is less robust compared to for example dual-rail design scheme. In dual-rail design data is encoded using two wires for each bit. Codes “01” and “10” present “1” and “0” data values respectively and code “00” represents spacer or idle state. This is robust method that guarantees correct operation with arbitrary delays in the circuit or logic. A disadvantage of dual-rail logic is larger area due the two wires per bit encoding. In the operation read request signal is generated to input latches. After processing acknowledge signal is generated to indicate that output is latched. Figure 6 shows block diagram of one data path stage implemented using dual rail scheme. Figure 7. Program current consumption as a function of operating point [9]. System level software (SW) power management can be done for both active and idle modes. In active mode we can reduce 53% of system power by DVS [9]. By implementing that to reference design, OKIs baseband chip, power consumption decreases about 100mW. One important issue in power management is to minimize processing activity variation [10]. This is illustrated in Figure 8 where we can see that battery lifetime decreases as a function of increase in workload variance even if the average workload remains fixed. Figure 6. Block diagram of dual-rail datapath stage. Authors in [7] have concluded that dual rail scheme with voltage scaling and sequencer lowers power by factor 2.4 compared to only sequencer approach. In the sequencer approach computing is based on finite number of consecutive sequences having interprocess latency between sequences to lower the computation speed. An other method is so called concurrent protocol that allows to start next sequence even if the previous one is not completed it’s return-to-zero phase. That speeds up the processing time. Authors in [8] have shown benefits of asynchronous design to achieve low power circuits. Their study case was adder and they have concluded that asynchronous design can save energy from 14% to 24% compared to statistical carry look-ahead adder (SCLA). B. Dynamic voltage scaling (DVS) In dynamic voltage scaling operating voltage is scaled during the operation to fit required processing needs. In Figure 7 is illustrated current consumption as a function of voltage and clock frequency for StrongARM microprocessor. In this benchmark six different functions was used and we can see that current variation between relative low between programs so current consumption is not dependent of the code but depends only on operating voltage and clock frequency.
Figure 8.Degradation in DVS savings with increase in workload variance. In idle mode shutting down each of the components can totally save energy about 97% in system level combined with DVS [9]. In Figure 9 is shown power management hooks and their share. This information should be available for system engineers and application programmers to achieve energy efficient design.
Figure 9.System level power savings distribution. In paper [5] authors have shown up to 70% power saving using supply voltage scaling and allowing some degree of errors in signal processing phase. They have introduced proposed method to applications where algorithms perform a large number of computation steps per data sample. C. Radio design In WSN radio design power amplifier dominates total power budged if the transmission range is more than 10 meters [11]. After 10 meters required transmission power starts to increase exponentially. But short-range communication having gigahertz carrier frequency the radio the frequency synthesizer dominates power rather than the actual transmit power [12]. In packet based communication the start-up time of radios start to dominate in energy consumption because in high data rates and short packets the actual transmission time will be relative short: This effect is illustrated in Figure 10.
either by time division i.e. each sensor sniffs periodically if there is transmission or specific low power equipment that detects transmission starts. Issues in time division systems are related to clocks and their inaccuracy. To keep sensors low cost system clock generator will have jitter, frequency errors and roaming over the time. This roaming and frequency errors causes margins to receivers i.e. receiver must be on well before actual transmission starts. This extra time when receiver is on wastes energy. Other possibility is having special equipment to detect transmission and after signal is detected the receiver is put on. This is will cause more HW but on the other hand it will consume less energy than useless time when receiver is on. The lowest implementation to detect transmission is Microelectromechanical Systems (MEMS). MEMS will emerge to wireless sensor networks to further reduce size and power consumption. There is already some proposal how to utilize MEMS technology in WSN. In [13] authors have shown that using MEMS they can develop RF power detector without burning energy during the detection. IV.
Figure 10.Effects of start-up time on short packet transmission [12]. In literature improvements for Bluetooth radios have been listed in Table 1. We can see from that table that lot of improvements have happen in radio design by decreasing operating voltage down to 1V [23].
PROTOCOLS
This section discusses how to manage energy in protocol level and also it covers media access control (MAC) issues. The primary goal to develop protocols to wireless sensor networks is to keep it as simple as possible to maintain power consumption. In the wireless sensor networks MAC has two main functions. The first function is to map communication services to hardware available and the second is to minimize power consumption. In this section author’s focus is in the latter one. Inefficient MAC consumes over 90% of its energy to monitor channel. In low power MACs radios are set on either pre-scheduled times or asynchronous in need basis [11]. This reduction in duty cycle can be seen directly in battery lifetime as illustrated in Figure 11 and we can see that 10% duty cycle improves battery lifetime about 10 times.
Table 1. Bluetooth radios’ power consumption. Publication
Tx current consumption
Rx current consumption
Supply voltage
OKI’s reference Darabi et. al. [19] Chang et. al. [20] Byun et al. [21] Komurasaki et. al. [22] Ugajin et al. [23] Cojocaru et al. [24]
34mA 47mA 37mA 25mA 26mA 33mA 18mA
55mA 46mA 39mA 33mA 34mA 53mA 24mA
2.7-3.3V 2.7V 2.7V 3V 1.8V 1V 1.8V
In radio design improvements can be achieved if the focus is on energy efficiency rather than bandwidth efficiency [11]. The key focus in research will be power amplifier efficiency and frequency synthesizer. For the radios one key system level issue is to set radios on only when needed and challenge here is to detect right timing for example to receive data. This can be managed
Figure 11. Battery lifetime improvement in the sensor node compared to a node with no power management as a function of duty cycle and active workload [9].
V.
DISCUSSION AND SUMMARY
In this paper design implications to power dissipation in sensor networks is presented. In digital signal processing there exists design techniques that reduces power consumption. The most attractive technology is dynamic voltage scaling that reduces power consumption noticeably but at the same time processing performance in terms of clock speed decreases. To compensate reduced operating voltage methods to adopt variable processing time is presented: asynchronous design with single- and dual-rail techniques. This can be applied in WSN by scaling voltage as low as possible to get lowest processing speed that fulfills system requirements. Also we should keep workload’s variation as small as possible. In digital design energy per operation scales with technology but communication energy per transmitted bit does not scale at the same rate. Se we can set general rule from implementation point of view is: Compute do not communicate. In the end implementation selections will be minor issue if the system level constraints are wrong. In the system level decision and MAC level optimization leads longer lifetime than implementation optimization. That is illustrated in Figure 11 by as a function of duty cycle.
[13]
[14]
[15]
[16]
[17]
[18]
[19]
VI. REFERENCES [1]
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