Low Power Programmable-Gain CMOS Distributed LNA for Ultra ...
6-1
Low Power Programmable-Gain CMOS Distributed LNA for Ultra-Wideband Applications Frank Zhang and Peter Kinget Columbia Integrated Systems Lab Columbia University, New York, NY 10027 U.S.A. Abstract A design methodology is presented for low power distributed amplifiers and is used for the design of a mW LNA with programmable gain implemented in a m CMOS dB from DC process. The LNA provides a gain of GHz, with an input match of dB and an output to match of dB over the entire band. The IIP3 is dBm, to dB. The gain is tunable and the NF ranges from from dB to dB while gain flatness and matching are maintained.
Rd_set M8 (40/0.5) Vdd
(1.2 nH)
Rd (70 ohm) Vcascode (Gain Control)
A
Distributed Amplifier Tradeoffs Design techniques for DAs have been discussed in numerous publications [5]–[7]. At low frequencies, the gain, G of a DA is given by (1) in Fig. 1, where N is the number of stages, e.g., is the transconductance of a single stage, and R is the characteristic impedance of the line, usually 50 . At high frequencies, the expression for gain is more complicated due to its traveling-wave-like nature, but is still directly and . Pseudo-transmission lines are proportional to formed by integrating the intrinsic gate and drain capacitances, , and , of the transistors with inductors and , respectively. The bandwidth of the DA is limited by
78
4-900784-01-X
Ld (3.3 nH)
M2 (320/0.18)
M4 (320/0.18)
M6 (320/0.18)
M3 (320/0.18)
M5 (320/0.18)
Lg (2.3 nH)
(1 nH) M7 (40/0.5) Rg_set
Output
Ibias (580uA)
Rg (70 ohm)
Input
(1 nH)
Fig. 1.
(1.2 nH)
I M1 (320/0.18)
Introduction A broadband low-noise amplifier (LNA) is a critical component of the ultra-wideband (UWB) receiver [1] and cognitive radio [2]. Recent publications have reported ways to obtain flat gain for UWB through modified narrowband techniques [3] and resistive feedback [4]. This paper investigates the use of distributed amplification in the context of UWB applications and introduces a design methodology geared towards low power operation. The main advantages of a distributed amplifier (DA) are its intrinsic broadband characteristic that goes all the way down to DC, and good input and output matching. But, high power consumption and large area have limited its application space. However, when one considers the trade-off between the five main design parameters of an LNA: power drain, gain, bandwidth, noise, and linearity, it becomes evident that the traditional way of biasing a MOS DA in strong inversion, is not the optimal choice for reducing power consumption. This paper describes the design of a low-power 3-stage distributed MOS DA biased in moderate inversion (M.I.).
Ld (3.3 nH)
Lg (2.3 nH)
M9 (80/0.18)
Schematic of the 3-stage distributed amplifi er.
the cutoff frequency, , of the gate and drain lines because matching degrades as the cutoff frequency is approached. As a rule of thumb, matching better than dB cannot be achieved for frequencies above of [8]. For the gate line we obtain: (2) To achieve impedance matching, the lines are terminated in their characteristic impedance , i.e. . The is the only cutoff frequency can then be rewritten so that variable. Eq. (2) shows that to obtain a given bandwidth for a given there is an upper limit on the size of the capacitance . The figure of merit (FOM) used in most DA designs and literature is the gain bandwidth product (GBW) GBW
(3)
where is the unity gain frequency of the transistor. The important observation from (3) is that the upper bound of GBW is proportional to and . cannot be made too large since it is limited by the attenuation caused by the losses in the on-chip inductors as well as area constraints. For the technology used in this design, a 3-stage amplifier resulted in is process and bias dependent. The the best compromise. tradeoffs between inversion coefficient (IC) and have been analyzed extensively in e.g., [9]. In order to achieve high for a given technology, the devices need to be biased at a high IC, i.e. in strong inversion, and this is indeed what has been done in most DA designs. However, the usefulness of GBW as the FOM for LNA design depends on the application. As mentioned earlier, noise, linearity, and current budget are all critical, but are not reflected in GBW. Therefore, using the 2005 Symposium on VLSI Circuits Digest of Technical Papers
TABLE I LNA Tradeoffs for Fixed Power Consumption
following unit-less FOM is more appropriate for gauging the total performance of LNAs for UWB applications: FOM
W/L
(4)
where IIP3 is the input-referred third-order intercept point, is the noise factor, and is the total power consumption of the DA. We now investigate the dependence of this FOM on the DA design parameters. The expression for gain in (1) is valid for MOS transistors biased in weak inversion (W.I.) as well as in strong inversion (S.I.). To the first-order, the IIP3 of a MOS transistor [10] is (5) where n is the subthreshold slope, a unit-less technology is . In the S.I. formula, is the constant, and second-order effect of mobility degradation and has the unit of [ ] [10]. From (5), it is evident that IIP3 is constant in W.I., and is directly proportional to the overdrive in S.I.. The IIP3 of the DA tracks the IIP3 of a single MOS transistor if we assume the worst-case scenario of constructive summation of distortion components. The noise characteristic of MESFET DAs has been analyzed extensively in [11] and the results are applicable to MOSFET DAs as well. The simplified expression for F is (6) where is a noise modeling constant equal to approximately in W.I. and in S.I. The important observation is . Eqn. (6) is a that noise is inversely proportional to simplified view of DA noise since only the drain current noise is included and therefore is only valid at low frequencies. The is gate-induced noise, which is directly proportional to important and is considered in the next section. The total power consumption of the DA is equal to (7) where I is the current through one stage and is is the supply voltage. the total current budget for the DA; Substituting the results from (1), (5) (7) into (4), the FOM of the DA in W.I. and S.I. is (8) and where the substitutions are used for W.I. and S.I., respectively. Table I also illustrates the tradeoffs in W.I. and S.I., assuming fixed power consumption. of the DA the FOM in For a fixed current budget S.I. is improved by increasing the , which corresponds to reducing the overdrive and inversion coefficient and increasing ; this moves the bias point towards W.I. operation. the Once the devices operate in W.I. the FOM can no longer be improved. So, to obtain a good trade-off between the different
Operation
Gain
IIP3
NF
BW
Toward W.I. Toward S.I. Desired
DA performance parameters we need to bias the transistors as close to W.I. as possible. This is also evident from the first row in Table I. However, operation towards W.I. requires a large which implies a lower and thus larger for a given . The desired set of amplifier specifications for gain, noise, distortion, and most importantly, bandwidth, in combination with the technology performance will determine how close this optimized biasing can be achieved. Due to bandwidth limitation, the 3-stage DA described in this work is biased in moderate inversion (i.e. between W.I. and S.I.). A closed form expression for the FOM in M.I. is difficult to obtain due to the partial drift, partial diffusion behavior of the device in that region. The gain and NF characteristic of the DA moving from W.I. to S.I. is monotonic, whereas the IIP3 improves somewhat in the M.I. region [10]. Design Methodology The proposed design procedure for the 3-stage DA is as follows: First, the cutoff frequency of the gate line is calcuGHz. lated from the required bandwidth of GHz: Secondly, the maximum gate capacitance is calculated from fF. Next, using the minimum length, the (2): maximum width of the transistor is determined for the worstcase process corner: m. The width of the transistors are then selected based on the constraint set by the cascode node and the gate-induced noise, both discussed later in this section. Finally, the inductor values are determined , and the selected R, which is for both the from , gate and drain lines. a) Gate-Induced Noise: The frequency at which the gate , noise becomes comparable to the drain current noise, is critical [11]. Equating the gate-induced noise with drain current noise gives (9) is a constant equal to approximately in S.I.. must be designed to be higher than the cutoff frequency where noise starts to increase anyway due to gain rolloff. This restriction forces the width of M1 to be less than the maximum allowed by the cutoff frequency. A width of m was used for M1 based on the value calculated from Eqn. (9). b) Cascode: A cascode structure is necessary for this design because of stability concerns and the effect of Miller capacitance. The cascode transistor improves reverse isolation and at the same time minimizes C ’s effect on bandwidth. However, the side effect of using large width transistors and low bias current is that the cascode node, labeled ”A” in Fig. 1, can now limit the frequency response of the circuit. At node A, “competes” with , , and . and are junction capacitances that have become where
2005 Symposium on VLSI Circuits Digest of Technical Papers
79
(10) is the unity-gain frequency of M2. For fixed where current, increases with decreasing W2, is increases with decreasing W2. The constant, and competing requirement for W2 in the numerator and denominator of (10) implies that an optimal width for M2 exists. From simulation, the optimal value for W2 was found to be slightly less than W1; the value was close enough to W1 so m was also used for W2. that for layout reasons, c) Adjustable Termination Resistors: The frequency response of the DA is less sensitive to process variation compared to modified narrowband techniques. A variation in capacitance1 of the transmission lines results in a different , but the change in characteristic impedance, and as a result of this variation is small. For UWB applications, gain flatness down to DC is not necessary, but for applications such as cognitive radio, it is a requirement. To achieve gain flatness below GHz the termination resistors , and to account for the worst case where need to track ( ) and ( ) skew in the same direction, adjustable termination resistors shown in Fig. 1 are used; M7 and M8 devices biased in triode region. The parallel are zeropolysilicon resistor combination of M7(M8) with a provides the flexibility to adjust the termination resistance to achieve flat gain below GHz. d) Programmable Gain: A distributed amplifier has the important property that gain and broadband matching can be dealt with separately. When the cascode voltage, , is reduced, M1 moves from operation in saturation towards reduces and the gain of the amplifier can be triode. The varied. At the same time, for a substantial range in the variation in the total gate capacitance remains small and therefore good impedance matching is maintained.
10 9 8 7
S
21
[dB]
6 5 4 3 2
Measured S
1
Simulated S21
0 0
1
Fig. 2.
21
8
7
6
5 4 3 Frequency [GHz]
2
Simulated (slow-slow corner) and measured
.
0 −5 −10 S11 , S22 [dB]
significant due to the large transistors used to obtain the high -efficiency, i.e., large . Some processes offer deep-nwell nFETs with a local substrate connection, which eliminates . However, now the capacitance associated with the large deep-nwell required to contain the large transistor shunts away the signal at the cascode node at high frequencies. Another concern is that the doping inside the deep-nwell is higher than the bulk which results in higher capacitance values. Therefore we use regular bulk nFET devices in our amplifier. The width of M2 needs to be optimized to achieve the desired frequency response. The pole at node A, , is:
−15 −20 −25
Measured S11
−30
Simulated S11 Measured S22
−35
Simulated S22
−40 0
Fig. 3.
4
2
6 Frequency [GHz]
12
10
8
Simulated (slow-slow corner) and measured
and
.
The chip occupies including pads; the die photograph is shown in Fig. 6. The stages of the DA were laid out as close as possible and EM simulations where performed on the amplifier to verify that the coupling between the stages is sufficiently small. The DA consumes mA from a V supply. V is the ”true” supply voltage since no external RF choke or biasT is used. This is because the voltage drop across the drain termination resistor is small due to low current consumption. Ten amplifier samples were characterized on an RF probe station. The S-parameter data was measured using the Anritsu 37369C 40 GHz network analyzer; the data for different samples was very consistent and the results for a typical sample are shown in Fig. 2 and 3. A good input and output impedance dB are obtained between match and a flat gain of MHz and GHz. The reverse isolation, , is less than dB. The noise figure was measured using the HP8970 11 Measured NF
10
Simulated NF
9
Measurement and Results
1 Inductance
cess.
80
depends on layout geometry therefore varies little with pro-
4-900784-01-X
NF [dB]
A 3-stage DA for UWB was designed in a m CMOS process with a - m thick top metal. The custom inductor designs with polysilicon patterned ground shields were optimized using an electromagnetic simulation tool (EMX). Simulations and characterization of a inductor test structure show a quality factor of about .
8 7 6 5 4 3
Fig. 4.
1
2
3
5 4 Frequency [GHz]
6
7
Simulated (slow-slow corner) and measured noise fi gure.
2005 Symposium on VLSI Circuits Digest of Technical Papers
TABLE II LNA Performance Comparison CMOS [ m]
Flat-Gain BW [GHz]
3-dB BW [GHz]
S21 [dB]
G [dB]
S11 [dB]
Spot NF [dB] -
NF [dB]
IIP3 [dBm]
ICP [dBm]
+
-
+
-
This Work
0.18
-
[12]
0.18
-
[6]
0.6
-
[4]
0.13
[3]
0.18
-
-
-
[3]
0.18
-
-
-
-
Area [mm ]
-
mW buffer stage for output match 10 5 0 −5
−30 −35 0
22
, S
−25
0 −10 −20
11
−20
[dB]
−10 −15
S
Noise Figure meter, and is shown in Fig. 4. As expected, noise is large at low frequencies and increases after the cutoff frequency [11]. Fig. 5 demonstrates the programmable gain feature; gain is varied from dB to dB while input and output matching, and gain flatness are maintained. The linearity of the amplifier was verified with two-tone IIP3 and dB gain compression (ICP) measurements which are reported in Table II. The performance of the presented amplifier is compared with other ultra-wideband LNAs in Table II. The performance of the presented design is at par or exceeds the performance of other LNAs for UWB applications [3], [4]. The power consumption of the presented amplifier is also significantly lower than previously published DAs [6], [12] which demonstrates that the presented design methodology is effective for low power DA design.
S21 [dB]
Measured @ 2 GHz *
P [mW]
−30 0
2
8 6 4 Freqency [GHz]
2
4
10
12
6 Freqency [GHz]
Fig. 5. Measured gain for different input and output matching for different
8
10
12
voltages. Inset: Measured voltages.
Conclusion A low power MOS DA design has been demonstrated. Improvement in overall DA performance is obtained by biasing the transistors towards the weak inversion region. While this approach limits the attainable bandwidth, as the of scaled MOS transistors increases, this design approach will become even more attractive. Thanks to the operation from DC to RF, combined with the programmable gain feature, this DA design can be used in various broadband applications including UWB and cognitive radio. Acknowledgment
Fig. 6.
The authors would like to thank R. Yan of Realtek for chip fabrication; S. Kapur and D. Long of Integrand Software for the use of EMX simulation tool; Y. Baeyens of Bell Labs, Lucent Technologies for help with NF measurement; R. Gharpurey of University of Michigan for technical discussions; and Anritsu for the use of 37369C network analyzer. Frank Zhang is supported through an NSF GK-12 fellowship. References [1] S. Stroh, “Ultra-wideband: Multimedia unplugged,” IEEE Spectrum, vol. 40, pp. 23–27, Sept. 2003. [2] P. Mannion, “Sharing spectrum the smarter way,” EE Times, April 05, 2004. [3] A. Bevilacqua and A. Niknejad, “An ultrawideband CMOS low-noise amplifi er for 3.1-10.6GHz wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004. [4] R. Gharpurey, “A broadband low-noise front-end amplifi er for ultra wideband in 0.13um CMOS,” in Proc. IEEE Custom Integrated Circuits Conference, Oct. 3–6, 2004, pp. 605–608.
Die photograph.
[5] T. T. Y. Wong, Fundamentals of Distributed Amplification. Norwood, MA: Artech House, Inc., 1993. [6] B. M. Ballweber, R. Gupta, and D. J. Allstot, “A fully integrated 0.5-5.5GHz CMOS distributed amplifi er,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 231–239, Feb. 2000. [7] J. B. Beyer, S. N. Prasad, R. C. Becker, J. E. Nordman, and G. K. Hohenwarter, “MESFET distributed amplifer design guidelines,” IEEE Trans. Microwave Theory Tech., vol. 32, no. 3, pp. 268–275, Mar. 1984. [8] P. H. Ladbrooke, MMIC Design: GaAs FETs and HEMTs. Norwood, MA: Artech House, Inc., 1989. [9] D. M. Binkley, C. E. Hopper, S. D. Tucker, B. C. Moss, J. M. Rochelle, and D. P. Foty, “A CAD methodology for optimizing transistor current and sizing in analog CMOS design,” IEEE J. Technol. Computer Aided Design, vol. 22, no. 2, pp. 225–237, Feb. 2003. [10] B. Toole, C. Plett, and M. Cloutier, “RF circuit implications of moderate inversion enhanced linear region in MOSFETs,” IEEE Trans. Circuits Syst. I, vol. 51, no. 2, pp. 319–328, Feb. 2004. [11] C. Aitchison, “The intrinsic noise fi gure of the MESFET distributed amplifi er,” IEEE Trans. Microwave Theory Tech., vol. 33, no. 6, pp. 460–466, June 1985. [12] R.-C. Liu, C.-S. Lin, K.-L. Deng, and H. Wang, “A 0.5-14-GHz 10.6dB CMOS cascode distributed amplifi er,” in Symp. VLSI Circuits Dig. of Tech. Papers, June 12–14, 2003, pp. 139–140.
2005 Symposium on VLSI Circuits Digest of Technical Papers
81
Low Power Programmable-Gain CMOS Distributed LNA for Ultra-Wideband Applications Frank Zhang and Peter Kinget Columbia Integrated Systems Lab Columbia University, New York, NY 10027 U.S.A. Abstract A design methodology is presented for low power distributed amplifiers and is used for the design of a mW LNA with programmable gain implemented in a m CMOS dB from DC process. The LNA provides a gain of GHz, with an input match of dB and an output to match of dB over the entire band. The IIP3 is dBm, to dB. The gain is tunable and the NF ranges from from dB to dB while gain flatness and matching are maintained.
Rd_set M8 (40/0.5) Vdd
(1.2 nH)
Rd (70 ohm) Vcascode (Gain Control)
A
Distributed Amplifier Tradeoffs Design techniques for DAs have been discussed in numerous publications [5]–[7]. At low frequencies, the gain, G of a DA is given by (1) in Fig. 1, where N is the number of stages, e.g., is the transconductance of a single stage, and R is the characteristic impedance of the line, usually 50 . At high frequencies, the expression for gain is more complicated due to its traveling-wave-like nature, but is still directly and . Pseudo-transmission lines are proportional to formed by integrating the intrinsic gate and drain capacitances, , and , of the transistors with inductors and , respectively. The bandwidth of the DA is limited by
78
4-900784-01-X
Ld (3.3 nH)
M2 (320/0.18)
M4 (320/0.18)
M6 (320/0.18)
M3 (320/0.18)
M5 (320/0.18)
Lg (2.3 nH)
(1 nH) M7 (40/0.5) Rg_set
Output
Ibias (580uA)
Rg (70 ohm)
Input
(1 nH)
Fig. 1.
(1.2 nH)
I M1 (320/0.18)
Introduction A broadband low-noise amplifier (LNA) is a critical component of the ultra-wideband (UWB) receiver [1] and cognitive radio [2]. Recent publications have reported ways to obtain flat gain for UWB through modified narrowband techniques [3] and resistive feedback [4]. This paper investigates the use of distributed amplification in the context of UWB applications and introduces a design methodology geared towards low power operation. The main advantages of a distributed amplifier (DA) are its intrinsic broadband characteristic that goes all the way down to DC, and good input and output matching. But, high power consumption and large area have limited its application space. However, when one considers the trade-off between the five main design parameters of an LNA: power drain, gain, bandwidth, noise, and linearity, it becomes evident that the traditional way of biasing a MOS DA in strong inversion, is not the optimal choice for reducing power consumption. This paper describes the design of a low-power 3-stage distributed MOS DA biased in moderate inversion (M.I.).
Ld (3.3 nH)
Lg (2.3 nH)
M9 (80/0.18)
Schematic of the 3-stage distributed amplifi er.
the cutoff frequency, , of the gate and drain lines because matching degrades as the cutoff frequency is approached. As a rule of thumb, matching better than dB cannot be achieved for frequencies above of [8]. For the gate line we obtain: (2) To achieve impedance matching, the lines are terminated in their characteristic impedance , i.e. . The is the only cutoff frequency can then be rewritten so that variable. Eq. (2) shows that to obtain a given bandwidth for a given there is an upper limit on the size of the capacitance . The figure of merit (FOM) used in most DA designs and literature is the gain bandwidth product (GBW) GBW
(3)
where is the unity gain frequency of the transistor. The important observation from (3) is that the upper bound of GBW is proportional to and . cannot be made too large since it is limited by the attenuation caused by the losses in the on-chip inductors as well as area constraints. For the technology used in this design, a 3-stage amplifier resulted in is process and bias dependent. The the best compromise. tradeoffs between inversion coefficient (IC) and have been analyzed extensively in e.g., [9]. In order to achieve high for a given technology, the devices need to be biased at a high IC, i.e. in strong inversion, and this is indeed what has been done in most DA designs. However, the usefulness of GBW as the FOM for LNA design depends on the application. As mentioned earlier, noise, linearity, and current budget are all critical, but are not reflected in GBW. Therefore, using the 2005 Symposium on VLSI Circuits Digest of Technical Papers
TABLE I LNA Tradeoffs for Fixed Power Consumption
following unit-less FOM is more appropriate for gauging the total performance of LNAs for UWB applications: FOM
W/L
(4)
where IIP3 is the input-referred third-order intercept point, is the noise factor, and is the total power consumption of the DA. We now investigate the dependence of this FOM on the DA design parameters. The expression for gain in (1) is valid for MOS transistors biased in weak inversion (W.I.) as well as in strong inversion (S.I.). To the first-order, the IIP3 of a MOS transistor [10] is (5) where n is the subthreshold slope, a unit-less technology is . In the S.I. formula, is the constant, and second-order effect of mobility degradation and has the unit of [ ] [10]. From (5), it is evident that IIP3 is constant in W.I., and is directly proportional to the overdrive in S.I.. The IIP3 of the DA tracks the IIP3 of a single MOS transistor if we assume the worst-case scenario of constructive summation of distortion components. The noise characteristic of MESFET DAs has been analyzed extensively in [11] and the results are applicable to MOSFET DAs as well. The simplified expression for F is (6) where is a noise modeling constant equal to approximately in W.I. and in S.I. The important observation is . Eqn. (6) is a that noise is inversely proportional to simplified view of DA noise since only the drain current noise is included and therefore is only valid at low frequencies. The is gate-induced noise, which is directly proportional to important and is considered in the next section. The total power consumption of the DA is equal to (7) where I is the current through one stage and is is the supply voltage. the total current budget for the DA; Substituting the results from (1), (5) (7) into (4), the FOM of the DA in W.I. and S.I. is (8) and where the substitutions are used for W.I. and S.I., respectively. Table I also illustrates the tradeoffs in W.I. and S.I., assuming fixed power consumption. of the DA the FOM in For a fixed current budget S.I. is improved by increasing the , which corresponds to reducing the overdrive and inversion coefficient and increasing ; this moves the bias point towards W.I. operation. the Once the devices operate in W.I. the FOM can no longer be improved. So, to obtain a good trade-off between the different
Operation
Gain
IIP3
NF
BW
Toward W.I. Toward S.I. Desired
DA performance parameters we need to bias the transistors as close to W.I. as possible. This is also evident from the first row in Table I. However, operation towards W.I. requires a large which implies a lower and thus larger for a given . The desired set of amplifier specifications for gain, noise, distortion, and most importantly, bandwidth, in combination with the technology performance will determine how close this optimized biasing can be achieved. Due to bandwidth limitation, the 3-stage DA described in this work is biased in moderate inversion (i.e. between W.I. and S.I.). A closed form expression for the FOM in M.I. is difficult to obtain due to the partial drift, partial diffusion behavior of the device in that region. The gain and NF characteristic of the DA moving from W.I. to S.I. is monotonic, whereas the IIP3 improves somewhat in the M.I. region [10]. Design Methodology The proposed design procedure for the 3-stage DA is as follows: First, the cutoff frequency of the gate line is calcuGHz. lated from the required bandwidth of GHz: Secondly, the maximum gate capacitance is calculated from fF. Next, using the minimum length, the (2): maximum width of the transistor is determined for the worstcase process corner: m. The width of the transistors are then selected based on the constraint set by the cascode node and the gate-induced noise, both discussed later in this section. Finally, the inductor values are determined , and the selected R, which is for both the from , gate and drain lines. a) Gate-Induced Noise: The frequency at which the gate , noise becomes comparable to the drain current noise, is critical [11]. Equating the gate-induced noise with drain current noise gives (9) is a constant equal to approximately in S.I.. must be designed to be higher than the cutoff frequency where noise starts to increase anyway due to gain rolloff. This restriction forces the width of M1 to be less than the maximum allowed by the cutoff frequency. A width of m was used for M1 based on the value calculated from Eqn. (9). b) Cascode: A cascode structure is necessary for this design because of stability concerns and the effect of Miller capacitance. The cascode transistor improves reverse isolation and at the same time minimizes C ’s effect on bandwidth. However, the side effect of using large width transistors and low bias current is that the cascode node, labeled ”A” in Fig. 1, can now limit the frequency response of the circuit. At node A, “competes” with , , and . and are junction capacitances that have become where
2005 Symposium on VLSI Circuits Digest of Technical Papers
79
(10) is the unity-gain frequency of M2. For fixed where current, increases with decreasing W2, is increases with decreasing W2. The constant, and competing requirement for W2 in the numerator and denominator of (10) implies that an optimal width for M2 exists. From simulation, the optimal value for W2 was found to be slightly less than W1; the value was close enough to W1 so m was also used for W2. that for layout reasons, c) Adjustable Termination Resistors: The frequency response of the DA is less sensitive to process variation compared to modified narrowband techniques. A variation in capacitance1 of the transmission lines results in a different , but the change in characteristic impedance, and as a result of this variation is small. For UWB applications, gain flatness down to DC is not necessary, but for applications such as cognitive radio, it is a requirement. To achieve gain flatness below GHz the termination resistors , and to account for the worst case where need to track ( ) and ( ) skew in the same direction, adjustable termination resistors shown in Fig. 1 are used; M7 and M8 devices biased in triode region. The parallel are zeropolysilicon resistor combination of M7(M8) with a provides the flexibility to adjust the termination resistance to achieve flat gain below GHz. d) Programmable Gain: A distributed amplifier has the important property that gain and broadband matching can be dealt with separately. When the cascode voltage, , is reduced, M1 moves from operation in saturation towards reduces and the gain of the amplifier can be triode. The varied. At the same time, for a substantial range in the variation in the total gate capacitance remains small and therefore good impedance matching is maintained.
10 9 8 7
S
21
[dB]
6 5 4 3 2
Measured S
1
Simulated S21
0 0
1
Fig. 2.
21
8
7
6
5 4 3 Frequency [GHz]
2
Simulated (slow-slow corner) and measured
.
0 −5 −10 S11 , S22 [dB]
significant due to the large transistors used to obtain the high -efficiency, i.e., large . Some processes offer deep-nwell nFETs with a local substrate connection, which eliminates . However, now the capacitance associated with the large deep-nwell required to contain the large transistor shunts away the signal at the cascode node at high frequencies. Another concern is that the doping inside the deep-nwell is higher than the bulk which results in higher capacitance values. Therefore we use regular bulk nFET devices in our amplifier. The width of M2 needs to be optimized to achieve the desired frequency response. The pole at node A, , is:
−15 −20 −25
Measured S11
−30
Simulated S11 Measured S22
−35
Simulated S22
−40 0
Fig. 3.
4
2
6 Frequency [GHz]
12
10
8
Simulated (slow-slow corner) and measured
and
.
The chip occupies including pads; the die photograph is shown in Fig. 6. The stages of the DA were laid out as close as possible and EM simulations where performed on the amplifier to verify that the coupling between the stages is sufficiently small. The DA consumes mA from a V supply. V is the ”true” supply voltage since no external RF choke or biasT is used. This is because the voltage drop across the drain termination resistor is small due to low current consumption. Ten amplifier samples were characterized on an RF probe station. The S-parameter data was measured using the Anritsu 37369C 40 GHz network analyzer; the data for different samples was very consistent and the results for a typical sample are shown in Fig. 2 and 3. A good input and output impedance dB are obtained between match and a flat gain of MHz and GHz. The reverse isolation, , is less than dB. The noise figure was measured using the HP8970 11 Measured NF
10
Simulated NF
9
Measurement and Results
1 Inductance
cess.
80
depends on layout geometry therefore varies little with pro-
4-900784-01-X
NF [dB]
A 3-stage DA for UWB was designed in a m CMOS process with a - m thick top metal. The custom inductor designs with polysilicon patterned ground shields were optimized using an electromagnetic simulation tool (EMX). Simulations and characterization of a inductor test structure show a quality factor of about .
8 7 6 5 4 3
Fig. 4.
1
2
3
5 4 Frequency [GHz]
6
7
Simulated (slow-slow corner) and measured noise fi gure.
2005 Symposium on VLSI Circuits Digest of Technical Papers
TABLE II LNA Performance Comparison CMOS [ m]
Flat-Gain BW [GHz]
3-dB BW [GHz]
S21 [dB]
G [dB]
S11 [dB]
Spot NF [dB] -
NF [dB]
IIP3 [dBm]
ICP [dBm]
+
-
+
-
This Work
0.18
-
[12]
0.18
-
[6]
0.6
-
[4]
0.13
[3]
0.18
-
-
-
[3]
0.18
-
-
-
-
Area [mm ]
-
mW buffer stage for output match 10 5 0 −5
−30 −35 0
22
, S
−25
0 −10 −20
11
−20
[dB]
−10 −15
S
Noise Figure meter, and is shown in Fig. 4. As expected, noise is large at low frequencies and increases after the cutoff frequency [11]. Fig. 5 demonstrates the programmable gain feature; gain is varied from dB to dB while input and output matching, and gain flatness are maintained. The linearity of the amplifier was verified with two-tone IIP3 and dB gain compression (ICP) measurements which are reported in Table II. The performance of the presented amplifier is compared with other ultra-wideband LNAs in Table II. The performance of the presented design is at par or exceeds the performance of other LNAs for UWB applications [3], [4]. The power consumption of the presented amplifier is also significantly lower than previously published DAs [6], [12] which demonstrates that the presented design methodology is effective for low power DA design.
S21 [dB]
Measured @ 2 GHz *
P [mW]
−30 0
2
8 6 4 Freqency [GHz]
2
4
10
12
6 Freqency [GHz]
Fig. 5. Measured gain for different input and output matching for different
8
10
12
voltages. Inset: Measured voltages.
Conclusion A low power MOS DA design has been demonstrated. Improvement in overall DA performance is obtained by biasing the transistors towards the weak inversion region. While this approach limits the attainable bandwidth, as the of scaled MOS transistors increases, this design approach will become even more attractive. Thanks to the operation from DC to RF, combined with the programmable gain feature, this DA design can be used in various broadband applications including UWB and cognitive radio. Acknowledgment
Fig. 6.
The authors would like to thank R. Yan of Realtek for chip fabrication; S. Kapur and D. Long of Integrand Software for the use of EMX simulation tool; Y. Baeyens of Bell Labs, Lucent Technologies for help with NF measurement; R. Gharpurey of University of Michigan for technical discussions; and Anritsu for the use of 37369C network analyzer. Frank Zhang is supported through an NSF GK-12 fellowship. References [1] S. Stroh, “Ultra-wideband: Multimedia unplugged,” IEEE Spectrum, vol. 40, pp. 23–27, Sept. 2003. [2] P. Mannion, “Sharing spectrum the smarter way,” EE Times, April 05, 2004. [3] A. Bevilacqua and A. Niknejad, “An ultrawideband CMOS low-noise amplifi er for 3.1-10.6GHz wireless receivers,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2259–2268, Dec. 2004. [4] R. Gharpurey, “A broadband low-noise front-end amplifi er for ultra wideband in 0.13um CMOS,” in Proc. IEEE Custom Integrated Circuits Conference, Oct. 3–6, 2004, pp. 605–608.
Die photograph.
[5] T. T. Y. Wong, Fundamentals of Distributed Amplification. Norwood, MA: Artech House, Inc., 1993. [6] B. M. Ballweber, R. Gupta, and D. J. Allstot, “A fully integrated 0.5-5.5GHz CMOS distributed amplifi er,” IEEE J. Solid-State Circuits, vol. 35, no. 2, pp. 231–239, Feb. 2000. [7] J. B. Beyer, S. N. Prasad, R. C. Becker, J. E. Nordman, and G. K. Hohenwarter, “MESFET distributed amplifer design guidelines,” IEEE Trans. Microwave Theory Tech., vol. 32, no. 3, pp. 268–275, Mar. 1984. [8] P. H. Ladbrooke, MMIC Design: GaAs FETs and HEMTs. Norwood, MA: Artech House, Inc., 1989. [9] D. M. Binkley, C. E. Hopper, S. D. Tucker, B. C. Moss, J. M. Rochelle, and D. P. Foty, “A CAD methodology for optimizing transistor current and sizing in analog CMOS design,” IEEE J. Technol. Computer Aided Design, vol. 22, no. 2, pp. 225–237, Feb. 2003. [10] B. Toole, C. Plett, and M. Cloutier, “RF circuit implications of moderate inversion enhanced linear region in MOSFETs,” IEEE Trans. Circuits Syst. I, vol. 51, no. 2, pp. 319–328, Feb. 2004. [11] C. Aitchison, “The intrinsic noise fi gure of the MESFET distributed amplifi er,” IEEE Trans. Microwave Theory Tech., vol. 33, no. 6, pp. 460–466, June 1985. [12] R.-C. Liu, C.-S. Lin, K.-L. Deng, and H. Wang, “A 0.5-14-GHz 10.6dB CMOS cascode distributed amplifi er,” in Symp. VLSI Circuits Dig. of Tech. Papers, June 12–14, 2003, pp. 139–140.
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