Low THD bandpass-based oscillator using multilevel ... - IEEE Xplore
Low THD bandpass-based oscillator using multilevel hard limiter F. Bahmani and E. Sa´nchez-Sinencio Abstract: In order to reduce the total harmonic distortion (THD) of a bandpass-based oscillator, instead of using a conventional hard limiter, a multilevel hard limiter (MHL) is proposed which inherently removes the third and the fifth-order harmonics from the frequency spectrum of its output signal. The input– output characteristic of the proposed MHL contains slope values of only zero and infinity, making it easy to implement. The optimal height and width of each stair of the MHL characteristic are derived. Measurement results show that for the same bandpass filter, the proposed approach shows 14 dB improvement in the THD of the output signal with respect to the conventional two-level hard limiter (comparator). The oscillator has been fabricated in TSMC 0.35 mm CMOS process and the die occupies an area of about 3.15 mm2. The oscillator chip prototype operates at the frequency of 10.7 MHz, consumes 40 mA current from a 3.3 V power supply and yields a THD of 253 dB.
1
Introduction
Sine wave generators are required in a number of diverse application areas, including audio testing, calibration equipment, transducer drivers, power conditioning and automatic test equipment. As the other characteristics of integrated circuits improve with technology, the linearity and spectral purity of the signals generated in systems become increasingly important [1]. Producing and manipulating the sine wave function is a common problem encountered by circuit designers. A sinusoidal oscillator is a combination of a selective (linear) circuit to set the oscillation frequency, a power boosting element at the oscillation frequency and an active element (limiter) to stabilise the oscillation amplitude [2]. To start-up the oscillation, the poles of the linearised circuit have to be on the right half plane of the complex frequency plane. The actual placement of the poles on the imaginary axis is due to the nonlinear components in a positive feedback loop. The selective network is ideally composed entirely of linear elements and includes reactive components, which can be reduced to a simple resonant circuit or a bandpass filter (BPF). The active element has the essential feature of being nonlinear (hard limiter) and is assumed to be free from reactive parameters. Therefore its behaviour is defined by a static characteristic of arbitrary shape. The property of the static characteristic of the nonlinear active element (limiter) essentially determines the level of distortion of the generated sinusoidal signal. However, the nonlinearities may cause the oscillation frequency to deviate from that expected based on linear operation if the amplitude becomes excessive. For example, in a master – slave tuning scheme, a voltage-controlled # The Institution of Engineering and Technology 2007 doi:10.1049/iet-cds:20060072 Paper first received 25th February and in final revised form 10th October 2006 The authors are with Analog Mixed-Signal Center, Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3128 USA E-mail: [email protected] IET Circuits Devices Syst., 2007, 1, (2), pp. 151 –160
oscillator (VCO) with significant nonlinearities, even though locked to the external clock with a phase-locked loop, results in a poor tracking operation [1]. Thus, VCO linearity is critical and is maintained by controlling the amplitude of the oscillation so that the effect of the selective circuit nonlinearities on the oscillation frequency is minimised. Amplitude control can be achieved with an automatic gain control circuit or more simply with a carefully designed hard limiter circuit. LC tank [3] and active-RC [4] circuits are among the most popular approaches to implement oscillators. Although for practical reasons the former approach is not preferred for implementations at relatively low-frequencies, the latter one suffers from the frequency limitation of the active elements (opamp) operating in closed loop. Operational transconductance amplifier (OTA)-based oscillators seem to be a better solution for frequencies below gigahartz due to the fact that they have high frequency poles and operate in open-loop architectures [5]. Here, a bandpass-based oscillator using the proposed multilevel hard limiter (MHL) is presented. It is shown that for the same BPF using the MHL, the linearity of the output signal is significantly improved in comparison with the traditional two-level hard limiter static characteristic. 2
Bandpass-based oscillator theory
The bandpass-based oscillator, shown in Fig. 1a, consists of a BPF as the selective element together with a hard limiter as the active element in positive feedback [5 – 7]. The conventional oscillator uses a two-level comparator as indicated in Fig. 1b, where z0 is the clamping amplitude and x0 is the threshold for the input signal, that is f (x) ¼ mx for jxj , x0 and f(x) ¼ sign(x)z0 for jxj . x0 . A sound use of the BPF in this structure allows decoupling the amplitude and frequency controls of the oscillator. That is, the oscillation amplitude is indirectly controlled by the clamping levels +z0 of the active element (comparator) while the oscillation frequency is changed by tuning the centre frequency of the BPF. The above property is due to the fact that only at the centre frequency of the BPF, the loop 151
y
(Selective element) Bandpass filter
H(s)
y = f (x )
d2 xðtÞ dxðtÞ v0 k þ NðA Þ þ v20 xðtÞ = 0 0 0 dt2 dt Q
z0
x
m
− x0
x0
Static characteristic f(⋅) (Active element) a
Fig. 1
can be written as
x
Once the steady state is achieved, the oscillation amplitude A0 can be determined from (5). 1 v0 ð6Þ A0 ’ N k0 Q
− z0 b
Bandpass-based oscillator
a Block diagram of a bandpass-based oscillator b Conventional static characteristic
gain phase becomes zero. If the gain in the feedback loop is made much larger than unity (before clamping), the feedback loop can be viewed as a sine-to-square wave converter. Owing to the presence of the BPF, which attenuates the harmonics of the square wave but the fundamental one, the describing function (DF) [8] method can be used to study the dynamic behaviour of the loop. In this technique, the input of the nonlinearity is assumed to be an undistorted sinusoidal signal, x(t) ¼ A0 sin(v0t). The higher-order harmonics present in the output signal y(t) in Fig. 1a are supposed to be filtered out sufficiently by BPF. Assuming A0 . x0 , the amplitude of the fundamental component a sin(v0t) of y(t) can be found from its Fourier series as 2 a¼
2mA0 4 1 x0 sin p A0
3 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ffi x x þ 0 1 0 5 A0 A0
ð1Þ
where m is the slope of the nonlinear characteristic in Fig. 1b and T ¼ 2p/v0 is the period of the signal. Thus, the DF of the nonlinear block in Fig. 1b, which is the linear gain relating the amplitude of the fundamental component at the output to that of the input, can be expressed as a A0 8 2 3 > 1 x0 > > sin > > 6 7 A0 > < 2m 6 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi7 6 7 2 ¼ p 4 x0 x0 5 > > 1 þ > > A0 A0 > > : m
N ðA0 Þ ¼
A0 . x0
Observe that the oscillation frequency is equal to v0 and independent of the oscillation amplitude. Next, we propose an MHL scheme that combined with a BPF yields an enhanced total harmonic distortion (THD) of the bandpass-based oscillator waveform. 3 Proposed MHL Few have been reported in the literature regarding the optimum shape of MHL (static characteristic) block in order to reduce its output harmonic distortion. Regarding the possible nonlinearities to be used in the feedback loop of Fig. 1a, some restrictions must be made; otherwise, the study of the oscillation made by the DF methodology is not feasible. We will exclusively focus on switching characteristics, that is slopes are only zero or infinity. Furthermore, practical implementation of these elements is relatively easy. 3.1 Optimum static characteristic (multilevel hard limiter) For the generalised static characteristic in Fig. 2, the output must be bounded therefore the slope of mN should be zero, where N is the number of levels. To determine the remaining slopes in Fig. 2, the input and output of the static characteristic block are assumed to be x(t) A0 sin v0t and y(t) ’ a sin v0t, respectively. Note, because of the odd symmetry of Fig. 2, y(t) does not contain any cosine terms. To find the output amplitude a, the time ti where the input amplitude A0 exceeds the voltage level of xi must be known. 1 1 xi ; i ¼ 1; 2; . . . ; N 1 ð7Þ sin ti ¼ v0 A0
ð2Þ
y = f (x) yN y2
A0 , x0
Therefore the hard limiter function f(.) in Fig. 1a can be expressed as a linear function whose slope depends on the oscillation amplitude A0 , that is df(x)/dx ¼ y/x ’ N(A0) Hence, the DF of the whole oscillator in Fig. 1a can be related to the transfer function of the BPF (H(s)) as HðsÞ ¼
X ðsÞ 1 ¼ Y ðsÞ N ðA0 Þ
ð5Þ
ð3Þ
mN +2
m3
y1 y0
m2
− x N − x2 − x1 − x0
m3
m1 x0
m2
x1
x2 x N
x1
x2 x N
x
− y0 − y1
− y2 − yN
mN +2
− x N − x2 − x1 − x0 t2
t1 t 0
x0
x(t )
tN
Assume the BPF has the following transfer function HðsÞ ¼
s2
k0 s þ ðv0 =QÞs þ v20
where Q and v0 are the quality factor and the centre frequency of the BPF, respectively. Using (3) and (4), the time domain differential equation associated with the closed-loop block diagram of Fig. 1a 152
T + ti 2
ð4Þ
t
Fig. 2 Generalised static characteristic IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
Table 1: Pn(ri) functions for an 5 1, 3, 5 and 7 n¼1 n¼3 n¼5 n¼7
P1 (ri) ¼ r(ri)
p P3 (ri) ¼ 22r3i (1 2 r2i ) p P5 (ri) ¼ 2/3ri(3 2 4r2i ) (12 r2i (3 2 4r2i )2) p 2 2ri (1 2 2r2i ) (1 2 r2i ) 2 p P7 (ri) ¼ ri/3(1 2 2ri ) (1 2 r2i )(12 16r2i (12 2r2i ) p (1 2 r2i )) 2 (22/3ri) (3 2 4r2i ) (1 2 r2i (3 2 4r2i )2)
as an ¼ ðm1 m2 ÞPn ðr1 Þ þ ðm2 m3 ÞPn ðr2 Þ þ m3 Pn ðr3 Þ; n ¼ 1; 3; 5; 7; . . . ð16Þ
Fig. 3 Optimum static characteristic a Four-level static characteristic b Four-level MHL optimised to reduce THD
Using f(x) for different intervals of x in Fig. 2, the output amplitude a with mN ¼ 0 can be found as a¼ where
1 A0 NX ðm miþ1 Þrðri Þ 2p i¼1 i
qffiffiffiffiffiffiffiffiffiffiffiffiffi 2 1 sin ðri Þ þ ri 1 r2i ; rðri Þ ¼ p
ð8Þ
ri , 1
ð9Þ
ð10Þ
Thus, on the basis of (8) the DF of Fig. 2 can be expressed as NðA0 Þ ¼
1 1 NX ðm miþ1 Þrðri Þ 2p i¼1 i
ð11Þ
Suitable choices of r(ri) and mi can minimise the output harmonics. This is explored next. As an example, a system with N ¼ 4 will be analysed. The transfer characteristic of the analysed system is shown in Fig. 3a. The DF can be found as N ðA0 Þ ¼
1 ðm rðr Þ þ ðm2 m3 Þrðr2 Þ 2p 3 3 þ ðm1 m2 Þrðr1 ÞÞ
ð12Þ
When the circuit reaches a steady-state oscillation (i.e. s ¼ jv0), the slopes of the hard limiter characteristic of Fig. 3a can be obtained using (6) and (12). 2pv0 m3 ðrðr3 Þ rðr2 ÞÞ m2 ðrðr2 Þ rðr1 ÞÞ k Q m1 ¼ 0 ð13Þ rðr1 Þ 2pv0 m3 ðrðr3 Þ rðr2 ÞÞ m1 rðr1 Þ k0 Q m2 ¼ rðr2 Þ rðr1 Þ 2pv0 m1 rðr1 Þ m2 ðrðr2 Þ rðr1 ÞÞ k Q m3 ¼ 0 rðr3 Þ rðr2 Þ
ð14Þ
ð15Þ
Using (8) for N ¼ 3, the Fourier series coefficients an of the output of the MHL block for A0 . x2 can be calculated IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
an ¼ ðm1 m2 ÞPn ðr1 Þ þ m2 Pn ðr2 Þ;
n ¼ 1; 3; 5; 7; . . . ð17Þ
where x ri ¼ i A0
where the index n represents the odd harmonics. The Pn functions are introduced to simplify the notation for an . The Pn functions to calculate the first four odd harmonics are shown in Table 1. It is important to note that for all Pn(r1) functions in Table 1 Pn(0) ¼ 0. This property will be exploited to find the optimum slopes of the nonlinear characteristic of Fig. 2 and Fig. 3a to make null the third and the fifth harmonic components. If r2 ¼ r3 , the expression for an can be simplified to
Analysing Fig. 3a and using r2 ¼ r3 , which implies r(r2) ¼ r(r3) and x2 ¼ x3 , result in m3 ¼ 1. The same result could have been obtained from (15) knowing r(r2) ¼ r(r3) implying a denominator of zero. Our ultimate goal is to minimise the number of harmonics at the output of the MHL. The first step in doing this was setting m3 ¼ 1. To further simplify an , the remaining terms must be reduced. The second term in (17) can be made zero by choosing m2 ¼ 0, or by setting r2 ¼ 0 implying x2 ¼ 0. When m3 was set to infinity previously, x2 was made equal to x3 . Therefore x2 ¼ x3 ¼ 0 would result in m1 ¼ m2 ¼ m3 ¼ 1 and the static characteristic in Fig. 3a would result in a two-level hard limiter (comparator). From here, the scenario of m2 ¼ 0 is a better option to null the second term without compromising the characteristic of the active element. To null the remaining term in (17) there are two possibilities. First, m1 can be set to 0. However, this choice of m1 ¼ 0 results in a dead band in the characteristic of the nonlinear block and prevents the start-up of the oscillator (Fig. 3a). The second method to cancel the first term in (17) would be to set r1 ¼ 0. Having r1 ¼ 0 implies x1 ¼ 0 and r(r1) ¼ 0 which makes m1 ¼ 1. From (13), having r(r1) ¼ 0 will also result in m1 ¼ 1, verifying the result. Fig. 3b shows the resultant four-level MHL with m1 ¼ 1, m2 ¼ 0, m3 ¼ 1 and m4 ¼ 0. It is worth mentioning that in (17), the product of mi and Pi(r1) cannot be zero (mi Pi(r1) ¼ 1 0). This multiplication implies ai must always have a finite value. Although the output harmonics cannot be made zero, the THD at the output of the active element can be minimised if odd slopes (m1 , m3 , m5 , . . .) are made infinite and even slopes (m2 , m4 , m6 , . . .) are made zero. From the previous example where N ¼ 4, a more general output static characteristic can be obtained to minimise the output harmonics of the hard limiter. For even integer number of levels N it is required that N ¼ 2k, where k is an integer number. The generalised static characteristic for minimised output harmonics is shown in Fig. 4. Next 153
Fig. 4 Generalised harmonics
static
characteristic
for
minimised
the detailed analysis of finding the optimum values of xi and yi to null the third and the fifth-order harmonics at the output of the MHL block is presented. 3.2
harmonics of fc(t) can be expressed as
y1 2p þ cos a 0 ðv 0 Þ ac ðv0 Þ ¼ y2 y2 T1 y1 6p a0 ð3v0 Þ þ cos ac ð3v0 Þ ¼ y2 y2 T1 y 10p a0 ð5v0 Þ ac ð5v0 Þ ¼ y2 1 þ cos y2 T1
Time domain characterisation
Previously, the slopes of the MHL block were determined on the basis of a combination of a general analysis and a specific example. However, to implement the MHL block into a practical system, the values of xi and yi must be exactly determined. Assuming xi ¼ yi , if a sine wave with the amplitude equal to yN is applied as the input to the generalised static characteristic shown in Fig. 4, the resulting positive half wave is as shown in Fig. 5. To obtain the values of xi and yi , a Fourier analysis must be performed on the output of the MHL (Fig. 5). To begin, a simple comparator will be used as the limiter building block. The reference level of this block will be taken as zero such that the generated output will be a square waveform. The output of this comparator with a reference of zero will be denoted f0(t). There are two methods which may be used to obtain the output waveform shown in Fig. 5. The first implementation focuses on using the sum of the outputs of 2N 2 1 comparator’s with different references of +yi . However, if this method is used, besides the increased power consumption and complexity, the exact times (ti) where the output’s are summed will vary based on fluctuations in the reference levels of the different comparator’s. These fluctuations will produce an unwanted output waveform which could cause the system not to operate as desired. The second implementation to obtain the MHL output as shown in Fig. 5 is based on using only one comparator with a reference voltage of zero. To illustrate this methodology, again we use the previous example of a four-level static characteristic. The output of this block for a sinusoidal input is shown in Fig. 6. As depicted in Fig. 7, the output of this block fc(t) can be obtained by summing f0(t) (ideal comparator output) together with two other properly scaled and time-shifted versions of f0(t). fc ðtÞ ¼ y1 f0 ðtÞ þ
ð19Þ ð20Þ ð21Þ
where T1 ¼ T/t1 and a0(nv0) and ac(nv0), n ¼ 1, 3 and 5, are the coefficients of the Fourier series of f0(t) and fc(t), respectively. A careful examination of (20) and (21) shows that in the case of a linear relation between y1 and y2 , a proper value of T1 can make the two terms inside the brackets zero. To find this proper value of T1 , the terms of cos(ip/T1) for i ¼ 2, 6 and 10 as functions of T1 are plotted in Fig. 8. In order to simultaneously null the third and the fifth-order harmonics, it is required that p T1 ¼ 8 which yields cos(6p/T1) ¼ z cos(10p/T1) ¼ 2 2/2. Thus, to make (20) and (21) zero, y1 and y2 have to be related as y2 pffiffiffi ¼ 2 y1
ð22Þ
p Note that for y2/y1 ¼ 2 and tp0 ¼ T/8, from (19) it can be concluded that ac(v0) ¼ ( y2/ 2) a0(v0), which means that the oscillation amplitude can be tuned by changing y2 while maintaining the condition described by (22).
3.3
General case: multilevel hard limiter
From the previous example, a general expression for the output f(t) of the MHL block in Fig. 5 can be derived by
y2 y T f0 ðt t1 Þ 2 f0 t t1 ð18Þ 2 2 2
where y1 and y2 are amplitudes of the stairs of waveform of Fig. 6. The sum operation in Fig. 7 is a mathematical sum and it is just a conceptual diagram to construct fc(t). However, this concept has been used in Section 4.1 in implementing the MHL block in current mode which makes the sum operation feasible. Note that due to the symmetry of fc(t), the even harmonics of its Fourier series are zero. The first odd 154
Fig. 5 Output of MHL for N slopes and a sine wave input
Fig. 6 Input (thin line) and output (thick line) of the nonlinear characteristic of Fig. 3b IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
Fig. 7 Decomposition of the output of the MHL block
induction as fc ðtÞ ¼ f0 ðtÞ þ
1 1 NX T ti yi f0 ðt ti Þ yi f0 t ð23Þ 2 i¼1 2
Thus, the Fourier series of the output signal fc(t) can be found as N 1 X ac ðnv0 Þ ¼ a0 ðnv0 Þ 1 þ yi ð1 ð1Þn Þ i¼1
cosðv0 ti Þ
;
n ¼ 3; 5; 7; . . .
ð24Þ
where ac(nv0) and a0(nv0) are the Fourier series coefficients of fc(t) and f0(t), respectively. It can be demonstrated that for specific values of k and n, the following expressions of ti and yi make (24) zero. T
i ¼ 1; 2; 3; . . . p yi ¼ cos Kþ1 i ; i ¼ 1; 2; 3; . . . 2 ti ¼
2Kþ2
i;
ð25Þ ð26Þ
The above fact has been visualised in Fig. 9 for k ¼ 1, 2, 4 and 8 and n ¼ f/f0 . In the case of four-level MHL, that is k ¼ 2 in Fig. 9, the absence of the third and the fifth-order harmonics in the frequency spectrum of the output signal of the proposed MHL has a significant effect on increasing the spectrum purity of
Fig. 8 Plots of cos(ip/T1) for i ¼ 2, 6 and 10 against T1 IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
the sinusoidal output without any extra effort to implement a significantly high-Q BPF. 3.4
Non-ideal effects
In implementation of fc(t), based on (23), the main sources of non-idealities are finite slopes (mi) and inaccuracy in the switching time ti . Considering the above effects, the output waveform of the previously studied four-level MHL block in Fig. 3 can be modelled as the waveform shown in Fig. 10. In this figure, the deviation of the slopes from their ideal (infinity) values correspond, to the deviation of t0 and t1 from their ideal values, zero and T/8, respectively. The nth Fourier series coefficient, taking into account these non-idealities, can be calculated as a^ c ðnv0 Þ ¼
ð1 ð1Þn Þsincðnv0 t0 =2Þ np nv t 0 0 þ ðy2 y1 Þ y1 cos 2 Dt1 cosðnv0 t1 þ 2
ð27Þ
where Dt1 ¼ ( y2 2 y1)/m3 and t0 ¼ y1/m1 . Note that for Dt1 ¼ 0 and t0 ¼ 0, (27) becomes (24). The overall THD of this waveform as well as the third and
Fig. 9 Frequency spectrum of the MHL (limiter) with different possible levels 155
Fig. 10
Non-ideal effects due to finite slopes of Fig. 3
Fig. 11 THD of the proposed four-level and the two-level (comparator) MHLs as a function of t0 and t1 in Fig. 6
the fifth-order harmonic distortions (HD3 and HD5) are shown in Figs. 11 and 12, respectively. The horizontal axes correspond to t0 and t1 and the vertical axis corresponds to distortion. Note that for values of t0 = 0 and t1 = T/8, the HD3 and the HD5 grew drastically from zero while the overall THD improves. The improvement in the THD is expected due to finite slopes, but it is not of interest since the higher harmonics of the output is attenuated by the BPF anyway. However, as Figs. 12a and 12b show, even with deviation of t0 and t1 from their ideal values, the HD3 and the HD5 of the proposed MHL are considerably below their corresponding values (Fig. 12c) for the conventional two-level hard limiter. Another source of non-ideality in implementation of fc(t) p is the deviation of y2/y1 from its ideal value of 2. The HD3 of fc(t) as a function of this deviation has been plotted in Fig. 13. For the purpose of comparison, the behaviour of HD3 as a function of t0 has been plotted in the same figure as well. The variations in y2/y1 and t0 are normalised and the new variable is pcalled Knorm so that Knorm ¼ 0 corresponds to y2/y1 ¼ 2 and t0 ¼ T/8. In other words, the horizontal axis in Fig. 13 represents the variations of both y2/y1 and t0 . Observe that for any Knorm = 0, the net change in HD3 due to t0 is greater than the corresponding change due to y2/y1 . 4
Circuit implementation
Fig. 14 shows the overall block diagram of the fabricated chip. A conventional two-level hard limiter (comparator)
Fig. 12
Third and fifth-order harmonic distortions
a HD3 as a function of t0 and t1 for the proposed four-level MHL b HD5 as a function of t0 and t1 for the proposed four-level MHL c HD3 and HD5 for two-level (comparator) MHL 156
IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
is included in the design to compare its performance with the proposed MHL block. A linearised transconductance buffer [9] is employed to monitor the output signal. 4.1
BPF design
To increase the linearity of the oscillator, besides increasing the Q, the nonlinearities associated with the BPF need to be minimised. Hence, a BPF using the linearised pseudodifferential OTA [10] has been designed. Fig. 15 shows the block diagram of the two-integrator loop biquad Gm-C filter. This topology is often preferred with respect to other versions since an additional low pass output is available. Furthermore, it has the advantage of allowing the control of the common-mode voltage at both integrator outputs. In addition, a minimum sensitivity of the quality factor with respect to capacitance mismatch is achieved by choosing C1 ¼ C2 [11]. Fig. 13 HD3 as a function of y2/y1 (solid line) and t0 (dashed lined)
Fig. 14 Overall block diagram of the oscillator for testing purposes
Fig. 15 Biquad Gm-C BPF
4.2
MHL static characteristic implementation
The main challenge in implementing the nonlinear characteristic of the MHL in Fig. 3b is the accuracy of the comparison of the sinusoidal input with zero and x1 . This problem can be avoided by emulating the performance of the static characteristic based on the decomposition of the waveforms in square waves as shown in Fig. 7. In this technique, the output signal of the BPF is only compared with zero and two independent delay lines generate the other two timeshifted waveforms. Its implementation is shown in Fig. 16. This implementation requires three tasks of comparison, time delay and digital to analogue (DAC) conversion. The input comparator compares the input signal with ground to generate the base square wave f0(t) in Fig. 7. Two separate delay lines generate f0(t 2 t1) and f0(t 2 (T/2 2 t1)). By having a well-characterised delay cell and using two decoders, it is possible to tune the total delay of the delay lines by configuring the delay cells in each line. In this technique, as shown in Fig. 16, each delay cell can be bypassed using a switch whose control signal is one of the output bits of a thermometer decoder. Thus, when the input word of the decoder is changed by one bit, one delay cell is configured in the delay chain. However, for simplicity, these decoders are not incorporated in our design. Instead, two separate delay lines with three and 10 delay cells are used to delay f0(t) by t1 and T/2 2 t1 , respectively. The propagation delay time of each delay cell, shown in Fig. 17, is directly
Fig. 16 Implementation of the proposed MHL block IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
157
Fig. 17
Schematic diagram of an NP-voltage cascade inverter
proportional to Vdd [12] and the load CL. 1 tdelay ¼ ðtpHL þ tpLH Þ 2 ¼
CL VDD 1 1 þ 2 kp Vp2 kn Vn2
Fig. 18
5 ! ð28Þ
where kp ¼ 0.5 mnCox(W/L)n and kn ¼ 0.5 mpCox(W/L)p and Vp and Vn are the bias voltages of the p-type and n-type current sources in Fig. 17, respectively. Thus, by using the delay cell shown in Fig. 17 the total delay of each line can be tuned by changing the Vdd of the corresponding delay cells. The square wave f0(t) and its delayed versions are controlling two groups of switches, Ms1–Ms3 and Ms4–Ms6, which conceptually form a 3-bit DAC circuit. Transistors M1–M9 provide the reference currents for the switches Ms1–Ms6. The three switches of Ms1–Ms3 generate the positive portion of the composite pulse fc(t) and its negative portion is generated by Ms4–Ms6. The currents of these two groups of switches after being summed up at the output nodes, across fc(t), are converted to voltage using two matched resistors R ¼ p 10 kV. To implement the 2 ratio between the two levels of the output voltage (22), the currents following through the switches have to be properly scaled with respect to IREF ¼ 20 mA which result in the following relations between the current sources in Fig. 16 W W W W W ¼ ¼ and ¼ L 1 L 3 L 5 L 6 L 8 W W W ¼ ¼ 0:7 and L 2 L 4 L 1 W W W ¼ ¼ 0:7 L 7 L 9 L 6
ð29Þ
Experimental results
The oscillator chip prototype was fabricated in TSMC 0.35 mm CMOS technology through and thanks to MOSIS. The micrograph is shown in Fig. 19. The die size occupies a silicon area of about 3.15 mm2. Fig. 20 shows the measured frequency response of the BPF which shows a centre frequency and quality factor of around 10.6 MHz and 20, respectively. A linear buffer, shown in Fig. 21, is used at the output of the BPF to convert the internal voltage mode signals to current [9]. The linearity of the buffer is adjustable through Ibias2 . To characterise the contribution of the BPF on the overall HD3 of the oscillator, an IM3 measurement has been carried on the cascade combination of the BPF and the buffer and the result is shown in Fig. 22. The two input tones are at frequencies of 10.65 and 10.75 MHz with equal amplitudes of 0.5 Vpp. The best obtained IM3 of the buffer is 263 dBm. From Fig. 14, by closing the loop of the filter and the nonlinear block, the circuit starts oscillating and its output spectrum for both cases of the conventional comparator and the proposed MHL are shown in Figs. 23 and 24, respectively. Note that to have a fair comparison between the two scenarios, the reference current IREF in Fig. 16 has been adjusted so that the oscillation amplitudes of both cases are the same. Comparing these results shows a 224 dB improvement in the reduction of the third-order harmonic distortion at the output of the filter in the case of the proposed MHL. Observe that the fifth-order harmonic is reduced by several decibels in Fig. 24, but its improvement is not as visible as the third-order one due to the attenuation of
ð30Þ
To compensate for the effect of the process variations on the absolute values of the delays, the delay networks are made configurable using two independent 3-bit words. Moreover, reducing the mismatch between delay cells by careful layout design can improve the accuracy of the delay line. However, a more precise implementation of the delay line can be obtained by using a delay locked-loop (DLL) [13] at the cost of more complexity and increased power consumption. The input comparator [14], required in Fig. 16, is depicted in Fig. 18. It is a synchronous high-speed comparator consisting of a cascade of a pre-amplifier, latch, self-biased differential amplifier and output driver. The quiescent current of the comparator is 90 mA. 158
Two stage opamp used as the comparator [13]
Fig. 19
Layout of the chip IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
Fig. 20 Frequency response of the BPF
Fig. 23 Output spectrum of the oscillator with a conventional two-level comparator
Fig. 21 Output buffer schematic
the filter. However, the seventh-order harmonics are comparable which is consistent with the analytical results obtained in (24). It is important to mention that the measured result in the case of the proposed MHL block is the best obtained result through adjusting the delay cells in Fig. 16 which tunes the delay time of t1 in Fig. 6. This has been achieved by changing the digital word controlling the delay cells in Fig. 16 in order to maintain the requirement of T1 ¼ T/t1 ¼ 8. If we assume that the first seven harmonics are the main harmonics at the output, the overall THD of the measured frequency spectra of Figs. 23 and 24 can be calculated as 238.63 and 253.16 dB, respectively. These results show that more than 14 dB improvement in the THD can be achieved by using the proposed MHL block. Fig. 25 shows the
Fig. 24 Output spectrum of the oscillator with the proposed multilevel comparator
theoretical predictions of THD against different quality factors of the BPF for both the comparator and the MHL block. This figure shows that, for the measured quality factor of 15, the experimental results are in good agreement with the theory. The performance of the VCO built using the proposed MHL block against some of the previously published works has been summarised in Table 2. The key advantage of using the proposed MHL
Fig. 25 Fig. 22 IM3 measurement results for the buffer IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
THD of the oscillator as a function of the quality factor
Solid lines: analytical; circles: experimental 159
Table 2: Summary of performance f0 , MHz
Q 8
Area mm2
Technology
Pdiss, mW
THD, dB 233
Rodriguez-Vazquez et al. [5]
7.76
3 mm CMOS
–
–
Pavan and Tsividis [7]
0.0135
20
Discrete
–
–
238
This work
10.7
15
0.35 mm CMOS
3.15
132
253
the bandpass filter. In our case, the required quality factors were 5 and 30 to yield the same THD of 247 dB. The proposed MHL has the potential to be applied to other applications requiring switching [15]. 7
Acknowledgment
The authors thank Jason Lee Wardlaw for his help in editing the paper. 8
Fig. 26 Comparison of HD3 as a function of the delay time deviation
block is the significant increase in the linearity of the output signal with a moderated value of Q. Fig. 26 shows the effect of the delay cells on the HD3 of the proposed architecture in both simulation and measurement cases. The horizontal axis represents the percentage of the delay with respect to the fundamental period T. To explore the effect of using a DLL to generate the delayed pulses, a system level simulation using SIMULINK has been carried out and the results are shown in Fig. 26 as well. In the DLL-based implementation, for a small range of the delay introduced to each cell, the composite waveform fc(t) generated by the DLL remains insensitive to the delays which yield a nearly constant HD3. As it can be seen from this figure, there is only one optimum delay for which the measured HD3 is reduced and this value is around 1/8 of the fundamental period T. Deviation from this optimal value for delay results in a degraded HD3 as it has been verified by the measurement results. 6
Conclusions
A bandpass-based oscillator using an MHL has been presented. The proposed MHL used in a bandpass-based oscillator provides an improvement of 14 dB in THD with respect to the conventional two-level hard limiter. Furthermore, to obtain the same THD for an oscillator using the proposed MHL and the conventional limiter, the proposed one will require a much lower quality factor of
160
References
1 Khoury, J.M.: ‘Design of a 15-MHz CMOS continuous-time filter with on-chip tuning’, IEEE J. Solid-State Circuits, 1991, 26, (12), pp. 1988– 1997 2 Bergen, A.R., Chua, L.O., Mees, A.I., and Szeto, E.W.: ‘Error bounds for general describing function problems’, IEEE Trans. Circuits Syst., 1982, 29, pp. 345–354 3 Hajimiri, A., and Lee, T.H.: ‘Design issues in CMOS differential LC oscillators’, IEEE J. Solid-State Circuits, 34, (5), pp. 717– 724 4 Vosper, J., Deloughry, R., and Wilson, B.: ‘Multiphase active-RC sinusoidal oscillators incorporating lowpass and allpass sections’. IEEE European Conf. on Circuit Theory and Design, August 2005, pp. 27–30 5 Rodriguez-Vazquez, A., Linares-Barranco, B., Huertas, J.L., and Sa´nchez-Sinencio, E.: ‘On the design of voltage-controlled sinusoidal oscillators using OTA’s’, IEEE Trans. Circuits Syst., 1990, 37, (2), pp. 198–211 6 Verhoeven, C.J.M., and Staveren, A.V.: ‘First and second order oscillators’. IEEE Int. Symp. on Circuits and Systems, May 2001, Tutorial Guide, pp. 6.1_1– 6.1_31 7 Pavan, S., and Tsividis, Y.P.: ‘An analytical solution for a class of oscillators, and its application to filter tuning’, IEEE Trans. Circuits Syst. I, 1998, 45, (5), pp. 547–556 8 Gelb, A., and Velder, W.A.: ‘Multiple-input describing functions and nonlinear system design’ (McGraw-Hill, New York, 1968) 9 Chen, J., Sa´nchez-Sinencio, E., and Silva-Martinez, J.: ‘Frequencydependent harmonic-distortion analysis of a linearized cross-coupled CMOS OTA and its application to OTA-C filters’, IEEE Trans. Circuits Syst. I, 2006, 53, (3), pp. 499–510 10 Bahmani, F., and Sa´nchez-Sinencio, E.: ‘A highly linear pseudodifferential transconductance’. IEEE European Solid State Conf., September 2004, pp. 111–114 11 Rezzi, F., Baschirotto, A., and Castello, R.: ‘A 3 V 12– 55 MHz BiCMOS pseudo-differential continuous-time filter’, IEEE Trans. Circuits Syst. I, 1995, 42, pp. 896–903 12 Rabaey, J.M., Chandrakasan, A., and Nikolic, B.: ‘Digital integrated circuit’ (Prentice-Hall, 2002, 2nd edn.) 13 Baronti, F., Lunardini, D., Roncella, R., and Saletti, R.: ‘A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme’, IEEE J. Solid-State Circuits, 2004, 39, (2), pp. 384–387 14 Baker, R.J., Li, H.W., and Boyce, D.E.: ‘CMOS circuit design layout, and simulation’ (IEEE Press, Piscataway, NJ, 1998), Chap. 26 15 Weldon, J.A., Rudell, J.C., Li, L., Sekhar Narayanaswami, R., Otsuka, M., Dedieu, S., Luns, T., King-Chun, T., Cheol-Chun, L., and Gray, P.R.: ‘A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers’, IEEE J. Solid-State Circuits, 2001, 36, (12), pp. 2003– 2015
IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
1
Introduction
Sine wave generators are required in a number of diverse application areas, including audio testing, calibration equipment, transducer drivers, power conditioning and automatic test equipment. As the other characteristics of integrated circuits improve with technology, the linearity and spectral purity of the signals generated in systems become increasingly important [1]. Producing and manipulating the sine wave function is a common problem encountered by circuit designers. A sinusoidal oscillator is a combination of a selective (linear) circuit to set the oscillation frequency, a power boosting element at the oscillation frequency and an active element (limiter) to stabilise the oscillation amplitude [2]. To start-up the oscillation, the poles of the linearised circuit have to be on the right half plane of the complex frequency plane. The actual placement of the poles on the imaginary axis is due to the nonlinear components in a positive feedback loop. The selective network is ideally composed entirely of linear elements and includes reactive components, which can be reduced to a simple resonant circuit or a bandpass filter (BPF). The active element has the essential feature of being nonlinear (hard limiter) and is assumed to be free from reactive parameters. Therefore its behaviour is defined by a static characteristic of arbitrary shape. The property of the static characteristic of the nonlinear active element (limiter) essentially determines the level of distortion of the generated sinusoidal signal. However, the nonlinearities may cause the oscillation frequency to deviate from that expected based on linear operation if the amplitude becomes excessive. For example, in a master – slave tuning scheme, a voltage-controlled # The Institution of Engineering and Technology 2007 doi:10.1049/iet-cds:20060072 Paper first received 25th February and in final revised form 10th October 2006 The authors are with Analog Mixed-Signal Center, Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3128 USA E-mail: [email protected] IET Circuits Devices Syst., 2007, 1, (2), pp. 151 –160
oscillator (VCO) with significant nonlinearities, even though locked to the external clock with a phase-locked loop, results in a poor tracking operation [1]. Thus, VCO linearity is critical and is maintained by controlling the amplitude of the oscillation so that the effect of the selective circuit nonlinearities on the oscillation frequency is minimised. Amplitude control can be achieved with an automatic gain control circuit or more simply with a carefully designed hard limiter circuit. LC tank [3] and active-RC [4] circuits are among the most popular approaches to implement oscillators. Although for practical reasons the former approach is not preferred for implementations at relatively low-frequencies, the latter one suffers from the frequency limitation of the active elements (opamp) operating in closed loop. Operational transconductance amplifier (OTA)-based oscillators seem to be a better solution for frequencies below gigahartz due to the fact that they have high frequency poles and operate in open-loop architectures [5]. Here, a bandpass-based oscillator using the proposed multilevel hard limiter (MHL) is presented. It is shown that for the same BPF using the MHL, the linearity of the output signal is significantly improved in comparison with the traditional two-level hard limiter static characteristic. 2
Bandpass-based oscillator theory
The bandpass-based oscillator, shown in Fig. 1a, consists of a BPF as the selective element together with a hard limiter as the active element in positive feedback [5 – 7]. The conventional oscillator uses a two-level comparator as indicated in Fig. 1b, where z0 is the clamping amplitude and x0 is the threshold for the input signal, that is f (x) ¼ mx for jxj , x0 and f(x) ¼ sign(x)z0 for jxj . x0 . A sound use of the BPF in this structure allows decoupling the amplitude and frequency controls of the oscillator. That is, the oscillation amplitude is indirectly controlled by the clamping levels +z0 of the active element (comparator) while the oscillation frequency is changed by tuning the centre frequency of the BPF. The above property is due to the fact that only at the centre frequency of the BPF, the loop 151
y
(Selective element) Bandpass filter
H(s)
y = f (x )
d2 xðtÞ dxðtÞ v0 k þ NðA Þ þ v20 xðtÞ = 0 0 0 dt2 dt Q
z0
x
m
− x0
x0
Static characteristic f(⋅) (Active element) a
Fig. 1
can be written as
x
Once the steady state is achieved, the oscillation amplitude A0 can be determined from (5). 1 v0 ð6Þ A0 ’ N k0 Q
− z0 b
Bandpass-based oscillator
a Block diagram of a bandpass-based oscillator b Conventional static characteristic
gain phase becomes zero. If the gain in the feedback loop is made much larger than unity (before clamping), the feedback loop can be viewed as a sine-to-square wave converter. Owing to the presence of the BPF, which attenuates the harmonics of the square wave but the fundamental one, the describing function (DF) [8] method can be used to study the dynamic behaviour of the loop. In this technique, the input of the nonlinearity is assumed to be an undistorted sinusoidal signal, x(t) ¼ A0 sin(v0t). The higher-order harmonics present in the output signal y(t) in Fig. 1a are supposed to be filtered out sufficiently by BPF. Assuming A0 . x0 , the amplitude of the fundamental component a sin(v0t) of y(t) can be found from its Fourier series as 2 a¼
2mA0 4 1 x0 sin p A0
3 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2ffi x x þ 0 1 0 5 A0 A0
ð1Þ
where m is the slope of the nonlinear characteristic in Fig. 1b and T ¼ 2p/v0 is the period of the signal. Thus, the DF of the nonlinear block in Fig. 1b, which is the linear gain relating the amplitude of the fundamental component at the output to that of the input, can be expressed as a A0 8 2 3 > 1 x0 > > sin > > 6 7 A0 > < 2m 6 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi7 6 7 2 ¼ p 4 x0 x0 5 > > 1 þ > > A0 A0 > > : m
N ðA0 Þ ¼
A0 . x0
Observe that the oscillation frequency is equal to v0 and independent of the oscillation amplitude. Next, we propose an MHL scheme that combined with a BPF yields an enhanced total harmonic distortion (THD) of the bandpass-based oscillator waveform. 3 Proposed MHL Few have been reported in the literature regarding the optimum shape of MHL (static characteristic) block in order to reduce its output harmonic distortion. Regarding the possible nonlinearities to be used in the feedback loop of Fig. 1a, some restrictions must be made; otherwise, the study of the oscillation made by the DF methodology is not feasible. We will exclusively focus on switching characteristics, that is slopes are only zero or infinity. Furthermore, practical implementation of these elements is relatively easy. 3.1 Optimum static characteristic (multilevel hard limiter) For the generalised static characteristic in Fig. 2, the output must be bounded therefore the slope of mN should be zero, where N is the number of levels. To determine the remaining slopes in Fig. 2, the input and output of the static characteristic block are assumed to be x(t) A0 sin v0t and y(t) ’ a sin v0t, respectively. Note, because of the odd symmetry of Fig. 2, y(t) does not contain any cosine terms. To find the output amplitude a, the time ti where the input amplitude A0 exceeds the voltage level of xi must be known. 1 1 xi ; i ¼ 1; 2; . . . ; N 1 ð7Þ sin ti ¼ v0 A0
ð2Þ
y = f (x) yN y2
A0 , x0
Therefore the hard limiter function f(.) in Fig. 1a can be expressed as a linear function whose slope depends on the oscillation amplitude A0 , that is df(x)/dx ¼ y/x ’ N(A0) Hence, the DF of the whole oscillator in Fig. 1a can be related to the transfer function of the BPF (H(s)) as HðsÞ ¼
X ðsÞ 1 ¼ Y ðsÞ N ðA0 Þ
ð5Þ
ð3Þ
mN +2
m3
y1 y0
m2
− x N − x2 − x1 − x0
m3
m1 x0
m2
x1
x2 x N
x1
x2 x N
x
− y0 − y1
− y2 − yN
mN +2
− x N − x2 − x1 − x0 t2
t1 t 0
x0
x(t )
tN
Assume the BPF has the following transfer function HðsÞ ¼
s2
k0 s þ ðv0 =QÞs þ v20
where Q and v0 are the quality factor and the centre frequency of the BPF, respectively. Using (3) and (4), the time domain differential equation associated with the closed-loop block diagram of Fig. 1a 152
T + ti 2
ð4Þ
t
Fig. 2 Generalised static characteristic IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
Table 1: Pn(ri) functions for an 5 1, 3, 5 and 7 n¼1 n¼3 n¼5 n¼7
P1 (ri) ¼ r(ri)
p P3 (ri) ¼ 22r3i (1 2 r2i ) p P5 (ri) ¼ 2/3ri(3 2 4r2i ) (12 r2i (3 2 4r2i )2) p 2 2ri (1 2 2r2i ) (1 2 r2i ) 2 p P7 (ri) ¼ ri/3(1 2 2ri ) (1 2 r2i )(12 16r2i (12 2r2i ) p (1 2 r2i )) 2 (22/3ri) (3 2 4r2i ) (1 2 r2i (3 2 4r2i )2)
as an ¼ ðm1 m2 ÞPn ðr1 Þ þ ðm2 m3 ÞPn ðr2 Þ þ m3 Pn ðr3 Þ; n ¼ 1; 3; 5; 7; . . . ð16Þ
Fig. 3 Optimum static characteristic a Four-level static characteristic b Four-level MHL optimised to reduce THD
Using f(x) for different intervals of x in Fig. 2, the output amplitude a with mN ¼ 0 can be found as a¼ where
1 A0 NX ðm miþ1 Þrðri Þ 2p i¼1 i
qffiffiffiffiffiffiffiffiffiffiffiffiffi 2 1 sin ðri Þ þ ri 1 r2i ; rðri Þ ¼ p
ð8Þ
ri , 1
ð9Þ
ð10Þ
Thus, on the basis of (8) the DF of Fig. 2 can be expressed as NðA0 Þ ¼
1 1 NX ðm miþ1 Þrðri Þ 2p i¼1 i
ð11Þ
Suitable choices of r(ri) and mi can minimise the output harmonics. This is explored next. As an example, a system with N ¼ 4 will be analysed. The transfer characteristic of the analysed system is shown in Fig. 3a. The DF can be found as N ðA0 Þ ¼
1 ðm rðr Þ þ ðm2 m3 Þrðr2 Þ 2p 3 3 þ ðm1 m2 Þrðr1 ÞÞ
ð12Þ
When the circuit reaches a steady-state oscillation (i.e. s ¼ jv0), the slopes of the hard limiter characteristic of Fig. 3a can be obtained using (6) and (12). 2pv0 m3 ðrðr3 Þ rðr2 ÞÞ m2 ðrðr2 Þ rðr1 ÞÞ k Q m1 ¼ 0 ð13Þ rðr1 Þ 2pv0 m3 ðrðr3 Þ rðr2 ÞÞ m1 rðr1 Þ k0 Q m2 ¼ rðr2 Þ rðr1 Þ 2pv0 m1 rðr1 Þ m2 ðrðr2 Þ rðr1 ÞÞ k Q m3 ¼ 0 rðr3 Þ rðr2 Þ
ð14Þ
ð15Þ
Using (8) for N ¼ 3, the Fourier series coefficients an of the output of the MHL block for A0 . x2 can be calculated IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
an ¼ ðm1 m2 ÞPn ðr1 Þ þ m2 Pn ðr2 Þ;
n ¼ 1; 3; 5; 7; . . . ð17Þ
where x ri ¼ i A0
where the index n represents the odd harmonics. The Pn functions are introduced to simplify the notation for an . The Pn functions to calculate the first four odd harmonics are shown in Table 1. It is important to note that for all Pn(r1) functions in Table 1 Pn(0) ¼ 0. This property will be exploited to find the optimum slopes of the nonlinear characteristic of Fig. 2 and Fig. 3a to make null the third and the fifth harmonic components. If r2 ¼ r3 , the expression for an can be simplified to
Analysing Fig. 3a and using r2 ¼ r3 , which implies r(r2) ¼ r(r3) and x2 ¼ x3 , result in m3 ¼ 1. The same result could have been obtained from (15) knowing r(r2) ¼ r(r3) implying a denominator of zero. Our ultimate goal is to minimise the number of harmonics at the output of the MHL. The first step in doing this was setting m3 ¼ 1. To further simplify an , the remaining terms must be reduced. The second term in (17) can be made zero by choosing m2 ¼ 0, or by setting r2 ¼ 0 implying x2 ¼ 0. When m3 was set to infinity previously, x2 was made equal to x3 . Therefore x2 ¼ x3 ¼ 0 would result in m1 ¼ m2 ¼ m3 ¼ 1 and the static characteristic in Fig. 3a would result in a two-level hard limiter (comparator). From here, the scenario of m2 ¼ 0 is a better option to null the second term without compromising the characteristic of the active element. To null the remaining term in (17) there are two possibilities. First, m1 can be set to 0. However, this choice of m1 ¼ 0 results in a dead band in the characteristic of the nonlinear block and prevents the start-up of the oscillator (Fig. 3a). The second method to cancel the first term in (17) would be to set r1 ¼ 0. Having r1 ¼ 0 implies x1 ¼ 0 and r(r1) ¼ 0 which makes m1 ¼ 1. From (13), having r(r1) ¼ 0 will also result in m1 ¼ 1, verifying the result. Fig. 3b shows the resultant four-level MHL with m1 ¼ 1, m2 ¼ 0, m3 ¼ 1 and m4 ¼ 0. It is worth mentioning that in (17), the product of mi and Pi(r1) cannot be zero (mi Pi(r1) ¼ 1 0). This multiplication implies ai must always have a finite value. Although the output harmonics cannot be made zero, the THD at the output of the active element can be minimised if odd slopes (m1 , m3 , m5 , . . .) are made infinite and even slopes (m2 , m4 , m6 , . . .) are made zero. From the previous example where N ¼ 4, a more general output static characteristic can be obtained to minimise the output harmonics of the hard limiter. For even integer number of levels N it is required that N ¼ 2k, where k is an integer number. The generalised static characteristic for minimised output harmonics is shown in Fig. 4. Next 153
Fig. 4 Generalised harmonics
static
characteristic
for
minimised
the detailed analysis of finding the optimum values of xi and yi to null the third and the fifth-order harmonics at the output of the MHL block is presented. 3.2
harmonics of fc(t) can be expressed as
y1 2p þ cos a 0 ðv 0 Þ ac ðv0 Þ ¼ y2 y2 T1 y1 6p a0 ð3v0 Þ þ cos ac ð3v0 Þ ¼ y2 y2 T1 y 10p a0 ð5v0 Þ ac ð5v0 Þ ¼ y2 1 þ cos y2 T1
Time domain characterisation
Previously, the slopes of the MHL block were determined on the basis of a combination of a general analysis and a specific example. However, to implement the MHL block into a practical system, the values of xi and yi must be exactly determined. Assuming xi ¼ yi , if a sine wave with the amplitude equal to yN is applied as the input to the generalised static characteristic shown in Fig. 4, the resulting positive half wave is as shown in Fig. 5. To obtain the values of xi and yi , a Fourier analysis must be performed on the output of the MHL (Fig. 5). To begin, a simple comparator will be used as the limiter building block. The reference level of this block will be taken as zero such that the generated output will be a square waveform. The output of this comparator with a reference of zero will be denoted f0(t). There are two methods which may be used to obtain the output waveform shown in Fig. 5. The first implementation focuses on using the sum of the outputs of 2N 2 1 comparator’s with different references of +yi . However, if this method is used, besides the increased power consumption and complexity, the exact times (ti) where the output’s are summed will vary based on fluctuations in the reference levels of the different comparator’s. These fluctuations will produce an unwanted output waveform which could cause the system not to operate as desired. The second implementation to obtain the MHL output as shown in Fig. 5 is based on using only one comparator with a reference voltage of zero. To illustrate this methodology, again we use the previous example of a four-level static characteristic. The output of this block for a sinusoidal input is shown in Fig. 6. As depicted in Fig. 7, the output of this block fc(t) can be obtained by summing f0(t) (ideal comparator output) together with two other properly scaled and time-shifted versions of f0(t). fc ðtÞ ¼ y1 f0 ðtÞ þ
ð19Þ ð20Þ ð21Þ
where T1 ¼ T/t1 and a0(nv0) and ac(nv0), n ¼ 1, 3 and 5, are the coefficients of the Fourier series of f0(t) and fc(t), respectively. A careful examination of (20) and (21) shows that in the case of a linear relation between y1 and y2 , a proper value of T1 can make the two terms inside the brackets zero. To find this proper value of T1 , the terms of cos(ip/T1) for i ¼ 2, 6 and 10 as functions of T1 are plotted in Fig. 8. In order to simultaneously null the third and the fifth-order harmonics, it is required that p T1 ¼ 8 which yields cos(6p/T1) ¼ z cos(10p/T1) ¼ 2 2/2. Thus, to make (20) and (21) zero, y1 and y2 have to be related as y2 pffiffiffi ¼ 2 y1
ð22Þ
p Note that for y2/y1 ¼ 2 and tp0 ¼ T/8, from (19) it can be concluded that ac(v0) ¼ ( y2/ 2) a0(v0), which means that the oscillation amplitude can be tuned by changing y2 while maintaining the condition described by (22).
3.3
General case: multilevel hard limiter
From the previous example, a general expression for the output f(t) of the MHL block in Fig. 5 can be derived by
y2 y T f0 ðt t1 Þ 2 f0 t t1 ð18Þ 2 2 2
where y1 and y2 are amplitudes of the stairs of waveform of Fig. 6. The sum operation in Fig. 7 is a mathematical sum and it is just a conceptual diagram to construct fc(t). However, this concept has been used in Section 4.1 in implementing the MHL block in current mode which makes the sum operation feasible. Note that due to the symmetry of fc(t), the even harmonics of its Fourier series are zero. The first odd 154
Fig. 5 Output of MHL for N slopes and a sine wave input
Fig. 6 Input (thin line) and output (thick line) of the nonlinear characteristic of Fig. 3b IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
Fig. 7 Decomposition of the output of the MHL block
induction as fc ðtÞ ¼ f0 ðtÞ þ
1 1 NX T ti yi f0 ðt ti Þ yi f0 t ð23Þ 2 i¼1 2
Thus, the Fourier series of the output signal fc(t) can be found as N 1 X ac ðnv0 Þ ¼ a0 ðnv0 Þ 1 þ yi ð1 ð1Þn Þ i¼1
cosðv0 ti Þ
;
n ¼ 3; 5; 7; . . .
ð24Þ
where ac(nv0) and a0(nv0) are the Fourier series coefficients of fc(t) and f0(t), respectively. It can be demonstrated that for specific values of k and n, the following expressions of ti and yi make (24) zero. T
i ¼ 1; 2; 3; . . . p yi ¼ cos Kþ1 i ; i ¼ 1; 2; 3; . . . 2 ti ¼
2Kþ2
i;
ð25Þ ð26Þ
The above fact has been visualised in Fig. 9 for k ¼ 1, 2, 4 and 8 and n ¼ f/f0 . In the case of four-level MHL, that is k ¼ 2 in Fig. 9, the absence of the third and the fifth-order harmonics in the frequency spectrum of the output signal of the proposed MHL has a significant effect on increasing the spectrum purity of
Fig. 8 Plots of cos(ip/T1) for i ¼ 2, 6 and 10 against T1 IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
the sinusoidal output without any extra effort to implement a significantly high-Q BPF. 3.4
Non-ideal effects
In implementation of fc(t), based on (23), the main sources of non-idealities are finite slopes (mi) and inaccuracy in the switching time ti . Considering the above effects, the output waveform of the previously studied four-level MHL block in Fig. 3 can be modelled as the waveform shown in Fig. 10. In this figure, the deviation of the slopes from their ideal (infinity) values correspond, to the deviation of t0 and t1 from their ideal values, zero and T/8, respectively. The nth Fourier series coefficient, taking into account these non-idealities, can be calculated as a^ c ðnv0 Þ ¼
ð1 ð1Þn Þsincðnv0 t0 =2Þ np nv t 0 0 þ ðy2 y1 Þ y1 cos 2 Dt1 cosðnv0 t1 þ 2
ð27Þ
where Dt1 ¼ ( y2 2 y1)/m3 and t0 ¼ y1/m1 . Note that for Dt1 ¼ 0 and t0 ¼ 0, (27) becomes (24). The overall THD of this waveform as well as the third and
Fig. 9 Frequency spectrum of the MHL (limiter) with different possible levels 155
Fig. 10
Non-ideal effects due to finite slopes of Fig. 3
Fig. 11 THD of the proposed four-level and the two-level (comparator) MHLs as a function of t0 and t1 in Fig. 6
the fifth-order harmonic distortions (HD3 and HD5) are shown in Figs. 11 and 12, respectively. The horizontal axes correspond to t0 and t1 and the vertical axis corresponds to distortion. Note that for values of t0 = 0 and t1 = T/8, the HD3 and the HD5 grew drastically from zero while the overall THD improves. The improvement in the THD is expected due to finite slopes, but it is not of interest since the higher harmonics of the output is attenuated by the BPF anyway. However, as Figs. 12a and 12b show, even with deviation of t0 and t1 from their ideal values, the HD3 and the HD5 of the proposed MHL are considerably below their corresponding values (Fig. 12c) for the conventional two-level hard limiter. Another source of non-ideality in implementation of fc(t) p is the deviation of y2/y1 from its ideal value of 2. The HD3 of fc(t) as a function of this deviation has been plotted in Fig. 13. For the purpose of comparison, the behaviour of HD3 as a function of t0 has been plotted in the same figure as well. The variations in y2/y1 and t0 are normalised and the new variable is pcalled Knorm so that Knorm ¼ 0 corresponds to y2/y1 ¼ 2 and t0 ¼ T/8. In other words, the horizontal axis in Fig. 13 represents the variations of both y2/y1 and t0 . Observe that for any Knorm = 0, the net change in HD3 due to t0 is greater than the corresponding change due to y2/y1 . 4
Circuit implementation
Fig. 14 shows the overall block diagram of the fabricated chip. A conventional two-level hard limiter (comparator)
Fig. 12
Third and fifth-order harmonic distortions
a HD3 as a function of t0 and t1 for the proposed four-level MHL b HD5 as a function of t0 and t1 for the proposed four-level MHL c HD3 and HD5 for two-level (comparator) MHL 156
IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
is included in the design to compare its performance with the proposed MHL block. A linearised transconductance buffer [9] is employed to monitor the output signal. 4.1
BPF design
To increase the linearity of the oscillator, besides increasing the Q, the nonlinearities associated with the BPF need to be minimised. Hence, a BPF using the linearised pseudodifferential OTA [10] has been designed. Fig. 15 shows the block diagram of the two-integrator loop biquad Gm-C filter. This topology is often preferred with respect to other versions since an additional low pass output is available. Furthermore, it has the advantage of allowing the control of the common-mode voltage at both integrator outputs. In addition, a minimum sensitivity of the quality factor with respect to capacitance mismatch is achieved by choosing C1 ¼ C2 [11]. Fig. 13 HD3 as a function of y2/y1 (solid line) and t0 (dashed lined)
Fig. 14 Overall block diagram of the oscillator for testing purposes
Fig. 15 Biquad Gm-C BPF
4.2
MHL static characteristic implementation
The main challenge in implementing the nonlinear characteristic of the MHL in Fig. 3b is the accuracy of the comparison of the sinusoidal input with zero and x1 . This problem can be avoided by emulating the performance of the static characteristic based on the decomposition of the waveforms in square waves as shown in Fig. 7. In this technique, the output signal of the BPF is only compared with zero and two independent delay lines generate the other two timeshifted waveforms. Its implementation is shown in Fig. 16. This implementation requires three tasks of comparison, time delay and digital to analogue (DAC) conversion. The input comparator compares the input signal with ground to generate the base square wave f0(t) in Fig. 7. Two separate delay lines generate f0(t 2 t1) and f0(t 2 (T/2 2 t1)). By having a well-characterised delay cell and using two decoders, it is possible to tune the total delay of the delay lines by configuring the delay cells in each line. In this technique, as shown in Fig. 16, each delay cell can be bypassed using a switch whose control signal is one of the output bits of a thermometer decoder. Thus, when the input word of the decoder is changed by one bit, one delay cell is configured in the delay chain. However, for simplicity, these decoders are not incorporated in our design. Instead, two separate delay lines with three and 10 delay cells are used to delay f0(t) by t1 and T/2 2 t1 , respectively. The propagation delay time of each delay cell, shown in Fig. 17, is directly
Fig. 16 Implementation of the proposed MHL block IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
157
Fig. 17
Schematic diagram of an NP-voltage cascade inverter
proportional to Vdd [12] and the load CL. 1 tdelay ¼ ðtpHL þ tpLH Þ 2 ¼
CL VDD 1 1 þ 2 kp Vp2 kn Vn2
Fig. 18
5 ! ð28Þ
where kp ¼ 0.5 mnCox(W/L)n and kn ¼ 0.5 mpCox(W/L)p and Vp and Vn are the bias voltages of the p-type and n-type current sources in Fig. 17, respectively. Thus, by using the delay cell shown in Fig. 17 the total delay of each line can be tuned by changing the Vdd of the corresponding delay cells. The square wave f0(t) and its delayed versions are controlling two groups of switches, Ms1–Ms3 and Ms4–Ms6, which conceptually form a 3-bit DAC circuit. Transistors M1–M9 provide the reference currents for the switches Ms1–Ms6. The three switches of Ms1–Ms3 generate the positive portion of the composite pulse fc(t) and its negative portion is generated by Ms4–Ms6. The currents of these two groups of switches after being summed up at the output nodes, across fc(t), are converted to voltage using two matched resistors R ¼ p 10 kV. To implement the 2 ratio between the two levels of the output voltage (22), the currents following through the switches have to be properly scaled with respect to IREF ¼ 20 mA which result in the following relations between the current sources in Fig. 16 W W W W W ¼ ¼ and ¼ L 1 L 3 L 5 L 6 L 8 W W W ¼ ¼ 0:7 and L 2 L 4 L 1 W W W ¼ ¼ 0:7 L 7 L 9 L 6
ð29Þ
Experimental results
The oscillator chip prototype was fabricated in TSMC 0.35 mm CMOS technology through and thanks to MOSIS. The micrograph is shown in Fig. 19. The die size occupies a silicon area of about 3.15 mm2. Fig. 20 shows the measured frequency response of the BPF which shows a centre frequency and quality factor of around 10.6 MHz and 20, respectively. A linear buffer, shown in Fig. 21, is used at the output of the BPF to convert the internal voltage mode signals to current [9]. The linearity of the buffer is adjustable through Ibias2 . To characterise the contribution of the BPF on the overall HD3 of the oscillator, an IM3 measurement has been carried on the cascade combination of the BPF and the buffer and the result is shown in Fig. 22. The two input tones are at frequencies of 10.65 and 10.75 MHz with equal amplitudes of 0.5 Vpp. The best obtained IM3 of the buffer is 263 dBm. From Fig. 14, by closing the loop of the filter and the nonlinear block, the circuit starts oscillating and its output spectrum for both cases of the conventional comparator and the proposed MHL are shown in Figs. 23 and 24, respectively. Note that to have a fair comparison between the two scenarios, the reference current IREF in Fig. 16 has been adjusted so that the oscillation amplitudes of both cases are the same. Comparing these results shows a 224 dB improvement in the reduction of the third-order harmonic distortion at the output of the filter in the case of the proposed MHL. Observe that the fifth-order harmonic is reduced by several decibels in Fig. 24, but its improvement is not as visible as the third-order one due to the attenuation of
ð30Þ
To compensate for the effect of the process variations on the absolute values of the delays, the delay networks are made configurable using two independent 3-bit words. Moreover, reducing the mismatch between delay cells by careful layout design can improve the accuracy of the delay line. However, a more precise implementation of the delay line can be obtained by using a delay locked-loop (DLL) [13] at the cost of more complexity and increased power consumption. The input comparator [14], required in Fig. 16, is depicted in Fig. 18. It is a synchronous high-speed comparator consisting of a cascade of a pre-amplifier, latch, self-biased differential amplifier and output driver. The quiescent current of the comparator is 90 mA. 158
Two stage opamp used as the comparator [13]
Fig. 19
Layout of the chip IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
Fig. 20 Frequency response of the BPF
Fig. 23 Output spectrum of the oscillator with a conventional two-level comparator
Fig. 21 Output buffer schematic
the filter. However, the seventh-order harmonics are comparable which is consistent with the analytical results obtained in (24). It is important to mention that the measured result in the case of the proposed MHL block is the best obtained result through adjusting the delay cells in Fig. 16 which tunes the delay time of t1 in Fig. 6. This has been achieved by changing the digital word controlling the delay cells in Fig. 16 in order to maintain the requirement of T1 ¼ T/t1 ¼ 8. If we assume that the first seven harmonics are the main harmonics at the output, the overall THD of the measured frequency spectra of Figs. 23 and 24 can be calculated as 238.63 and 253.16 dB, respectively. These results show that more than 14 dB improvement in the THD can be achieved by using the proposed MHL block. Fig. 25 shows the
Fig. 24 Output spectrum of the oscillator with the proposed multilevel comparator
theoretical predictions of THD against different quality factors of the BPF for both the comparator and the MHL block. This figure shows that, for the measured quality factor of 15, the experimental results are in good agreement with the theory. The performance of the VCO built using the proposed MHL block against some of the previously published works has been summarised in Table 2. The key advantage of using the proposed MHL
Fig. 25 Fig. 22 IM3 measurement results for the buffer IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
THD of the oscillator as a function of the quality factor
Solid lines: analytical; circles: experimental 159
Table 2: Summary of performance f0 , MHz
Q 8
Area mm2
Technology
Pdiss, mW
THD, dB 233
Rodriguez-Vazquez et al. [5]
7.76
3 mm CMOS
–
–
Pavan and Tsividis [7]
0.0135
20
Discrete
–
–
238
This work
10.7
15
0.35 mm CMOS
3.15
132
253
the bandpass filter. In our case, the required quality factors were 5 and 30 to yield the same THD of 247 dB. The proposed MHL has the potential to be applied to other applications requiring switching [15]. 7
Acknowledgment
The authors thank Jason Lee Wardlaw for his help in editing the paper. 8
Fig. 26 Comparison of HD3 as a function of the delay time deviation
block is the significant increase in the linearity of the output signal with a moderated value of Q. Fig. 26 shows the effect of the delay cells on the HD3 of the proposed architecture in both simulation and measurement cases. The horizontal axis represents the percentage of the delay with respect to the fundamental period T. To explore the effect of using a DLL to generate the delayed pulses, a system level simulation using SIMULINK has been carried out and the results are shown in Fig. 26 as well. In the DLL-based implementation, for a small range of the delay introduced to each cell, the composite waveform fc(t) generated by the DLL remains insensitive to the delays which yield a nearly constant HD3. As it can be seen from this figure, there is only one optimum delay for which the measured HD3 is reduced and this value is around 1/8 of the fundamental period T. Deviation from this optimal value for delay results in a degraded HD3 as it has been verified by the measurement results. 6
Conclusions
A bandpass-based oscillator using an MHL has been presented. The proposed MHL used in a bandpass-based oscillator provides an improvement of 14 dB in THD with respect to the conventional two-level hard limiter. Furthermore, to obtain the same THD for an oscillator using the proposed MHL and the conventional limiter, the proposed one will require a much lower quality factor of
160
References
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IET Circuits Devices Syst., Vol. 1, No. 2, April 2007
