Low-voltage Analog CMOS filter design. - Semantic Scholar
Low-voltage analog CMOS filter design. M. Steyaert, J. Crols, S. Gogaert, W.Sansen K.U.Leuven, ESAT-MICAS K a r d i ~ aMercierlaan l 94,3001 Heverlee, Belgium Abstract - Design techniques for low-voltage analog TUters In CMOS technologies are discussed. The use of OTA-C implementation techniques towards low power supply voltages (3 V and below) requires special source degenerationand input signal folding techniques. Firstly, design techniques to achieve Pull CMOS continuous-time filters with low distortlon (Total harmonic distortion c -50 dB) and low power supply voltages (3 V) are discussed. The use of switched-capacitortechniques at extremely low voltages (1.5 V) requjre extra care for the switches in the circuit. Special design techniques, such as voltage multlpliers for the clock drivers and single transistor switches, are analyzed to achieve the low power supply speciflcatlons.
I. INTRODUCTION
The demand for system mobility, greater packing densities, smaller size and lower power drain has result in a demand of analog signal processing circuits operating power supply voltages of 3 V and less. Therefore design techniques for low-voltage analog filters in CMOS technologies are discussed in this paper. The implementation of analog filters can be realized with several techniques, such as switchedcapacitor (SC) and OTA-C techniques. The design of full CMOS continuous-time filters can be realized with MOSFET-C or OTA-C techniques. However to achieve low power supply voltages and to achieve at the same time low-distortion specifications, the OTA-C technique is usually preferred. The main problem in these OTA-C filters is the design of a low-voltage low-distortion OTA. A full CMOS low-distomon structure, based on source degeneration and input signal folding techniques, will be discussed. The design of switched-capacitor filters is still very attractive due to the high filter accuracy and low power consumption. However for extremely low voltages problems can occur for the switches. Design techniques and trade-offs of single device switches and voltage multipliers will be overviewed.
The THD is the RMS value of the contribution of all the harmonics. The THD of a differential pair can easily be calculated as I
111
HD2=0,HD3=i. 'IN 32 (vm-vr)*. Because of the differential structure the second harmonic distortion (HD2) is a function of mismatches between the transistors. By careful lay-out this component can be made smaller than -65 dB in CMOS technologies. To realise however a Third Harmonic Distortion (HD3) of -60 dB at a differential input voltage of 0.5 V, the V,, - V , should be 3 V which requires high (f5 V) supply voltages.
B.Source degenerated topologies A technique that allows natural linearisation due to its intrinsic feedback is the source degeneration technique. Other important advantages of this structure are that is exhibits excess lead phase in its phase response and that this technique is lowly sensitive to transistor mismatches. An ordinary resistor can be used for this purpose. But this approach requires large resistors which increases both the silicon area and the parasitic capacitance. Those resistors have to be driven by large transconductances, then the power consumption increases as well. The topology by Krummenacher et al. [2], shown in Fig. la, which uses transistors biased in triode region is basically a source degenerated structure for small signals with an additional internal mechanism which increases its transconductance for large signals. This last fact increases the linear range of this topology in the order of a factor 2.
mr I
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PI
102
1 VDO
11. LOW VOLTAGE OTA-C TECHNIQUES
A . Limitations of easy structures
The major limitation in ordinary OTA-structures is the noise generated by the intrinsic nonlinearities of the electronic devices. Due to the nonlinear nature of the relationship between the input signal and the output signals, several unwanted signals are generated. These signals, in case of a sinusoidal input, are at multiple frequencies of the incoming signal frequency. These signals are called the harmonic distortions of the input signal [l]. This kind of noise is accounted by the Total Harmonic Distortion (THD).
Fig. 1. CMOS source degenerated topologies using a ) transistors in triode region; b) saturated transistors.
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Another approach using source degeneration was proposed by Torrance et al. [3]. In this technique, the resistors used for the source degeneration are simulated by saturated transistors with their drab connected to their gate. In this case, the factor n corresponds to the number of additional pairs used. This topology is shown in Fig. l b for the use of 2 additional sections.Because the input voltage for each section is Vhb,the transconductance is also reduced by the same factor n. The third harmonic distortion, the most important one,is decreased by a factor 'n . Using both techniques, the design of OTAs with HD3 lower than -60 dB is feasible [4], [ 5 ] . Fig. 2 shows a measurement of the THD of the realised OTA-C filter at 3 V supply voltage with an input voltage of 0.6 Vptp at a frequency of 1OkHz. However, not only the harmonic distortion reduces but the linear range for the input signals is almost twice that for the ordinary differentialpair. The major disadvantages of this structure are the additional transistors and the increment of the power consumption. The Evst drawback is not really important but it represents some additional silicon area. The second shortcoming has been overcome using a cross coupled technique as presented in Fig. 3. The transconductance is increased with K , = 1+ 1/(1+ p, /&). When we implement the same transconductance as before, the TKD is reduced by a factor K:. This OTA-structure is used in a OTA-C filter at 3 V supply voltage. The measured noise was 110 p V w s and the results of the THO are displayed in Fig. 4. O T
0
I"\
e,,
0
01
01
01
OA
1
.*IMgNplp)
Fig. 4.THD in function of the inputswing.
C . A low distortion approachfor the common mode loop
As mentioned above, the linearity of the system can be further increased by implementing a fully differential signal path. In that case, because of increased symmetry, all common mode signals and even order distortions cancel out, except for the influence of component mismatches. A Fully differential signal path leads to lower distortion, higher Common Mode Rejection Ratio (CMRR) and higher Power Supply Rejection Ratio (PSRR).Differential structures have one major disadvantage however. Because the signal is no longer referred to the ground, the operating point of the amplifier cannot be stabilised with the differential feedback loop. A Common Mode Feedback Loop (CMFB) has to be added as well. This loop can become quite complicated because it should reduce the common mode signals over a wide frequency range without affecting the differential performance of the OTA. With the presented OTA a satisfying CMFB can easily be realised. To understand the principle, it has to be mentioned that in high order filters, several OTA-C integrator stages are placed in series to realise the filter structure as shown in Fig. 5. The problem is to control and to set the common output voltage of the OTAs (OTA1 in Fig. 5). This can easily be arranged because in the low distortion OTA structure (see Fig. 3) an extra terminal is available: the common mode voltage at the input of an OTA can be sensed at the Vcm-terminal. The CMFB for the OTAl can thus be generated from the Vcm of the next OTA (OTA2 in Fig. 5 ) . The only extra component required is a simple opamp to regulate the measwed common mode voltage to the reference voltage (in this case the ground). Low distortion of the common mode detector is automatically guaranteed because the common mode voltage is sensed by the low distortion input stage of the OTA.
@=-
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Fig. 2.Total harmonic distortion V , = 0.6 Vptp.
T+
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VCMFB
VCMFB
VSS
Fig. 3. Cross-coupling to reduce power consumption.
Fig. 5. Block diagram of the CMFB system.
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III. LOW VOLTAGE SC TECHNIQUES A . Concepts OTA-C filters are not very well suited for use at extremely low power supply voltages. The distortion of the OTA's used in such a filter rapidly increases when the power supply voltage is decreased to 2 V and lower. For these applications the use of switched-capacitor filters is much more attractive. Fig. 6 shows a switched-capacitor inverting integrator, the basic building block of a switched-capacitor filter. The consequence of this structure is that the OTAs used in switched-capacitor filters do not require an input voltage swing because the input nodes are kept at the reference level at a l l times. OTAs for low voltage switchedcapacitor filters are therefore much easier to design than those for low voltage OTA-C filters. A second advantage of the feedback system used in switched-capacitor filters is that the distortion of the filter is not directly related to the distortion of the OTA's. As long as the OTAs are used within their output voltage swing the distortion is limited and the feedback loop will correct this distortion. Switchedcapacitor filters have a total harmonic distortion of about -70dB for the full swing of the used OTAs, even at extremely low power supply voltages. In an extremely low voltage switched-capacitor filter the switches are the biggest problem. Typically these switches are complementary driven nMOS and PMOS transistors. The problem is that these devices do not switch on unless the voltage between gate and source is higher than the Vr . The formula for the conductivity of these switches is (we will use a 2 pm n-well CMOS process with Vr = fo.9 V for all examples discussed in this text) : ,g
F [ v ~ -vrw
= KP,
-V,
- 'Y.
(4-
-
Fig. 7 displays the conductivity of the switch when minimum size transistors are used. In this curve there is a minimal conductivity at Vu - V,,, (3.8 V at Vu = 5 V). In Fig. 8 this minimum conductivity is plotted versus the power supply as a maximum resistivity. When V,, is reduced and
Iv, I
there is a point at which the resistivity is r e a h v,, + rnfinte because there is a zone in which neither of the two transistor is switched on. From this point on it is useless to use a complementary switch. In this case it is preferable to use a single nMOS switch because it has a three times lower resistivity than a PMOS switch. When a single transistor switch is used, tbe signal swing that can be applied is limited. In the case of single nMOS switches switch 2,3 and 4 limit the signal swing to 2(Vu - V , -V,,,,). Switch 1 limits it however to V , -Vrn - V - . This means that there is not much swing left when an extremely low voltage power supply is used (0.3 V when V,, = 1.5 V). This swing can only be used when the nMOS switch is bigger than minimum size (e.g. W / L= 10) because the switch is used in its low conductivity region. The consequence of using big switches is high clock feed through. This effect is however limited because low voltage clock signals are used. 025
e
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0 1
m)]
005
For switches 2,3 and 4 in Fig. 6 the lowest conductivity appears when the source voltage is equal to the reference level. For switch 1 the worst case occurs when for the nMOS the source voltage is equal to the maximum input signal level or when for the PMOS the source voltage is equal to the minimum input signal level.
-
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Fig. 7. Conductivity of a complementaryswitch in function of the signal voltage level. IS0
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Fig. 8. Maximum resistivity of a complementary switch in function of the power supply voltage
Fig. 6. Switchedcapacitor invelting integrator.
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B.Implementation techniques The easiest way to improve the obtainable voltage swing
is using a special process tuned for the implementation of extremely low voltage switched-capacitor filters. In [6] a CMOS process is used which has an extra nMOS transistor with V , = 0.2 V. This transistor is used as switch together with a normal PMOS transistor ( IVT,l = 0.85 V). In this way a voltage swing of 1 V is obtained with V , = 1.4 V. To realise this an extra mask and an extra implantation is necessary. The main disadvantage of this technique is the very high cost for developing a special process for only one kind of application. For this reason it can not be considered as a feasible solution. Another disadvantage of the nMOS switch-transistor used here is that it can not be tumed off completely anymore. The result is distortion and a deformation of the filter transfer characteristic. The most often used technique to improve the voltage swing is on chip clock signal voltage multiplication [7], [8], [9]. In these realisations a technique is used which is derived from the programming system in EEPROM's [lo], [ l l ] . A system of charching and discharching capacitances which are connected to each other with diodes is used to make a higher voltage ( V < , ) .This voltage is not used as voltage supply because the power consumption would be too high and the necess'uy chip area for this voltage multiplier would be too big. Only the clock signals for the switches run on this voltage. The necessary condition for a low voltage switchedcapacitor filter using complementary switches is V , > V , +IV,I. In the first implementation technique this is solved by making one of the V , ' s smaller. In the second it is solved by replacing V , with a special Vc, which can be made higher. The necessary condition for a switchedcapacitor filter using single nMOS switches is V , > V _ + V , + V h , (V, is the signal voltage swing in Volts peak-to-peak). Now a third implementation technique is introduced, called switched-buffer, which allows a large voltage swing at extremely low voltages without needmg a special process or a voltage multiplier. It is based on the fact that the limitation V , > V w + V , + Vdm holds only for switch 1. By eliminating switch 1 and replacing it by a switched buffer the voltage swing can be doubled. In Fig. 9 a switched-buffer inverting integrator is shown. Switch 1 is replaced by a buffer which is turned on and off by @, .This is done by switching the current sources in the buffer on and off. The main design consideration for this buffer is that it must be able to handle a large input voltage swing. This means that it is necessary to use a rail-to-rail amplifier. At these low voltages this can be done with a dual differential inputpair [12]. The disadvantage of this technique is that it needs switch transistors which are larger than minimum size. The switched buffers increase the power consumption and the chip area.
Fig. 9. Switched-buffer inverting integrator
IV. REFERENCES. P. R. Gray and R. G. Meyer, "Analysis and design of analog integrated circuits," John Willey & Sons. Singapore, 1984. F. Krummenacher and N. Joehl. "A 4 MHz CMOS continuous-time filter with on chip automatic tuning," IEEE J. of Solid-state Circuits, Vol. SC-23. pp 750-757, June 1988. R. R. Torrance, T. R. Viswanathan and J. V. Hanson, "CMOS voltage to current transducers," E E E Trans. on Circuits and Systems. Vol. Cas-32, pp 1097-1 104, NOV.1985. J. Silva-Martinez, M. Stcyaert and W. Sanscn, "A high-frequency large-signal very low-distortion transconductor." IEEE Proc.ESSCIR90. Orenoble France, pp169-172, Sept. 1990. J. Silva-Martinez, M. Steyaert and W. Sansen, "A large-signal very low-distortion transconductor for high-frequency continuous-time filters," IEEE J. of Solid-state Circuits, Vol. SC-26. pp 946-955, July 1991. r. Adachi, A. Ishinawa, A. Barlow and K. Takasuka, ' A 1.4 V switched capacitor filter," Proc. CICC (Bmton). pp.8.2.1-8.2.4, May 1990. R. Castello and L. Tomasini, "1.5-VHigh-performance SC filters in BiCMOS technology," IEEE J. of Solid-State Circuits, Vol. SC-26, no. 7, pp.930-936, July 1991. F. Calias, F. H. Salchi and D. Girard, "A set of four I C s in CMOS technology for a programmable hearing aid," IEEE J. of Solid-state Circuits, vol. SC-20, no. 2, pp.301-312, April 1989. R. Becker and J. Mulder. "SIGFRED: A low-power DTMF and signalling frequency detector," Roc.ESSCIRC (Grcnoble). pp.5-8.
%
~
~
~
~
;
"On-chip high-voltage generation in MNOS integrated circuits using an im roved voltage multiplier technique," IEEE J. of Solid-State Circuits.$ol. SC-11, pp.374-378. June 1978. B. Gerber, J. C. Martin and J. Fellrath, "A 1.5 V single-supply onetransistor CMOS EEPROM," lEEE J. of Solid-State Circuits, vol. SC-16, no. 3, p.195, 1981. J. H. Huijsing and D. Lincbarger, "Low-voltage operational amplifier with rail-to-rail input and output ranges," IEEE J. of Solid-State Circuits. vol. SC-20, no. 6. pp.1144-1150. Dec. 1985.
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I. INTRODUCTION
The demand for system mobility, greater packing densities, smaller size and lower power drain has result in a demand of analog signal processing circuits operating power supply voltages of 3 V and less. Therefore design techniques for low-voltage analog filters in CMOS technologies are discussed in this paper. The implementation of analog filters can be realized with several techniques, such as switchedcapacitor (SC) and OTA-C techniques. The design of full CMOS continuous-time filters can be realized with MOSFET-C or OTA-C techniques. However to achieve low power supply voltages and to achieve at the same time low-distortion specifications, the OTA-C technique is usually preferred. The main problem in these OTA-C filters is the design of a low-voltage low-distortion OTA. A full CMOS low-distomon structure, based on source degeneration and input signal folding techniques, will be discussed. The design of switched-capacitor filters is still very attractive due to the high filter accuracy and low power consumption. However for extremely low voltages problems can occur for the switches. Design techniques and trade-offs of single device switches and voltage multipliers will be overviewed.
The THD is the RMS value of the contribution of all the harmonics. The THD of a differential pair can easily be calculated as I
111
HD2=0,HD3=i. 'IN 32 (vm-vr)*. Because of the differential structure the second harmonic distortion (HD2) is a function of mismatches between the transistors. By careful lay-out this component can be made smaller than -65 dB in CMOS technologies. To realise however a Third Harmonic Distortion (HD3) of -60 dB at a differential input voltage of 0.5 V, the V,, - V , should be 3 V which requires high (f5 V) supply voltages.
B.Source degenerated topologies A technique that allows natural linearisation due to its intrinsic feedback is the source degeneration technique. Other important advantages of this structure are that is exhibits excess lead phase in its phase response and that this technique is lowly sensitive to transistor mismatches. An ordinary resistor can be used for this purpose. But this approach requires large resistors which increases both the silicon area and the parasitic capacitance. Those resistors have to be driven by large transconductances, then the power consumption increases as well. The topology by Krummenacher et al. [2], shown in Fig. la, which uses transistors biased in triode region is basically a source degenerated structure for small signals with an additional internal mechanism which increases its transconductance for large signals. This last fact increases the linear range of this topology in the order of a factor 2.
mr I
P
PI
102
1 VDO
11. LOW VOLTAGE OTA-C TECHNIQUES
A . Limitations of easy structures
The major limitation in ordinary OTA-structures is the noise generated by the intrinsic nonlinearities of the electronic devices. Due to the nonlinear nature of the relationship between the input signal and the output signals, several unwanted signals are generated. These signals, in case of a sinusoidal input, are at multiple frequencies of the incoming signal frequency. These signals are called the harmonic distortions of the input signal [l]. This kind of noise is accounted by the Total Harmonic Distortion (THD).
Fig. 1. CMOS source degenerated topologies using a ) transistors in triode region; b) saturated transistors.
0-7803-1254-6193$03.00 0 1993 IEEE 1447
Authorized licensed use limited to: MIT Libraries. Downloaded on July 2, 2009 at 17:50 from IEEE Xplore. Restrictions apply.
Another approach using source degeneration was proposed by Torrance et al. [3]. In this technique, the resistors used for the source degeneration are simulated by saturated transistors with their drab connected to their gate. In this case, the factor n corresponds to the number of additional pairs used. This topology is shown in Fig. l b for the use of 2 additional sections.Because the input voltage for each section is Vhb,the transconductance is also reduced by the same factor n. The third harmonic distortion, the most important one,is decreased by a factor 'n . Using both techniques, the design of OTAs with HD3 lower than -60 dB is feasible [4], [ 5 ] . Fig. 2 shows a measurement of the THD of the realised OTA-C filter at 3 V supply voltage with an input voltage of 0.6 Vptp at a frequency of 1OkHz. However, not only the harmonic distortion reduces but the linear range for the input signals is almost twice that for the ordinary differentialpair. The major disadvantages of this structure are the additional transistors and the increment of the power consumption. The Evst drawback is not really important but it represents some additional silicon area. The second shortcoming has been overcome using a cross coupled technique as presented in Fig. 3. The transconductance is increased with K , = 1+ 1/(1+ p, /&). When we implement the same transconductance as before, the TKD is reduced by a factor K:. This OTA-structure is used in a OTA-C filter at 3 V supply voltage. The measured noise was 110 p V w s and the results of the THO are displayed in Fig. 4. O T
0
I"\
e,,
0
01
01
01
OA
1
.*IMgNplp)
Fig. 4.THD in function of the inputswing.
C . A low distortion approachfor the common mode loop
As mentioned above, the linearity of the system can be further increased by implementing a fully differential signal path. In that case, because of increased symmetry, all common mode signals and even order distortions cancel out, except for the influence of component mismatches. A Fully differential signal path leads to lower distortion, higher Common Mode Rejection Ratio (CMRR) and higher Power Supply Rejection Ratio (PSRR).Differential structures have one major disadvantage however. Because the signal is no longer referred to the ground, the operating point of the amplifier cannot be stabilised with the differential feedback loop. A Common Mode Feedback Loop (CMFB) has to be added as well. This loop can become quite complicated because it should reduce the common mode signals over a wide frequency range without affecting the differential performance of the OTA. With the presented OTA a satisfying CMFB can easily be realised. To understand the principle, it has to be mentioned that in high order filters, several OTA-C integrator stages are placed in series to realise the filter structure as shown in Fig. 5. The problem is to control and to set the common output voltage of the OTAs (OTA1 in Fig. 5). This can easily be arranged because in the low distortion OTA structure (see Fig. 3) an extra terminal is available: the common mode voltage at the input of an OTA can be sensed at the Vcm-terminal. The CMFB for the OTAl can thus be generated from the Vcm of the next OTA (OTA2 in Fig. 5 ) . The only extra component required is a simple opamp to regulate the measwed common mode voltage to the reference voltage (in this case the ground). Low distortion of the common mode detector is automatically guaranteed because the common mode voltage is sensed by the low distortion input stage of the OTA.
@=-
laQJzamxrmaacasamaaaxr7ma,eam90000larm h.gwncy (Iw
Fig. 2.Total harmonic distortion V , = 0.6 Vptp.
T+
2-2SVC" A
VCMFB
VCMFB
VSS
Fig. 3. Cross-coupling to reduce power consumption.
Fig. 5. Block diagram of the CMFB system.
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III. LOW VOLTAGE SC TECHNIQUES A . Concepts OTA-C filters are not very well suited for use at extremely low power supply voltages. The distortion of the OTA's used in such a filter rapidly increases when the power supply voltage is decreased to 2 V and lower. For these applications the use of switched-capacitor filters is much more attractive. Fig. 6 shows a switched-capacitor inverting integrator, the basic building block of a switched-capacitor filter. The consequence of this structure is that the OTAs used in switched-capacitor filters do not require an input voltage swing because the input nodes are kept at the reference level at a l l times. OTAs for low voltage switchedcapacitor filters are therefore much easier to design than those for low voltage OTA-C filters. A second advantage of the feedback system used in switched-capacitor filters is that the distortion of the filter is not directly related to the distortion of the OTA's. As long as the OTAs are used within their output voltage swing the distortion is limited and the feedback loop will correct this distortion. Switchedcapacitor filters have a total harmonic distortion of about -70dB for the full swing of the used OTAs, even at extremely low power supply voltages. In an extremely low voltage switched-capacitor filter the switches are the biggest problem. Typically these switches are complementary driven nMOS and PMOS transistors. The problem is that these devices do not switch on unless the voltage between gate and source is higher than the Vr . The formula for the conductivity of these switches is (we will use a 2 pm n-well CMOS process with Vr = fo.9 V for all examples discussed in this text) : ,g
F [ v ~ -vrw
= KP,
-V,
- 'Y.
(4-
-
Fig. 7 displays the conductivity of the switch when minimum size transistors are used. In this curve there is a minimal conductivity at Vu - V,,, (3.8 V at Vu = 5 V). In Fig. 8 this minimum conductivity is plotted versus the power supply as a maximum resistivity. When V,, is reduced and
Iv, I
there is a point at which the resistivity is r e a h v,, + rnfinte because there is a zone in which neither of the two transistor is switched on. From this point on it is useless to use a complementary switch. In this case it is preferable to use a single nMOS switch because it has a three times lower resistivity than a PMOS switch. When a single transistor switch is used, tbe signal swing that can be applied is limited. In the case of single nMOS switches switch 2,3 and 4 limit the signal swing to 2(Vu - V , -V,,,,). Switch 1 limits it however to V , -Vrn - V - . This means that there is not much swing left when an extremely low voltage power supply is used (0.3 V when V,, = 1.5 V). This swing can only be used when the nMOS switch is bigger than minimum size (e.g. W / L= 10) because the switch is used in its low conductivity region. The consequence of using big switches is high clock feed through. This effect is however limited because low voltage clock signals are used. 025
e
E
0
0 1
m)]
005
For switches 2,3 and 4 in Fig. 6 the lowest conductivity appears when the source voltage is equal to the reference level. For switch 1 the worst case occurs when for the nMOS the source voltage is equal to the maximum input signal level or when for the PMOS the source voltage is equal to the minimum input signal level.
-
0
-
0
-0 5
. 1
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'
,
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2 V.
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Fig. 7. Conductivity of a complementaryswitch in function of the signal voltage level. IS0
-
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Fig. 8. Maximum resistivity of a complementary switch in function of the power supply voltage
Fig. 6. Switchedcapacitor invelting integrator.
1449
Authorized licensed use limited to: MIT Libraries. Downloaded on July 2, 2009 at 17:50 from IEEE Xplore. Restrictions apply.
B.Implementation techniques The easiest way to improve the obtainable voltage swing
is using a special process tuned for the implementation of extremely low voltage switched-capacitor filters. In [6] a CMOS process is used which has an extra nMOS transistor with V , = 0.2 V. This transistor is used as switch together with a normal PMOS transistor ( IVT,l = 0.85 V). In this way a voltage swing of 1 V is obtained with V , = 1.4 V. To realise this an extra mask and an extra implantation is necessary. The main disadvantage of this technique is the very high cost for developing a special process for only one kind of application. For this reason it can not be considered as a feasible solution. Another disadvantage of the nMOS switch-transistor used here is that it can not be tumed off completely anymore. The result is distortion and a deformation of the filter transfer characteristic. The most often used technique to improve the voltage swing is on chip clock signal voltage multiplication [7], [8], [9]. In these realisations a technique is used which is derived from the programming system in EEPROM's [lo], [ l l ] . A system of charching and discharching capacitances which are connected to each other with diodes is used to make a higher voltage ( V < , ) .This voltage is not used as voltage supply because the power consumption would be too high and the necess'uy chip area for this voltage multiplier would be too big. Only the clock signals for the switches run on this voltage. The necessary condition for a low voltage switchedcapacitor filter using complementary switches is V , > V , +IV,I. In the first implementation technique this is solved by making one of the V , ' s smaller. In the second it is solved by replacing V , with a special Vc, which can be made higher. The necessary condition for a switchedcapacitor filter using single nMOS switches is V , > V _ + V , + V h , (V, is the signal voltage swing in Volts peak-to-peak). Now a third implementation technique is introduced, called switched-buffer, which allows a large voltage swing at extremely low voltages without needmg a special process or a voltage multiplier. It is based on the fact that the limitation V , > V w + V , + Vdm holds only for switch 1. By eliminating switch 1 and replacing it by a switched buffer the voltage swing can be doubled. In Fig. 9 a switched-buffer inverting integrator is shown. Switch 1 is replaced by a buffer which is turned on and off by @, .This is done by switching the current sources in the buffer on and off. The main design consideration for this buffer is that it must be able to handle a large input voltage swing. This means that it is necessary to use a rail-to-rail amplifier. At these low voltages this can be done with a dual differential inputpair [12]. The disadvantage of this technique is that it needs switch transistors which are larger than minimum size. The switched buffers increase the power consumption and the chip area.
Fig. 9. Switched-buffer inverting integrator
IV. REFERENCES. P. R. Gray and R. G. Meyer, "Analysis and design of analog integrated circuits," John Willey & Sons. Singapore, 1984. F. Krummenacher and N. Joehl. "A 4 MHz CMOS continuous-time filter with on chip automatic tuning," IEEE J. of Solid-state Circuits, Vol. SC-23. pp 750-757, June 1988. R. R. Torrance, T. R. Viswanathan and J. V. Hanson, "CMOS voltage to current transducers," E E E Trans. on Circuits and Systems. Vol. Cas-32, pp 1097-1 104, NOV.1985. J. Silva-Martinez, M. Stcyaert and W. Sanscn, "A high-frequency large-signal very low-distortion transconductor." IEEE Proc.ESSCIR90. Orenoble France, pp169-172, Sept. 1990. J. Silva-Martinez, M. Steyaert and W. Sansen, "A large-signal very low-distortion transconductor for high-frequency continuous-time filters," IEEE J. of Solid-state Circuits, Vol. SC-26. pp 946-955, July 1991. r. Adachi, A. Ishinawa, A. Barlow and K. Takasuka, ' A 1.4 V switched capacitor filter," Proc. CICC (Bmton). pp.8.2.1-8.2.4, May 1990. R. Castello and L. Tomasini, "1.5-VHigh-performance SC filters in BiCMOS technology," IEEE J. of Solid-State Circuits, Vol. SC-26, no. 7, pp.930-936, July 1991. F. Calias, F. H. Salchi and D. Girard, "A set of four I C s in CMOS technology for a programmable hearing aid," IEEE J. of Solid-state Circuits, vol. SC-20, no. 2, pp.301-312, April 1989. R. Becker and J. Mulder. "SIGFRED: A low-power DTMF and signalling frequency detector," Roc.ESSCIRC (Grcnoble). pp.5-8.
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"On-chip high-voltage generation in MNOS integrated circuits using an im roved voltage multiplier technique," IEEE J. of Solid-State Circuits.$ol. SC-11, pp.374-378. June 1978. B. Gerber, J. C. Martin and J. Fellrath, "A 1.5 V single-supply onetransistor CMOS EEPROM," lEEE J. of Solid-State Circuits, vol. SC-16, no. 3, p.195, 1981. J. H. Huijsing and D. Lincbarger, "Low-voltage operational amplifier with rail-to-rail input and output ranges," IEEE J. of Solid-State Circuits. vol. SC-20, no. 6. pp.1144-1150. Dec. 1985.
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