m CMOS bluetooth receiver IC - Solid-State
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
A 3-V, 0.35-m CMOS Bluetooth Receiver IC Wenjun Sheng, Student Member, IEEE, Bo Xia, Student Member, IEEE, Ahmed E. Emira, Student Member, IEEE, Chunyu Xin, Student Member, IEEE, Ari Yakov Valero-López, Student Member, IEEE, Sung Tae Moon, Student Member, IEEE, and Edgar Sánchez-Sinencio, Fellow, IEEE
Abstract—A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm2 die using TSMC 0.35- m standard CMOS process. 82 dBm sensitivity at 1e-3 bit error rate, 10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply. Index Terms—Active complex filter, CMOS integrated circuits, GFSK demodulator, low-IF receiver, radio receivers.
I. INTRODUCTION
B
LUETOOTH is a universal radio standard recently developed for short-distance wireless communication applications. The first-generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. The radio band used by Bluetooth is the Industrial, Scientific and Medical (ISM) band ranging from 2400 to 2483.5 MHz. The modulation scheme employed is Gaussian frequency shift keying (GFSK) with an instantaneous bit rate of 1 Mb/s [1]. Due to the application environment of the Bluetooth system, the specification has made emphasis on intermodulation performance. Low cost, low power consumption, and small form factor are essential requirements for a Bluetooth transceiver. Several industry-designed Bluetooth transceivers have been recently reported [2]–[6]. In this paper, we present a fully integrated CMOS Bluetooth receiver designed independently in a university environment. The receiver was fabricated using a low-cost 0.35- m standard CMOS process provided by TSMC. The receiver uses a low-IF architecture with 2-MHz IF. A lowpower mixed-mode GFSK demodulator that has a measured performance close to a digital optimum detector ensures a high sensitivity of the receiver. An on-chip automatically tuned OTA-C complex filter achieves more than 45 dB of image rejection and suppresses strong adjacent channel interference. In Section II, the receiver architecture and high-level design issues are addressed. Section III explains the circuit design of each building block in detail. Experimental measurements are reported in Section IV. Conclusions are provided in Section V.
Manuscript received February 15, 2002; revised July 30, 2002. The authors are with the Analog & Mixed Signal Center, Department of Electrical Engineering, Texas A&M University, College Station, TX 77843 USA. Digital Object Identifier 10.1109/JSSC.2002.806277
Fig. 1. Power spectrum density of a Bluetooth signal downconverted to baseband.
II. RECEIVER ARCHITECTURE Three different architectures are commonly used in current receiver designs: high-IF, low-IF, and direct-conversion architectures. The selection of different IFs results in different circuit implementation tradeoffs. The Bluetooth specification is developed in favor of high- or low-IF architectures due to the extremely short preamble and long frequency locking time provided in each time slot [1]. However, the redundancy in the sync word may relax the fast settling time requirement in direct conversion receivers. A high-IF receiver, which uses an IF much larger than the signal channel bandwidth, requires off-chip components with high quality factors ( ); hence, the system integration level is reduced, and extra power on the I/O driving circuits is demanded. In addition, the high-IF choice also increases the complexity of the IF band circuits and causes more power dissipation in the IF stage. Thus, high-IF architecture is not adopted in the proposed design. In a baseband Bluetooth signal, 99% of the signal power is contained within the dc to 430-kHz bandwidth, as illustrated in Fig. 1. If a direct-conversion architecture is used, the flicker noise and dc offset will significantly degrade the signal-to-noise ratio (SNR). Hence, a low-IF architecture is more appropriate in this proposed design, especially when considering the relaxed image rejection requirement in the Bluetooth standard [1]. Fig. 2 shows the block diagram of the proposed low-IF receiver. The RF signal is amplified and downconverted to an IF by the RF front end (LNA-Mixer); then the channel selection is performed by an active complex filter, and next the IF signal is passed through an amplitude limiter which removes any amplitude perturbations. As required by the Bluetooth standard, a receiver signal strength indicator (RSSI) with
0018-9200/03$17.00 © 2003 IEEE
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Fig. 2. Low-IF Bluetooth receiver architecture.
a dynamic range of 26 dB is implemented within the limiter to indicate the received signal power. After the limiter, a GFSK demodulator demodulates the IF signal. Finally, a frequency offset cancellation and decision circuit is used to recover the original data. The choice of the IF is involved in many design tradeoffs. To relax the image rejection requirement and reduce the folded-back interference level, a very low-IF is preferable, i.e., half of the channel bandwidth. However, such a low IF increases the PLL locking time and phase noise when an integer-N frequency synthesizer is used due to the reduced loop bandwidth and requires a sharp cut off from the channel selection filter to reject the dc offset and flicker noise. On the other hand, a higher IF improves the demodulator performance, but of the channel selection filter will increase and the required power consumption will be higher. For a good compromise, an IF of two times the channel bandwidth is chosen, i.e., 2 MHz. For a low-IF Bluetooth receiver, the image signal is an in-band Bluetooth-modulated adjacent channel interference, which becomes a co-channel interference after frequency downconversion. When calculating the required image rejection ratio (IRR), the co-channel interference requirement, which is lower than the required SNR for the GFSK demodulator, should be used. An image rejection of 33 dB is sufficient to meet the specifications [7]. For the on-chip image rejection, we have potentially several choices: Hartley architecture, Weaver architecture [8], passive RC polyphase filter, or active polyphase filter. For the Hartely architecture, the high channel bandwidth-to-IF ratio makes the design of the 90 phase shifter very difficult. Weaver architecture requires an extra set of mixers, a frequency synthesizer, and high-order bandpass filters to reject the second image; thus, the power consumption and silicon area penalty is high. Passive RC polyphase filters can achieve a high image rejection ratio [9]; however, due to , they cannot achieve the required attenuation their limited of the adjacent channel interference, especially those strong folded-back interferences. Extra filtering is then required to reject the adjacent channel interference, which is also true for Hartley and Weaver architectures. Another drawback of a passive RC polyphase filter is that the finite input impedance loads the RF mixers. Thus, finally an active complex filter, which can achieve good image rejection and adjacent channel interference rejection, is used in the proposed design. The Bluetooth standard allows a transmitted center frequency offset as large as 100 kHz in one time slot [1]. If the fre-
Fig. 3. Simplified LNA and mixer schematic.
quency offset cannot be cancelled before the channel-selection filter, the passband of the filter has to be increased to accommodate a signal with a large frequency offset. As shown in Fig. 1, the baseband signal bandwidth is 430 kHz, resulting in a passband of the complex channel selection filter ranging from 1.47 to 2.53 MHz. A GFSK signal can be demodulated in either the analog or digital domain. The use of an analog demodulator in Bluetooth receiver avoids the use of an automatic gain control (AGC), which requires an extremely fast settling due to the short preambles (4 b) of Bluetooth. In this paper, we propose a novel architecture to realize a robust, low-power mixed-mode GFSK demodulator with a performance close to the digital optimum detector. III. CIRCUIT IMPLEMENTATIONS A differential topology is employed throughout the receiver circuits, among other properties, to minimize the undesired coupling through the low resistance substrate. A. LNA and Mixer A simplified schematic of the LNA and mixer is shown in Fig. 3. The LNA employs a cascode topology with inductive source degeneration through an on-chip spiral inductor. The input matching network (Lg, Ls, M1) is designed considering the nonquasi-static resistance [10]. The performance of the LNA is optimized by properly choosing the size of the input and cascode transistors. The size of the input transistor M1 of the amplifier input is chosen to obtain an effective circuit for optimum noise figure (NF) [11]. The size of the cascode transistor M2 is the same as M1:128/0.4 m, such that M1 and M2 can be laid out as a dual-gate transistor to
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(a) (a)
(b Fig. 5. (a) CMFB circuit. (b) CMFF circuit. (b Fig. 4. (a) Linear frequency translation to convert LPF to complex BPF. (b) Pseudodifferential OTA.
minimize the parasitic capacitance at the drain of M1, thus improving the noise figure. On-chip single-layer octagonal spiral inductors are used to implement the source degeneration inductance (0.3 nH) and load inductance (2.6 nH). The mixer is a modified double-balanced Gilbert-cell mixer. The tail current is removed in order to improve the linearity and allow low-voltage operation. Extra current ( ) is injected into the RF transistors to reduce the current flowing through the local oscillator (LO) switches and load resistors, thus dramatically reducing the flicker noise contributed by the switches and allowing the use of large load resistors which increase the conversion gain. Since the load of the mixer is resistive, the need of a common-mode feedback (CMFB) circuit is avoided. In order to avoid performance degradation, no access to the internal high-frequency nodes between the LNA and mixer is granted. The LNA and mixer have been tested as a single block: together they consume 10 mA of current from a 3-V power supply. The measured cascaded NF and voltage gain are 8.5 and 25 dB, respectively. The IIP3 is around 9 dBm. B. Active Complex Filter Complex filters have received much attention recently [12]. This interest comes from their ability to attenuate the image signal and the folded-back strong interference after downconversion. After mixing the RF signal at the output of the LNA with the two quadrature LO outputs, the signal and the image are downconverted to the IF frequency at the outputs of the I and Q mixers. However, the desired and image signals have 90 and 90 between the I and Q branches, respectively. Therefore, if the I and Q outputs are viewed as the real and imaginary parts of a complex signal, the desired signal will be cenwhile the image signal is centered at . A lowtered at pass filter (LPF) prototype can be converted to a bandpass complex filter by applying a linear frequency transformation, which is equivalent to replace each pair of grounded capacitors, in I and Q branches, by the circuit shown in Fig. 4(a) for an operational transconductance amplifier—capacitor (OTA-C) filter
(sometimes called the - filter) [12]. This transformation . is equivalent to shifting the LPF frequency response to Therefore, the image signal at will be outside the filter passband and will be rejected. System level simulations show that a complex filter based on a fourth-order Chebychev LPF or sixth-order Butterworth LPF may be sufficient to achieve the required selectivity. The Butterworth approximation is preferred for two reasons. First, it has small group delay variation (0.6 s) within the passband. Second, all the poles will have the same angular frequency leading to better matching in the cross-coupled in the LPF prototype OTAs in the entire filter. The highest tuning. is two, which can be realized easily without using However, a frequency tuning circuit is required to compensate for the expected large variations in the process used. To simplify the LPF to bandpass filter (BPF) transformation, the LPF prototype should have only grounded capacitors. The LPF prototype is implemented using three biquads. In order to reduce the input referred noise, the least number of transistors is used in the OTA, shown in Fig. 4(b). Long channel transistors (6 m) are used to enhance the output resistance, improve matching, and reduce flicker noise. A pseudodifferential architecture is used to reduce the required supply voltage. The transconductance of the OTA is given by (1) is the common-mode input voltage. Note that the where transconductance can be tuned by changing the common-mode . If the bias voltage is connected to a fixed bias voltage voltage source, the common-mode rejection ratio (CMRR) of the OTA equals unity. To enhance the CMRR of the OTAs, common-mode feedback (CMFB) or common-mode feed forward (CMFF) is used depending on the common-mode (CM) impedance at the output node. If the output CM impedance is high, then CMFB is needed to lower this impedance. This is illustrated in Fig. 5(a), where the output CM impedance becomes and is the transconductance of the CMFB loop. In the figure, the CM detector (CMD) senses the CM signal at the output nodes and feeds the correction signal to the bias voltage of the OTA. Since the CMD circuit is inverting, another inverting stage is added to make the CMFB loop gain negative. On
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(a)
Fig. 7.
(b Fig. 6. (a) CMD and auxiliary inverting circuit. (b) Bias circuit (for OTA in Fig. 7).
the other hand, if the output CM impedance is sufficiently small, CMFB is not needed and CMFF is used to isolate the input and output CM signals of the OTA. This is illustrated in Fig. 5(b). Note that the polarity of the OTA indicated in Fig. 4(b) is only in the differential mode (DM) sense. DM transconductance polarity can be changed by just exchanging the output terminals or input terminals without adding any extra components. However, the CM transconductance does not change by exchanging the output or input terminals. In fact, the CM transconductance of the OTA in Fig. 4(b) is always negative. Thus, a loop can be stable in DM but unstable in CM. The CMD and the inverting circuit are shown in Fig. 6(a). If no CMFB or CMFF is used, the bias voltage of the OTA is obtained from the biasing circuit shown in Fig. 6(b). Fig. 7 shows the I branch of one of the filter biquads. OTA and OTA form a negative feedback DM loop, but a positive feedback CM loop. The output node ) node due of OTA , node 1, is a low impedance ( to the resistive-connected OTA . Hence, no CMFB is needed at this node and only CMFF is used in all the OTAs that feed this node, excluding OTA . If CMFF is used in OTA , the CM impedance at node 1 will be very high. Instead, the bias voltage of OTA is obtained from the biasing circuit in Fig. 6(b). Note , not that the input to this biasing circuit is connected to to the input or output nodes of the OTA, and therefore OTA in all biquads can be biased using a single biasing circuit. The use of CMFF in OTA breaks the CM loop formed by OTA and OTA . Without CMFB, node 2 is a CM high impedance node, and hence, needs CMFB to stabilize it. The CMFB loop is formed in OTA through CMD . CMFF is also used in OTA , OTA , and OTA to isolate the CM signals in this biquad stage from the next biquad and from the corresponding biquad in the Q branch. Only two CMDs are needed to form the CM control circuit in this biquad stage with six OTAs. By using the min-
I branch of a complex biquadratic section.
imum number of CM control circuits, this efficient scheme saves considerable power and silicon area and contributes less noise than using a CM control circuit for each OTA. A CMRR in excess of 50 dB is obtained. Fig. 8 shows the block diagram of the entire complex filter. Passive input high-pass RC filters are used to isolate the CM applied mixer output from the filter CM input. The voltage through the R of the high-pass filter tunes the transconductance of the filter input stage, which uses the same OTA architecture shown in Fig. 4(b). An important design issue is how to distribute the gain among the filter stages. If all of the gain (15 dB) is used at the filter input stage, the noise performance will be optimized but the linearity is degraded and vice versa if the gain stage is placed at the end of the filter stages. Due to the tough noise requirement on the filter, a 15-dB gain stage is placed at the filter input as shown in Fig. 8. Since Bluetooth uses GFSK, in-band linearity is not a major issue. In contrast, the filter design should be focused to improve the out-of-band linearity. Since the out-of-band blockers will be attenuated by the filter, harmonics generated by the out-of-band blockers are dominated by the filter’s first gain stage. Hence, to improve the overall filter linearity, the gain stage is designed to have better linearity than ) of the the filter by using a larger overdrive voltage ( input NMOS transistors. Fig. 9 shows the frequency tuning circuit of the complex filter, which is built to compensate for process variations. The relaxation oscillator is built based on the same OTA architecture used in the filter. Under nominal conditions, the frequency of the relaxation oscillator is equal to the reference frequency (1 MHz). The operation of the tuning circuit is described as follows: after reset, the 7-b reference and oscillator counters start counting until the reference counter reaches 64. At this time, the Up/Dn counter is clocked to count up or down or freeze according to the output of the digital comparator, which compares the con. The content of the tent of the oscillator counter with 7-b Up/Dn counter is then converted to an analog voltage to control the frequency of the oscillator (by controlling the value through in the CMD circuit). When the reference of
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Fig. 8.
Complete complex filter.
Fig. 9.
Frequency tuning circuit for a complex filter.
Fig. 10.
Frequency synthesizer block diagram.
counter overflows (reaches 128), it sends a reset signal to the oscillator counter to begin a new frequency comparison cycle based on the updated oscillator frequency. Eventually, the oscillator frequency will reach the reference frequency within an error depending on the digital-to-analog (D/A) resolution. The in the CMFB and the same control voltage is applied to bias circuits of the filter (Fig. 6) to tune the frequency to the correct value. A dead zone is added to the comparator transfer characteristic to avoid oscillation in the loop around the desired frequency. The width of the dead zone is three counter steps around the middle count. The maximum error in the frequency-tuning loop depends on D/A accuracy and the range of VCO control. For 30 process variations and 7-b D/A, the maximum frequency error is 0.23 . This error is mapped to only a 4.6-kHz error in the filter center frequency, which is quite tolerable for Bluetooth application. A nonsystematic error should also be added due to mismatches between the transconductance and capacitance in the filter and the oscillator. These mismatches can add roughly 1% error to the frequency tuning. This is equivalent to another 20 kHz in error in the center frequency of the filter, which is still within the range that a Bluetooth filter can tolerate. Guard rings are used to isolate the “noisy” tuning circuit from the filter. An RC LPF is used at the output of the tuning circuit
Fig. 11.
Charge pump schematic.
to further attenuate the noise. A 1-MHz tone was observed at the output of the filter at 20 dB below the noise floor. The areas occupied by the filter and the tuning circuit are 1.6 0.8-mm and 1 0.4-mm , respectively. The filter consumes 4.7 mA current while the tuning circuit current consumption is 0.8 mA. The measured IRR is 45 dB. The image side noise coming from the antenna and LNA is rejected by the complex filter. The noise
SHENG et al.: CMOS BLUETOOTH RECEIVER IC
Fig. 12.
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VCO with varactor array.
generated by the I and Q mixers is uncorrelated at the filter inputs. Half of this noise will be rejected by the filter (image side), while the other half will pass through the filter (signal side).
C. Frequency Synthesizer and VCO Fig. 13.
A 15/16 prescaler.
Fig. 14.
A 3/4 divider.
The frequency synthesizer uses an integer N architecture in order to generate the LO signal ranging from 2.404 to 2.481 GHz. Fig. 10 shows the block diagram of the frequency synthesizer. The reference frequency should be equal to the channel spacing of 1 MHz since the dividing modulus is integer. It is generated from an external 16-MHz crystal oscillator. Fig. 11 shows the schematic diagram of the charge pump. helps the current source to be The current mirror carrying turned off quickly by discharging the controlling node . In the absence of the bleed current sources M5–M6, the switching time of the current mirror depends on the time constant of the diode connected transistor M3, slowing down the operation of the charge pump and degrading the output waveform. The improved switching speed of the charge pump is obtained at the expense of quiescent power dissipation. However, this is justified as the pulse matching directly affects the spurious performance of the frequency synthesizer [13]. was fixed at The charge pump output current is 20 A. at 10 A. The small value of the current allows 30 A and having a large output resistance, improving the matching in the currents flowing through the current mirrors. A tradeoff between of the output transistors and the output range of the the output node is present in the design of the output stage of the charge pump. The phase noise of Bluetooth is implied to be 128 dBc/Hz at a 3-MHz offset frequency. Due to its stringent phase noise
requirement and relatively small tuning range (3.3%), the LC-tuned negative-resistance oscillator is the most suitable. One critical concern for the LC-tuned oscillator is that the narrow tuning range might be out of the desired band due to the technology process variations. Moreover, there is a serious tradeoff between the tuning range and the sensitivity. A wide tuning range is good for overcoming the process variations, but it increases the sensitivity of the frequency to control voltage noise due to increased gain. On the other hand, if the tuning range is decreased to make the frequency less sensitive to the control voltage noise, the VCO may not be able to cover enough frequency range to compensate for the process
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Fig. 15.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
Current steering NOR D Flip-flop.
Fig. 17.
(b
(a) Fig. 16. buffer.
Effect of VCO on the loop filter. (a) Without the buffer. (b) With the
variations. To solve this tradeoff, a discrete-tunable varactor array is introduced. As shown in Fig. 12, the varactor array consists of two parts: that is controlled by a large inversion-mode MOS varactor and three small MOS varactors controlled by the digital word . If the oscillation frequency range is out of the desired band due to process variations, the PLL will saturate the control voltage at its extreme value. When the control voltage reaches
Limiter and RSSI.
its maximum or minimum value, the digital word is decreased or increased so that the oscillation frequency band can be shifted is the only varactor that is directly conaccordingly. Since nected to the control voltage, the tuning sensitivity is determined only. However, the total tuning range is by the variation of and the remaining varactors decided by the combination of . Testing results show that, by using the discrete-tunable varactor array, the VCO can cover the range of 2380–2710 MHz while maintaining a VCO gain of less than 140 MHz/V. The design of the prescaler in the frequency synthesizer has to be optimized for maximum speed with minimum power consumption. Fig. 13 shows a 15/16 prescaler formed by a 3/4 divider and two divide-by-two flip flops. The 3/4 divider shown in Fig. 14 uses a combination of NOR gate and D flip-flops. A property of this configuration is that the fan-out of the flip-flops is smaller than that of more conventional architectures. Another advantage of this architecture is that both flip-flops are similar and only one design is needed. Several implementations can be used for the full speed flip-flops. The classical current steering is preferred over dynamic logic implementations because the power consumption can be reduced, due to the limited swing of the signals in the flip-flop. Fig. 15 shows a current steering1 NOR _D flip flop [14]. The NOR gate is merged with the input is set at the middle of the swing of the differential pair and input signals A and B. Only an extra transistor is added in parallel to one of the inputs of the FF1 (Fig. 14) to perform the 1Simulations showed that the flip-flop design can tolerate up to 30% decrease in g of transistors, and still operate properly.
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(a)
(b Fig. 18. (a) Zero-crossing detector. (b) Proposed GFSK demodulator.
NOR operation. This means the same flip-flop can be used in the whole prescaler. The sizing of the transistors in the flip-flop is not straightforward. Since we have three stacked transistors, we need to carefully size the transistors in order to accommodate them within the power supply. At the same time, the transistor size has to be as small as possible to minimize the capacitance in each node to run the flip-flops at high frequency. The effect of the load has also to be considered during the sizing of the transistors. The tail current is 1 mA. The size of the transistors in the latches is smaller than that of the differential pairs to increase the speed of the flip-flop. When the loop filter is directly connected to the VCO control input, high-frequency signal from the VCO leaks back to the loop filter, overwhelming the control signal coming from the charge pump and preventing the synthesizer from locking. Fig. 16(a) shows the reason for such a leak. The control voltage of the VCO is connected to an inversion mode varactor. The gate and ), thus a of the varactor is the output of the VCO ( large high-frequency signal is present at the gate. Even though the control voltage node of the VCO is common for both outputs and , it is not a dc level. Small differences in amplitude and phase at the outputs of the VCO generate a high-frequency signal at this node. Inserting a buffer between the loop filter and the VCO solves the problem of the signal leaking to the loop filter, as shown in Fig. 16(b).
(a)
(b Fig. 19.
(a) ZD one-shot. (b) SK one-shot.
Fig. 20.
Format of the access code (trailer only exists in the data packet).
D. Limiter and GFSK Demodulator The employed limiter architecture is a cascaded structure of five voltage gain cells (Fig. 17), each cell consisting of an NMOS differential pair and NMOS loads provides 14 dB gain, which makes the overall gain 70 dB. A feedback-type offset cancellation mechanism is used to reduce the input offset voltage. A 26-dB RSSI is an integral part of the limiting amplifier. The signals at the output of each amplifying cell are rectified by multiplier-type rectifiers and summed up by resistors to provide a logarithmic output voltage [15]. As shown in Fig. 2, the I and Q outputs from two limiters feed the GFSK demodulator.
The proposed demodulator is based on the concept of a zerocrossing detector shown in Fig. 18(a). Fig. 18(b) shows the block diagram of the demodulator. The I and Q inputs come from the limiters. Two zero-crossing detection (ZD) one-shots emulate a differentiator in the demodulator. They detect the positive and negative zero crossing points of input I and Q signals and generate a narrow pulse (10 ns) at each zero-crossing moment. After the ZD one-shot, the pulses from both I and Q branches are combined together through OR gates and NOR gates. For
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Fig. 21.
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Block diagram of the dc offset cancellation and decision circuits. (a) Circuit and operation modes of the integrator/LPF block. (b) Clocks in the circuit.
(a)
(b) Fig. 22.
Integrator/LPF block. (a) Circuit and operation modes of the integrator/LPF block. (b) Clocks in the circuit.
the ZD one-shot circuit shown in Fig. 19(a), the timing capacitor, resistor, and the threshold of the digital gates determine the pulsewidth of the one-shot. Process variations and mismatches may cause different widths of the pulses generated by different one-shots, and this will affect the BER negatively. In order to eliminate the pulsewidth variation, another shape-keeping (SK) one-shot is used to recondition the pulses. The SK one-shot is shown in Fig. 19(b). R1–R3 form a voltage divider, providing a reference voltage. The pulsewidth at the output of the SK one-shot is determined mainly by the ratio of R1, R2, R3, and the value of resistor R5 and capacitor C2. The SK one-shot generates a new train of equal-width pulses (40 ns) corresponding to each pulse from ZD one-shots. For the SK one-shot to work properly, its pulsewidth should be larger than the pulsewidth of any ZD one-shot. On the other hand, an SK one-shot with a pulse that is too wide might cause overlapping of adjacent pulses
and degrade the performance. Therefore, a judicious choice of the pulsewidth is required to comply with the previous restrictions even with very large process variations and mismatch to assure robustness. The pulsewidth of SK one-shot is chosen to be larger than any of ZD one-shots even with very large process variations, thus, the demodulator is robust to process variations and mismatches. Using both I and Q branches, instead of a single branch, improves the performance of the demodulation due to the increased zero-crossing information per bit period. Since the active complex filter before the demodulator inherently has I and Q outputs, the extra silicon area and power consumption needed to build the two branches demodulator are moderate, while the performance is greatly improved. When the input Bluetooth modulated signal has the nominal modulation index of 0.32, for 1e-3 BER as specified in Bluetooth standard, only a 16.2-dB input SNR is required for the demodulator. When
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(a)
Fig. 23.
Die microphotograph of Bluetooth receiver (6.25 mm ).
a Bluetooth modulated co-channel interference, which is 11.2 dB lower than the desired signal, is added to the signal, the measured BER is better than 1e-3. The demodulator consumes 3 mA of current, and no calibration is required. (b
E. Frequency Offset Cancellation Circuit Performance degradation caused by LO frequency drifting between the transmitter and receiver is a major concern in the design of a Bluetooth receiver. Given an indoor environment and limited mobility, the Doppler shift in the system is negligible in comparison with the LO frequency offset produced by inaccurate LOs. According to the Bluetooth specifications, the maximum LO frequency offset between two Bluetooth units can be 100 kHz, combining the transmitter-receiver LO offset and other frequency drifting. This amount equals almost 60% of the maximum frequency deviation provided by the GFSK modulation scheme. Using the proposed demodulator, this frequency offset is converted into a dc offset voltage. This considerable shift in the dc voltage severely increases the decision error in the bit detector and hence degrades the BER performance of the whole system. System-level simulations show that the dc offset has to be less than 10% of the peak-to-peak voltage of the demodulated signal to assure a good performance of the receiver. The last stage of the demodulator is used to cancel the dc offset and detect the received data bits. In each Bluetooth data packet, there are four preamble bits and four trailer bits in the access code, either in form of “0101” or “1010,” which average a zero dc offset (Fig. 20). By integrating either of those two segments, we can get an estimation of the existing dc offset and subtract it from the demodulated signal. Since a maximum 25 kHz frequency drifting is likely to occur in one time slot, the baseband circuit should be able to track this variation and adjust the subtracted offset voltage once the drifting exceeds
Fig. 24.
(a) Input return loss of receiver. (b) Phase noise of VCO.
Fig. 25.
VCO tuning range testing result.
certain threshold. In the circuit implementation, we change the operating mode of the circuit using switched-capacitor techniques. The dc offset cancellation circuit works as an integrator during the reception of the access code and as a very low-pass filter (20-kHz 3-dB BW) during the data packets transmission to track the possible frequency drifting. A switched-capacitor sample-and-hold circuit stores the offset voltage and feeds it back to a voltage subtractor (node 1, Fig. 21) to cancel the dc offset before the signal goes to the decision circuit. A complete
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(a) (a)
(b Fig. 26. (a) Noise spectrum at a complex filter output. (b) Complex filter frequency response for the signal and image sides.
(b Fig. 27. (a) IIP3 of the receiver. (b) Measured BER versus receiver input RF signal power.
circuit block diagram of the dc cancellation and decision circuit is shown in Fig. 21. One critical issue in the circuit design is the timing arrangement. Since the access code is at the beginning of the data packet, the dc cancellation circuit starts to integrate the incoming signal whenever the RF front end detects a power burst in the received signal. Signal synchronization at this stage is not very accurate, hence the dc offset estimation is not accurate either. Fine synchronization is achieved by calculating the autocorrelation of the sync word. Once the receiver clock is synchronized to the transmitter clock, we can integrate the trailer in the access code of a data packet to get an accurate dc offset estimation. Fig. 22 shows the operation modes and clocks of the integrator/LPF circuit. The decision circuit is an integrate-and-dump circuit. It is relatively immune to the timing error and hence has better performance than a simple sample-and-decision circuit. The bit detection is implemented by a latch comparator [16]. The total current consumption of the offset cancellation circuit is less than 1 mA. The circuit can handle frequency errors up to 150 kHz. IV. EXPERIMENTAL RESULTS The receiver IC is fabricated in TSMC 0.35- m standard CMOS process and packaged in a 48-pin TQFP plastic package.
It takes a 6.25-mm silicon area. The die microphotograph is shown in Fig. 23. The receiver active current is about 65 mA ( 2) of from a 3-V power supply. An unexpected low the on-chip inductors used in the VCO was obtained during the measurements. The problem is caused by the inadequate accuracy of the available simulator for on-chip spiral inductor simulations and the fact that several necessary parameters of the technology process needed for the simulation are not of available from MOSIS worsens the problem. The low on-chip spiral inductors forces extra current consumption of greater than VCO buffers during the measurements. For a 5, as expected, the total receiver current consumption would be below 45 mA. In Fig. 24(a), the measured input return loss of the receiver is less than 12 dB in the whole Bluetooth frequency band. In Fig. 24(b) the measured phase noise of the VCO at 1-, 2-, and 3-MHz offset at a 2.4-GHz center frequency are 118 dBc/Hz, 125 dBc/Hz, and 130 dBc/Hz, respectively. In Fig. 25, the measured VCO tuning range is shown. With the tunable varactor array, the VCO is able to cover the frequency range of 2380–2710 MHz, which is about 14% of the oscillation frequency. Fig. 26(a) shows the measured noise spectrum at the filter output, and the NF of receiver is 15 dB. Fig. 26(b) shows
SHENG et al.: CMOS BLUETOOTH RECEIVER IC
the complex filter frequency response for the signal and image side. The IRR is 45 dB. The filter attenuates the first and second adjacent channels by 27 and 58 dB on the signal side, respectively. The first adjacent channel at the image side is attenuated by 79 dB. The IIP3 was measured by applying to the input two 39-dBm interferers which are 3 and 6 MHz away from the desired Bluetooth signal. As shown in Fig. 27(a), the measured IIP3 of the receiver is 10 dBm. The measured receiver BER versus the input RF signal power is shown at Fig. 27(b). At a 1e-3 BER, the minimum detectable signal is 82 dBm. V. CONCLUSION The development of the proposed Bluetooth receiver followed a top-down approach. The system architecture was chosen and developed independently.2 Key building blocks not reported before, such as the active complex - filter and the mixed-mode GFSK demodulator, were proposed. All system and circuits were obtained within a period of 12 months. This is the first functional Bluetooth receiver IC designed independently in a university environment, using a low-cost standard CMOS process and meeting major specifications. The key performance measurements are 82 dBm sensitivity at 1e-3 BER, 10 dBm IIP3, and 15-dB noise figure. ACKNOWLEDGMENT The authors would like to thank the RF IC Design Group from Texas Instruments and the Wireless Subscriber Systems Group from Motorola for system and circuit design discussions. They also thank D. Hernández-Garduño and A. Valdés-García for their assistance in the layout and PCB design and S. Yan for technical discussions.
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[8] B. Razavi, RF Microelectronics. Englewood Cliffs, NJ: Prentice-Hall, 1998. [9] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol. 36, pp. 873–887, June 2001. [10] M. S. J. Steyaert, J. Janssens, B. D. Muer, M. Borremans, and N. Itoh, “A 2 V CMOS cellular transceiver front-end,” IEEE J. Solid-State Circuits, vol. 35, pp. 1895–1907, Dec. 2000. [11] D. K. Shaeffer and T. H. Lee, “A 1.5-V 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid State Circuits, vol. 32, pp. 745–759, May 1997. [12] P. Andreani, S. Mattisson, and B. Essink, “A CMOS gm-C polyphase filter with high image band rejection,” in Proc. 2000 26th Eur. SolidState Circuits Conf., Sept. 2000, pp. 244–247. [13] J. F. Parker and D. Ray, “A 1.6-GHz CMOS PLL with on-chip loop filter,” IEEE J. Solid-State Circuits, vol. 33, pp. 337–343, Mar. 1998. [14] C. Lam and B. Razavi, “A 2.6 GHz/ 5.2 GHz frequency synthesizer in 0.4 m CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 788–794, May 2000. [15] S. Khorram, A. Rofougaran, and A. A. Abidi, “A CMOS limiting amplifier and signal-strength indicator,” in Symp. VLSI Circuits Dig. Tech. Papers, 1995, pp. 95–96. [16] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.
Wenjun Sheng (S’97) was born in China in 1974. He received the B.S. degree in electronic engineering from Tsinghua University, Beijing, China, in 1996 and the M.E. and Ph.D. degrees in electrical engineering from Texas A&M University, College Station, in 1999 and 2002, respectively. From August 1998 to July 1999, he was with Texas Instruments, Inc., Dallas, TX, for his internship. He worked in the wireless baseband group and RF system group of Texas Instruments. Since April 2002, he has been with Qualcomm, Inc., San Diego, CA, as a senior RFIC design engineer. He is working on the design of RF and analog ICs for wireless communication applications. His research interests are focused on RF transceiver design for wireless communications and RF/analog IC design. Dr. Sheng is a corecipient of the 2002 Radio Frequency Integrated Circuits Symposium Best Student Paper Award.
REFERENCES [1] Bluetooth Specification Version 1.0 B. [2] A. Ajjkuttira, C. Leung, E. Khoo, M. Choke, R. Singh, T. Teo, B. Gheong, J. See, H. Yap, P. Leong, C. Law, M. Itoh, A. Yoshida, Y. Yoshida, A. Tamura, and H. Nakamura, “A fully-integrated CMOS RFIC for bluetooth applications,” in Proc. IEEE Int. Solid-State Circuits Conf., 2001, pp. 198–199. [3] F. O. Eynde, J.-J Schmit, V. Charlier, R. Alexandre, C. Sturman, K. Coffin, B. Mollekens, J. Craninckx, S. Terrijn, A. Monterastelli, S. Beerens, P. Goetschalcks, M. Ingels, D. Joos, S. Guncer, and A. Pontioglu, “A fully-integrated single-chip SOC for bluetooth,” in Proc. IEEE Int. Solid-State Circuits Conf., 2001, pp. 196–197. [4] H. Darabi, S. Khorram, E. Chien, M. Pan, S. Wu, S. Moloudi, J. C. Leete, J. Rael, M. Syed, R. Lee, B. Ibrahim, M. Rofougaran, and A. Rofougaran, “A 2.4 GHz CMOS transceiver for bluetooth,” IEEE J. Solid-State Circuits, vol. 36, pp. 2016–2024, Dec. 2001. [5] N. Filiol, N. Birkett, J. Cherry, F. Balteanu, C. Gojocaru, A. Namdar, T. Pamir, K. Sheikh, G. Glandon, D. Payer, A. Swaminathan, R. Forbes, T. Riley, S. M. Alinoor, E. Macrobbie, M. Cloutier, S. Pipilos, and T. Varelas, “A 22 mW bluetooth RF transceiver with direct RF modulation and on-chip IF filtering,” in Proc. IEEE Int. Solid-State Circuits Conf., 2001, pp. 202–203. [6] C. Durdodt, M. Friedrich, C. Grewing, M. Hammes, A. Hanke, S. Heinen, J. Oehm, D. Pham-Stabner, D. Seippel, D. Theil, S. V. Waasen, and E. Wagner, “The first very low-IF RX, 2-point modulation TX CMOS system on chip bluetooth solution,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., 2001, pp. 99–102. [7] W. Sheng, “Design and Implementation of CMOS Radio Frequency Receivers,” Ph.D. dissertation, Texas A&M University, 2002. 2Although Darabi et al. [4] reported a Bluetooth transceiver using a similar low-IF architecture, we independently also proposed the same architecture. Our silicon design was submitted in April 2001.
Bo Xia received the B.S. degree in electrical engineering from Shanghai Jiao Tong University, China, in 1997. He is currently working toward the Ph.D. degree in electrical engineering at Texas A&M University, College Station. From 1997 to 1998, he worked as a Staff Engineer at Hewlett Packard Co., Ltd. Since 1998, he has been a Research Assistant in the Analog and Mixed Signal Center, Texas A&M University. He held an internship at AGERE, Allentown, PA, from July 2002 to September 2002. His research includes RF transceiver systems and circuits design, ADC and AGC circuits design. Mr. Xia is a corecipient of the Best Student Paper Award on IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2002.
Ahmed A. Emira (S’00) was born in Cairo, Egypt, in 1974. He received the B.Sc. and M.Sc. degrees from Cairo University, Cairo, in 1997 and 1999, respectively. He is currently working toward the Ph.D. degree at Texas A&M University, College Station. He worked as a Teaching Assistant in the Department of Electrical and Computer Engineering, Cairo University, from July 1997 until December 1999. He has held an internship at Motorola, Austin, TX, from September 2001 to August 2002. His current interests include mixed-signal circuits, analog filter design, and communication system architectures. Mr. Emira received the third best student paper award in RFIC, Seattle, WA, 2002.
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Chunyu Xin (S’01) was born in Tianjin, China, in 1974. He received the M.S. degree from Nankai University, Tianjin, China, in 1999. He is currently working toward the Ph.D degree at Texas A&M University, College Station. His current research interests are integrated RF and IF circuits designs. Mr. Xin is a coauthor of the best conference student paper award received in Seattle, WA, June 2002.
Ari Yakov Valero-López (S’00) was born in Mexico City, Mexico, in 1972. He received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico, in 1996, and the M.Sc. degree from the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico, in 1998. He is currently working toward the Ph.D. degree at Texas A&M University, College Station. His current field of research is in the design and fabrication of analog and mixed-signal circuits and frequency synthesizers for communication systems. Mr. Valero-Lopez is a corecipient of the third best student paper award in RFIC, Seattle, WA, 2002.
Sung Tae Moon (S’00) was born in Busan, Korea, in 1974. He received the Bachelor of Engineering Degree from the Seoul National University, Seoul, Korea, in 1997. He is currently working toward the Ph.D. degree at Texas A&M University, College Station. His current interest of research is in the design and fabrication of analog and mixed-signal circuits and RF/MW oscillators for communication systems. Mr. Moon is a corecipient of the third best student paper award in RFIC, Seattle, WA, 2002.
Edgar Sánchez-Sinencio (S’72–M’74–SM’83– F’92) was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, in 1966, the M.S.E.E. degree from Stanford University, Stanford, CA, in 1970, and the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1973. In 1974, he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983, he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983–1984. He is currently the TI J. Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He is coauthor of the book Switched Capacitor Circuits (New York: Van Nostrand-Reinhold, 1984) and coeditor of the book Low Voltage/Low-Power Integrated Circuits and Systems (Piscataway, NJ: IEEE Press, 1999). His present interests are in the area of RF-communication circuits and analog and mixed-mode circuit design. Dr. Sánchez-Sinencio was an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (1985–1987) and an Associate Editor for the IEEE TRANSACTIONS ON NEURAL NETWORKS. He is the former Editor-in-Chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II. He is a former President of the IEEE Circuits and Systems Technical Committee on Neural Systems and Applications and CAS Technical Committee on Analog Signal Processing. In November 1995, he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico, the first honorary degree awarded for Microelectronic Circuit Design contributions. He received the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the corecipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He is currently the IEEE Circuits and Systems Society representative to the Solid-State Circuits Society (2000–2002). He is currently a member of the IEEE Solid-State Circuits Award Committee.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
A 3-V, 0.35-m CMOS Bluetooth Receiver IC Wenjun Sheng, Student Member, IEEE, Bo Xia, Student Member, IEEE, Ahmed E. Emira, Student Member, IEEE, Chunyu Xin, Student Member, IEEE, Ari Yakov Valero-López, Student Member, IEEE, Sung Tae Moon, Student Member, IEEE, and Edgar Sánchez-Sinencio, Fellow, IEEE
Abstract—A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm2 die using TSMC 0.35- m standard CMOS process. 82 dBm sensitivity at 1e-3 bit error rate, 10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply. Index Terms—Active complex filter, CMOS integrated circuits, GFSK demodulator, low-IF receiver, radio receivers.
I. INTRODUCTION
B
LUETOOTH is a universal radio standard recently developed for short-distance wireless communication applications. The first-generation Bluetooth products are focused on providing low-cost radio connections among personal electronic devices. The radio band used by Bluetooth is the Industrial, Scientific and Medical (ISM) band ranging from 2400 to 2483.5 MHz. The modulation scheme employed is Gaussian frequency shift keying (GFSK) with an instantaneous bit rate of 1 Mb/s [1]. Due to the application environment of the Bluetooth system, the specification has made emphasis on intermodulation performance. Low cost, low power consumption, and small form factor are essential requirements for a Bluetooth transceiver. Several industry-designed Bluetooth transceivers have been recently reported [2]–[6]. In this paper, we present a fully integrated CMOS Bluetooth receiver designed independently in a university environment. The receiver was fabricated using a low-cost 0.35- m standard CMOS process provided by TSMC. The receiver uses a low-IF architecture with 2-MHz IF. A lowpower mixed-mode GFSK demodulator that has a measured performance close to a digital optimum detector ensures a high sensitivity of the receiver. An on-chip automatically tuned OTA-C complex filter achieves more than 45 dB of image rejection and suppresses strong adjacent channel interference. In Section II, the receiver architecture and high-level design issues are addressed. Section III explains the circuit design of each building block in detail. Experimental measurements are reported in Section IV. Conclusions are provided in Section V.
Manuscript received February 15, 2002; revised July 30, 2002. The authors are with the Analog & Mixed Signal Center, Department of Electrical Engineering, Texas A&M University, College Station, TX 77843 USA. Digital Object Identifier 10.1109/JSSC.2002.806277
Fig. 1. Power spectrum density of a Bluetooth signal downconverted to baseband.
II. RECEIVER ARCHITECTURE Three different architectures are commonly used in current receiver designs: high-IF, low-IF, and direct-conversion architectures. The selection of different IFs results in different circuit implementation tradeoffs. The Bluetooth specification is developed in favor of high- or low-IF architectures due to the extremely short preamble and long frequency locking time provided in each time slot [1]. However, the redundancy in the sync word may relax the fast settling time requirement in direct conversion receivers. A high-IF receiver, which uses an IF much larger than the signal channel bandwidth, requires off-chip components with high quality factors ( ); hence, the system integration level is reduced, and extra power on the I/O driving circuits is demanded. In addition, the high-IF choice also increases the complexity of the IF band circuits and causes more power dissipation in the IF stage. Thus, high-IF architecture is not adopted in the proposed design. In a baseband Bluetooth signal, 99% of the signal power is contained within the dc to 430-kHz bandwidth, as illustrated in Fig. 1. If a direct-conversion architecture is used, the flicker noise and dc offset will significantly degrade the signal-to-noise ratio (SNR). Hence, a low-IF architecture is more appropriate in this proposed design, especially when considering the relaxed image rejection requirement in the Bluetooth standard [1]. Fig. 2 shows the block diagram of the proposed low-IF receiver. The RF signal is amplified and downconverted to an IF by the RF front end (LNA-Mixer); then the channel selection is performed by an active complex filter, and next the IF signal is passed through an amplitude limiter which removes any amplitude perturbations. As required by the Bluetooth standard, a receiver signal strength indicator (RSSI) with
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Fig. 2. Low-IF Bluetooth receiver architecture.
a dynamic range of 26 dB is implemented within the limiter to indicate the received signal power. After the limiter, a GFSK demodulator demodulates the IF signal. Finally, a frequency offset cancellation and decision circuit is used to recover the original data. The choice of the IF is involved in many design tradeoffs. To relax the image rejection requirement and reduce the folded-back interference level, a very low-IF is preferable, i.e., half of the channel bandwidth. However, such a low IF increases the PLL locking time and phase noise when an integer-N frequency synthesizer is used due to the reduced loop bandwidth and requires a sharp cut off from the channel selection filter to reject the dc offset and flicker noise. On the other hand, a higher IF improves the demodulator performance, but of the channel selection filter will increase and the required power consumption will be higher. For a good compromise, an IF of two times the channel bandwidth is chosen, i.e., 2 MHz. For a low-IF Bluetooth receiver, the image signal is an in-band Bluetooth-modulated adjacent channel interference, which becomes a co-channel interference after frequency downconversion. When calculating the required image rejection ratio (IRR), the co-channel interference requirement, which is lower than the required SNR for the GFSK demodulator, should be used. An image rejection of 33 dB is sufficient to meet the specifications [7]. For the on-chip image rejection, we have potentially several choices: Hartley architecture, Weaver architecture [8], passive RC polyphase filter, or active polyphase filter. For the Hartely architecture, the high channel bandwidth-to-IF ratio makes the design of the 90 phase shifter very difficult. Weaver architecture requires an extra set of mixers, a frequency synthesizer, and high-order bandpass filters to reject the second image; thus, the power consumption and silicon area penalty is high. Passive RC polyphase filters can achieve a high image rejection ratio [9]; however, due to , they cannot achieve the required attenuation their limited of the adjacent channel interference, especially those strong folded-back interferences. Extra filtering is then required to reject the adjacent channel interference, which is also true for Hartley and Weaver architectures. Another drawback of a passive RC polyphase filter is that the finite input impedance loads the RF mixers. Thus, finally an active complex filter, which can achieve good image rejection and adjacent channel interference rejection, is used in the proposed design. The Bluetooth standard allows a transmitted center frequency offset as large as 100 kHz in one time slot [1]. If the fre-
Fig. 3. Simplified LNA and mixer schematic.
quency offset cannot be cancelled before the channel-selection filter, the passband of the filter has to be increased to accommodate a signal with a large frequency offset. As shown in Fig. 1, the baseband signal bandwidth is 430 kHz, resulting in a passband of the complex channel selection filter ranging from 1.47 to 2.53 MHz. A GFSK signal can be demodulated in either the analog or digital domain. The use of an analog demodulator in Bluetooth receiver avoids the use of an automatic gain control (AGC), which requires an extremely fast settling due to the short preambles (4 b) of Bluetooth. In this paper, we propose a novel architecture to realize a robust, low-power mixed-mode GFSK demodulator with a performance close to the digital optimum detector. III. CIRCUIT IMPLEMENTATIONS A differential topology is employed throughout the receiver circuits, among other properties, to minimize the undesired coupling through the low resistance substrate. A. LNA and Mixer A simplified schematic of the LNA and mixer is shown in Fig. 3. The LNA employs a cascode topology with inductive source degeneration through an on-chip spiral inductor. The input matching network (Lg, Ls, M1) is designed considering the nonquasi-static resistance [10]. The performance of the LNA is optimized by properly choosing the size of the input and cascode transistors. The size of the input transistor M1 of the amplifier input is chosen to obtain an effective circuit for optimum noise figure (NF) [11]. The size of the cascode transistor M2 is the same as M1:128/0.4 m, such that M1 and M2 can be laid out as a dual-gate transistor to
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(a) (a)
(b Fig. 5. (a) CMFB circuit. (b) CMFF circuit. (b Fig. 4. (a) Linear frequency translation to convert LPF to complex BPF. (b) Pseudodifferential OTA.
minimize the parasitic capacitance at the drain of M1, thus improving the noise figure. On-chip single-layer octagonal spiral inductors are used to implement the source degeneration inductance (0.3 nH) and load inductance (2.6 nH). The mixer is a modified double-balanced Gilbert-cell mixer. The tail current is removed in order to improve the linearity and allow low-voltage operation. Extra current ( ) is injected into the RF transistors to reduce the current flowing through the local oscillator (LO) switches and load resistors, thus dramatically reducing the flicker noise contributed by the switches and allowing the use of large load resistors which increase the conversion gain. Since the load of the mixer is resistive, the need of a common-mode feedback (CMFB) circuit is avoided. In order to avoid performance degradation, no access to the internal high-frequency nodes between the LNA and mixer is granted. The LNA and mixer have been tested as a single block: together they consume 10 mA of current from a 3-V power supply. The measured cascaded NF and voltage gain are 8.5 and 25 dB, respectively. The IIP3 is around 9 dBm. B. Active Complex Filter Complex filters have received much attention recently [12]. This interest comes from their ability to attenuate the image signal and the folded-back strong interference after downconversion. After mixing the RF signal at the output of the LNA with the two quadrature LO outputs, the signal and the image are downconverted to the IF frequency at the outputs of the I and Q mixers. However, the desired and image signals have 90 and 90 between the I and Q branches, respectively. Therefore, if the I and Q outputs are viewed as the real and imaginary parts of a complex signal, the desired signal will be cenwhile the image signal is centered at . A lowtered at pass filter (LPF) prototype can be converted to a bandpass complex filter by applying a linear frequency transformation, which is equivalent to replace each pair of grounded capacitors, in I and Q branches, by the circuit shown in Fig. 4(a) for an operational transconductance amplifier—capacitor (OTA-C) filter
(sometimes called the - filter) [12]. This transformation . is equivalent to shifting the LPF frequency response to Therefore, the image signal at will be outside the filter passband and will be rejected. System level simulations show that a complex filter based on a fourth-order Chebychev LPF or sixth-order Butterworth LPF may be sufficient to achieve the required selectivity. The Butterworth approximation is preferred for two reasons. First, it has small group delay variation (0.6 s) within the passband. Second, all the poles will have the same angular frequency leading to better matching in the cross-coupled in the LPF prototype OTAs in the entire filter. The highest tuning. is two, which can be realized easily without using However, a frequency tuning circuit is required to compensate for the expected large variations in the process used. To simplify the LPF to bandpass filter (BPF) transformation, the LPF prototype should have only grounded capacitors. The LPF prototype is implemented using three biquads. In order to reduce the input referred noise, the least number of transistors is used in the OTA, shown in Fig. 4(b). Long channel transistors (6 m) are used to enhance the output resistance, improve matching, and reduce flicker noise. A pseudodifferential architecture is used to reduce the required supply voltage. The transconductance of the OTA is given by (1) is the common-mode input voltage. Note that the where transconductance can be tuned by changing the common-mode . If the bias voltage is connected to a fixed bias voltage voltage source, the common-mode rejection ratio (CMRR) of the OTA equals unity. To enhance the CMRR of the OTAs, common-mode feedback (CMFB) or common-mode feed forward (CMFF) is used depending on the common-mode (CM) impedance at the output node. If the output CM impedance is high, then CMFB is needed to lower this impedance. This is illustrated in Fig. 5(a), where the output CM impedance becomes and is the transconductance of the CMFB loop. In the figure, the CM detector (CMD) senses the CM signal at the output nodes and feeds the correction signal to the bias voltage of the OTA. Since the CMD circuit is inverting, another inverting stage is added to make the CMFB loop gain negative. On
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(a)
Fig. 7.
(b Fig. 6. (a) CMD and auxiliary inverting circuit. (b) Bias circuit (for OTA in Fig. 7).
the other hand, if the output CM impedance is sufficiently small, CMFB is not needed and CMFF is used to isolate the input and output CM signals of the OTA. This is illustrated in Fig. 5(b). Note that the polarity of the OTA indicated in Fig. 4(b) is only in the differential mode (DM) sense. DM transconductance polarity can be changed by just exchanging the output terminals or input terminals without adding any extra components. However, the CM transconductance does not change by exchanging the output or input terminals. In fact, the CM transconductance of the OTA in Fig. 4(b) is always negative. Thus, a loop can be stable in DM but unstable in CM. The CMD and the inverting circuit are shown in Fig. 6(a). If no CMFB or CMFF is used, the bias voltage of the OTA is obtained from the biasing circuit shown in Fig. 6(b). Fig. 7 shows the I branch of one of the filter biquads. OTA and OTA form a negative feedback DM loop, but a positive feedback CM loop. The output node ) node due of OTA , node 1, is a low impedance ( to the resistive-connected OTA . Hence, no CMFB is needed at this node and only CMFF is used in all the OTAs that feed this node, excluding OTA . If CMFF is used in OTA , the CM impedance at node 1 will be very high. Instead, the bias voltage of OTA is obtained from the biasing circuit in Fig. 6(b). Note , not that the input to this biasing circuit is connected to to the input or output nodes of the OTA, and therefore OTA in all biquads can be biased using a single biasing circuit. The use of CMFF in OTA breaks the CM loop formed by OTA and OTA . Without CMFB, node 2 is a CM high impedance node, and hence, needs CMFB to stabilize it. The CMFB loop is formed in OTA through CMD . CMFF is also used in OTA , OTA , and OTA to isolate the CM signals in this biquad stage from the next biquad and from the corresponding biquad in the Q branch. Only two CMDs are needed to form the CM control circuit in this biquad stage with six OTAs. By using the min-
I branch of a complex biquadratic section.
imum number of CM control circuits, this efficient scheme saves considerable power and silicon area and contributes less noise than using a CM control circuit for each OTA. A CMRR in excess of 50 dB is obtained. Fig. 8 shows the block diagram of the entire complex filter. Passive input high-pass RC filters are used to isolate the CM applied mixer output from the filter CM input. The voltage through the R of the high-pass filter tunes the transconductance of the filter input stage, which uses the same OTA architecture shown in Fig. 4(b). An important design issue is how to distribute the gain among the filter stages. If all of the gain (15 dB) is used at the filter input stage, the noise performance will be optimized but the linearity is degraded and vice versa if the gain stage is placed at the end of the filter stages. Due to the tough noise requirement on the filter, a 15-dB gain stage is placed at the filter input as shown in Fig. 8. Since Bluetooth uses GFSK, in-band linearity is not a major issue. In contrast, the filter design should be focused to improve the out-of-band linearity. Since the out-of-band blockers will be attenuated by the filter, harmonics generated by the out-of-band blockers are dominated by the filter’s first gain stage. Hence, to improve the overall filter linearity, the gain stage is designed to have better linearity than ) of the the filter by using a larger overdrive voltage ( input NMOS transistors. Fig. 9 shows the frequency tuning circuit of the complex filter, which is built to compensate for process variations. The relaxation oscillator is built based on the same OTA architecture used in the filter. Under nominal conditions, the frequency of the relaxation oscillator is equal to the reference frequency (1 MHz). The operation of the tuning circuit is described as follows: after reset, the 7-b reference and oscillator counters start counting until the reference counter reaches 64. At this time, the Up/Dn counter is clocked to count up or down or freeze according to the output of the digital comparator, which compares the con. The content of the tent of the oscillator counter with 7-b Up/Dn counter is then converted to an analog voltage to control the frequency of the oscillator (by controlling the value through in the CMD circuit). When the reference of
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Fig. 8.
Complete complex filter.
Fig. 9.
Frequency tuning circuit for a complex filter.
Fig. 10.
Frequency synthesizer block diagram.
counter overflows (reaches 128), it sends a reset signal to the oscillator counter to begin a new frequency comparison cycle based on the updated oscillator frequency. Eventually, the oscillator frequency will reach the reference frequency within an error depending on the digital-to-analog (D/A) resolution. The in the CMFB and the same control voltage is applied to bias circuits of the filter (Fig. 6) to tune the frequency to the correct value. A dead zone is added to the comparator transfer characteristic to avoid oscillation in the loop around the desired frequency. The width of the dead zone is three counter steps around the middle count. The maximum error in the frequency-tuning loop depends on D/A accuracy and the range of VCO control. For 30 process variations and 7-b D/A, the maximum frequency error is 0.23 . This error is mapped to only a 4.6-kHz error in the filter center frequency, which is quite tolerable for Bluetooth application. A nonsystematic error should also be added due to mismatches between the transconductance and capacitance in the filter and the oscillator. These mismatches can add roughly 1% error to the frequency tuning. This is equivalent to another 20 kHz in error in the center frequency of the filter, which is still within the range that a Bluetooth filter can tolerate. Guard rings are used to isolate the “noisy” tuning circuit from the filter. An RC LPF is used at the output of the tuning circuit
Fig. 11.
Charge pump schematic.
to further attenuate the noise. A 1-MHz tone was observed at the output of the filter at 20 dB below the noise floor. The areas occupied by the filter and the tuning circuit are 1.6 0.8-mm and 1 0.4-mm , respectively. The filter consumes 4.7 mA current while the tuning circuit current consumption is 0.8 mA. The measured IRR is 45 dB. The image side noise coming from the antenna and LNA is rejected by the complex filter. The noise
SHENG et al.: CMOS BLUETOOTH RECEIVER IC
Fig. 12.
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VCO with varactor array.
generated by the I and Q mixers is uncorrelated at the filter inputs. Half of this noise will be rejected by the filter (image side), while the other half will pass through the filter (signal side).
C. Frequency Synthesizer and VCO Fig. 13.
A 15/16 prescaler.
Fig. 14.
A 3/4 divider.
The frequency synthesizer uses an integer N architecture in order to generate the LO signal ranging from 2.404 to 2.481 GHz. Fig. 10 shows the block diagram of the frequency synthesizer. The reference frequency should be equal to the channel spacing of 1 MHz since the dividing modulus is integer. It is generated from an external 16-MHz crystal oscillator. Fig. 11 shows the schematic diagram of the charge pump. helps the current source to be The current mirror carrying turned off quickly by discharging the controlling node . In the absence of the bleed current sources M5–M6, the switching time of the current mirror depends on the time constant of the diode connected transistor M3, slowing down the operation of the charge pump and degrading the output waveform. The improved switching speed of the charge pump is obtained at the expense of quiescent power dissipation. However, this is justified as the pulse matching directly affects the spurious performance of the frequency synthesizer [13]. was fixed at The charge pump output current is 20 A. at 10 A. The small value of the current allows 30 A and having a large output resistance, improving the matching in the currents flowing through the current mirrors. A tradeoff between of the output transistors and the output range of the the output node is present in the design of the output stage of the charge pump. The phase noise of Bluetooth is implied to be 128 dBc/Hz at a 3-MHz offset frequency. Due to its stringent phase noise
requirement and relatively small tuning range (3.3%), the LC-tuned negative-resistance oscillator is the most suitable. One critical concern for the LC-tuned oscillator is that the narrow tuning range might be out of the desired band due to the technology process variations. Moreover, there is a serious tradeoff between the tuning range and the sensitivity. A wide tuning range is good for overcoming the process variations, but it increases the sensitivity of the frequency to control voltage noise due to increased gain. On the other hand, if the tuning range is decreased to make the frequency less sensitive to the control voltage noise, the VCO may not be able to cover enough frequency range to compensate for the process
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Fig. 15.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
Current steering NOR D Flip-flop.
Fig. 17.
(b
(a) Fig. 16. buffer.
Effect of VCO on the loop filter. (a) Without the buffer. (b) With the
variations. To solve this tradeoff, a discrete-tunable varactor array is introduced. As shown in Fig. 12, the varactor array consists of two parts: that is controlled by a large inversion-mode MOS varactor and three small MOS varactors controlled by the digital word . If the oscillation frequency range is out of the desired band due to process variations, the PLL will saturate the control voltage at its extreme value. When the control voltage reaches
Limiter and RSSI.
its maximum or minimum value, the digital word is decreased or increased so that the oscillation frequency band can be shifted is the only varactor that is directly conaccordingly. Since nected to the control voltage, the tuning sensitivity is determined only. However, the total tuning range is by the variation of and the remaining varactors decided by the combination of . Testing results show that, by using the discrete-tunable varactor array, the VCO can cover the range of 2380–2710 MHz while maintaining a VCO gain of less than 140 MHz/V. The design of the prescaler in the frequency synthesizer has to be optimized for maximum speed with minimum power consumption. Fig. 13 shows a 15/16 prescaler formed by a 3/4 divider and two divide-by-two flip flops. The 3/4 divider shown in Fig. 14 uses a combination of NOR gate and D flip-flops. A property of this configuration is that the fan-out of the flip-flops is smaller than that of more conventional architectures. Another advantage of this architecture is that both flip-flops are similar and only one design is needed. Several implementations can be used for the full speed flip-flops. The classical current steering is preferred over dynamic logic implementations because the power consumption can be reduced, due to the limited swing of the signals in the flip-flop. Fig. 15 shows a current steering1 NOR _D flip flop [14]. The NOR gate is merged with the input is set at the middle of the swing of the differential pair and input signals A and B. Only an extra transistor is added in parallel to one of the inputs of the FF1 (Fig. 14) to perform the 1Simulations showed that the flip-flop design can tolerate up to 30% decrease in g of transistors, and still operate properly.
SHENG et al.: CMOS BLUETOOTH RECEIVER IC
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(a)
(b Fig. 18. (a) Zero-crossing detector. (b) Proposed GFSK demodulator.
NOR operation. This means the same flip-flop can be used in the whole prescaler. The sizing of the transistors in the flip-flop is not straightforward. Since we have three stacked transistors, we need to carefully size the transistors in order to accommodate them within the power supply. At the same time, the transistor size has to be as small as possible to minimize the capacitance in each node to run the flip-flops at high frequency. The effect of the load has also to be considered during the sizing of the transistors. The tail current is 1 mA. The size of the transistors in the latches is smaller than that of the differential pairs to increase the speed of the flip-flop. When the loop filter is directly connected to the VCO control input, high-frequency signal from the VCO leaks back to the loop filter, overwhelming the control signal coming from the charge pump and preventing the synthesizer from locking. Fig. 16(a) shows the reason for such a leak. The control voltage of the VCO is connected to an inversion mode varactor. The gate and ), thus a of the varactor is the output of the VCO ( large high-frequency signal is present at the gate. Even though the control voltage node of the VCO is common for both outputs and , it is not a dc level. Small differences in amplitude and phase at the outputs of the VCO generate a high-frequency signal at this node. Inserting a buffer between the loop filter and the VCO solves the problem of the signal leaking to the loop filter, as shown in Fig. 16(b).
(a)
(b Fig. 19.
(a) ZD one-shot. (b) SK one-shot.
Fig. 20.
Format of the access code (trailer only exists in the data packet).
D. Limiter and GFSK Demodulator The employed limiter architecture is a cascaded structure of five voltage gain cells (Fig. 17), each cell consisting of an NMOS differential pair and NMOS loads provides 14 dB gain, which makes the overall gain 70 dB. A feedback-type offset cancellation mechanism is used to reduce the input offset voltage. A 26-dB RSSI is an integral part of the limiting amplifier. The signals at the output of each amplifying cell are rectified by multiplier-type rectifiers and summed up by resistors to provide a logarithmic output voltage [15]. As shown in Fig. 2, the I and Q outputs from two limiters feed the GFSK demodulator.
The proposed demodulator is based on the concept of a zerocrossing detector shown in Fig. 18(a). Fig. 18(b) shows the block diagram of the demodulator. The I and Q inputs come from the limiters. Two zero-crossing detection (ZD) one-shots emulate a differentiator in the demodulator. They detect the positive and negative zero crossing points of input I and Q signals and generate a narrow pulse (10 ns) at each zero-crossing moment. After the ZD one-shot, the pulses from both I and Q branches are combined together through OR gates and NOR gates. For
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Fig. 21.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
Block diagram of the dc offset cancellation and decision circuits. (a) Circuit and operation modes of the integrator/LPF block. (b) Clocks in the circuit.
(a)
(b) Fig. 22.
Integrator/LPF block. (a) Circuit and operation modes of the integrator/LPF block. (b) Clocks in the circuit.
the ZD one-shot circuit shown in Fig. 19(a), the timing capacitor, resistor, and the threshold of the digital gates determine the pulsewidth of the one-shot. Process variations and mismatches may cause different widths of the pulses generated by different one-shots, and this will affect the BER negatively. In order to eliminate the pulsewidth variation, another shape-keeping (SK) one-shot is used to recondition the pulses. The SK one-shot is shown in Fig. 19(b). R1–R3 form a voltage divider, providing a reference voltage. The pulsewidth at the output of the SK one-shot is determined mainly by the ratio of R1, R2, R3, and the value of resistor R5 and capacitor C2. The SK one-shot generates a new train of equal-width pulses (40 ns) corresponding to each pulse from ZD one-shots. For the SK one-shot to work properly, its pulsewidth should be larger than the pulsewidth of any ZD one-shot. On the other hand, an SK one-shot with a pulse that is too wide might cause overlapping of adjacent pulses
and degrade the performance. Therefore, a judicious choice of the pulsewidth is required to comply with the previous restrictions even with very large process variations and mismatch to assure robustness. The pulsewidth of SK one-shot is chosen to be larger than any of ZD one-shots even with very large process variations, thus, the demodulator is robust to process variations and mismatches. Using both I and Q branches, instead of a single branch, improves the performance of the demodulation due to the increased zero-crossing information per bit period. Since the active complex filter before the demodulator inherently has I and Q outputs, the extra silicon area and power consumption needed to build the two branches demodulator are moderate, while the performance is greatly improved. When the input Bluetooth modulated signal has the nominal modulation index of 0.32, for 1e-3 BER as specified in Bluetooth standard, only a 16.2-dB input SNR is required for the demodulator. When
SHENG et al.: CMOS BLUETOOTH RECEIVER IC
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(a)
Fig. 23.
Die microphotograph of Bluetooth receiver (6.25 mm ).
a Bluetooth modulated co-channel interference, which is 11.2 dB lower than the desired signal, is added to the signal, the measured BER is better than 1e-3. The demodulator consumes 3 mA of current, and no calibration is required. (b
E. Frequency Offset Cancellation Circuit Performance degradation caused by LO frequency drifting between the transmitter and receiver is a major concern in the design of a Bluetooth receiver. Given an indoor environment and limited mobility, the Doppler shift in the system is negligible in comparison with the LO frequency offset produced by inaccurate LOs. According to the Bluetooth specifications, the maximum LO frequency offset between two Bluetooth units can be 100 kHz, combining the transmitter-receiver LO offset and other frequency drifting. This amount equals almost 60% of the maximum frequency deviation provided by the GFSK modulation scheme. Using the proposed demodulator, this frequency offset is converted into a dc offset voltage. This considerable shift in the dc voltage severely increases the decision error in the bit detector and hence degrades the BER performance of the whole system. System-level simulations show that the dc offset has to be less than 10% of the peak-to-peak voltage of the demodulated signal to assure a good performance of the receiver. The last stage of the demodulator is used to cancel the dc offset and detect the received data bits. In each Bluetooth data packet, there are four preamble bits and four trailer bits in the access code, either in form of “0101” or “1010,” which average a zero dc offset (Fig. 20). By integrating either of those two segments, we can get an estimation of the existing dc offset and subtract it from the demodulated signal. Since a maximum 25 kHz frequency drifting is likely to occur in one time slot, the baseband circuit should be able to track this variation and adjust the subtracted offset voltage once the drifting exceeds
Fig. 24.
(a) Input return loss of receiver. (b) Phase noise of VCO.
Fig. 25.
VCO tuning range testing result.
certain threshold. In the circuit implementation, we change the operating mode of the circuit using switched-capacitor techniques. The dc offset cancellation circuit works as an integrator during the reception of the access code and as a very low-pass filter (20-kHz 3-dB BW) during the data packets transmission to track the possible frequency drifting. A switched-capacitor sample-and-hold circuit stores the offset voltage and feeds it back to a voltage subtractor (node 1, Fig. 21) to cancel the dc offset before the signal goes to the decision circuit. A complete
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 1, JANUARY 2003
(a) (a)
(b Fig. 26. (a) Noise spectrum at a complex filter output. (b) Complex filter frequency response for the signal and image sides.
(b Fig. 27. (a) IIP3 of the receiver. (b) Measured BER versus receiver input RF signal power.
circuit block diagram of the dc cancellation and decision circuit is shown in Fig. 21. One critical issue in the circuit design is the timing arrangement. Since the access code is at the beginning of the data packet, the dc cancellation circuit starts to integrate the incoming signal whenever the RF front end detects a power burst in the received signal. Signal synchronization at this stage is not very accurate, hence the dc offset estimation is not accurate either. Fine synchronization is achieved by calculating the autocorrelation of the sync word. Once the receiver clock is synchronized to the transmitter clock, we can integrate the trailer in the access code of a data packet to get an accurate dc offset estimation. Fig. 22 shows the operation modes and clocks of the integrator/LPF circuit. The decision circuit is an integrate-and-dump circuit. It is relatively immune to the timing error and hence has better performance than a simple sample-and-decision circuit. The bit detection is implemented by a latch comparator [16]. The total current consumption of the offset cancellation circuit is less than 1 mA. The circuit can handle frequency errors up to 150 kHz. IV. EXPERIMENTAL RESULTS The receiver IC is fabricated in TSMC 0.35- m standard CMOS process and packaged in a 48-pin TQFP plastic package.
It takes a 6.25-mm silicon area. The die microphotograph is shown in Fig. 23. The receiver active current is about 65 mA ( 2) of from a 3-V power supply. An unexpected low the on-chip inductors used in the VCO was obtained during the measurements. The problem is caused by the inadequate accuracy of the available simulator for on-chip spiral inductor simulations and the fact that several necessary parameters of the technology process needed for the simulation are not of available from MOSIS worsens the problem. The low on-chip spiral inductors forces extra current consumption of greater than VCO buffers during the measurements. For a 5, as expected, the total receiver current consumption would be below 45 mA. In Fig. 24(a), the measured input return loss of the receiver is less than 12 dB in the whole Bluetooth frequency band. In Fig. 24(b) the measured phase noise of the VCO at 1-, 2-, and 3-MHz offset at a 2.4-GHz center frequency are 118 dBc/Hz, 125 dBc/Hz, and 130 dBc/Hz, respectively. In Fig. 25, the measured VCO tuning range is shown. With the tunable varactor array, the VCO is able to cover the frequency range of 2380–2710 MHz, which is about 14% of the oscillation frequency. Fig. 26(a) shows the measured noise spectrum at the filter output, and the NF of receiver is 15 dB. Fig. 26(b) shows
SHENG et al.: CMOS BLUETOOTH RECEIVER IC
the complex filter frequency response for the signal and image side. The IRR is 45 dB. The filter attenuates the first and second adjacent channels by 27 and 58 dB on the signal side, respectively. The first adjacent channel at the image side is attenuated by 79 dB. The IIP3 was measured by applying to the input two 39-dBm interferers which are 3 and 6 MHz away from the desired Bluetooth signal. As shown in Fig. 27(a), the measured IIP3 of the receiver is 10 dBm. The measured receiver BER versus the input RF signal power is shown at Fig. 27(b). At a 1e-3 BER, the minimum detectable signal is 82 dBm. V. CONCLUSION The development of the proposed Bluetooth receiver followed a top-down approach. The system architecture was chosen and developed independently.2 Key building blocks not reported before, such as the active complex - filter and the mixed-mode GFSK demodulator, were proposed. All system and circuits were obtained within a period of 12 months. This is the first functional Bluetooth receiver IC designed independently in a university environment, using a low-cost standard CMOS process and meeting major specifications. The key performance measurements are 82 dBm sensitivity at 1e-3 BER, 10 dBm IIP3, and 15-dB noise figure. ACKNOWLEDGMENT The authors would like to thank the RF IC Design Group from Texas Instruments and the Wireless Subscriber Systems Group from Motorola for system and circuit design discussions. They also thank D. Hernández-Garduño and A. Valdés-García for their assistance in the layout and PCB design and S. Yan for technical discussions.
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[8] B. Razavi, RF Microelectronics. Englewood Cliffs, NJ: Prentice-Hall, 1998. [9] F. Behbahani, Y. Kishigami, J. Leete, and A. A. Abidi, “CMOS mixers and polyphase filters for large image rejection,” IEEE J. Solid-State Circuits, vol. 36, pp. 873–887, June 2001. [10] M. S. J. Steyaert, J. Janssens, B. D. Muer, M. Borremans, and N. Itoh, “A 2 V CMOS cellular transceiver front-end,” IEEE J. Solid-State Circuits, vol. 35, pp. 1895–1907, Dec. 2000. [11] D. K. Shaeffer and T. H. Lee, “A 1.5-V 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid State Circuits, vol. 32, pp. 745–759, May 1997. [12] P. Andreani, S. Mattisson, and B. Essink, “A CMOS gm-C polyphase filter with high image band rejection,” in Proc. 2000 26th Eur. SolidState Circuits Conf., Sept. 2000, pp. 244–247. [13] J. F. Parker and D. Ray, “A 1.6-GHz CMOS PLL with on-chip loop filter,” IEEE J. Solid-State Circuits, vol. 33, pp. 337–343, Mar. 1998. [14] C. Lam and B. Razavi, “A 2.6 GHz/ 5.2 GHz frequency synthesizer in 0.4 m CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, pp. 788–794, May 2000. [15] S. Khorram, A. Rofougaran, and A. A. Abidi, “A CMOS limiting amplifier and signal-strength indicator,” in Symp. VLSI Circuits Dig. Tech. Papers, 1995, pp. 95–96. [16] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.
Wenjun Sheng (S’97) was born in China in 1974. He received the B.S. degree in electronic engineering from Tsinghua University, Beijing, China, in 1996 and the M.E. and Ph.D. degrees in electrical engineering from Texas A&M University, College Station, in 1999 and 2002, respectively. From August 1998 to July 1999, he was with Texas Instruments, Inc., Dallas, TX, for his internship. He worked in the wireless baseband group and RF system group of Texas Instruments. Since April 2002, he has been with Qualcomm, Inc., San Diego, CA, as a senior RFIC design engineer. He is working on the design of RF and analog ICs for wireless communication applications. His research interests are focused on RF transceiver design for wireless communications and RF/analog IC design. Dr. Sheng is a corecipient of the 2002 Radio Frequency Integrated Circuits Symposium Best Student Paper Award.
REFERENCES [1] Bluetooth Specification Version 1.0 B. [2] A. Ajjkuttira, C. Leung, E. Khoo, M. Choke, R. Singh, T. Teo, B. Gheong, J. See, H. Yap, P. Leong, C. Law, M. Itoh, A. Yoshida, Y. Yoshida, A. Tamura, and H. Nakamura, “A fully-integrated CMOS RFIC for bluetooth applications,” in Proc. IEEE Int. Solid-State Circuits Conf., 2001, pp. 198–199. [3] F. O. Eynde, J.-J Schmit, V. Charlier, R. Alexandre, C. Sturman, K. Coffin, B. Mollekens, J. Craninckx, S. Terrijn, A. Monterastelli, S. Beerens, P. Goetschalcks, M. Ingels, D. Joos, S. Guncer, and A. Pontioglu, “A fully-integrated single-chip SOC for bluetooth,” in Proc. IEEE Int. Solid-State Circuits Conf., 2001, pp. 196–197. [4] H. Darabi, S. Khorram, E. Chien, M. Pan, S. Wu, S. Moloudi, J. C. Leete, J. Rael, M. Syed, R. Lee, B. Ibrahim, M. Rofougaran, and A. Rofougaran, “A 2.4 GHz CMOS transceiver for bluetooth,” IEEE J. Solid-State Circuits, vol. 36, pp. 2016–2024, Dec. 2001. [5] N. Filiol, N. Birkett, J. Cherry, F. Balteanu, C. Gojocaru, A. Namdar, T. Pamir, K. Sheikh, G. Glandon, D. Payer, A. Swaminathan, R. Forbes, T. Riley, S. M. Alinoor, E. Macrobbie, M. Cloutier, S. Pipilos, and T. Varelas, “A 22 mW bluetooth RF transceiver with direct RF modulation and on-chip IF filtering,” in Proc. IEEE Int. Solid-State Circuits Conf., 2001, pp. 202–203. [6] C. Durdodt, M. Friedrich, C. Grewing, M. Hammes, A. Hanke, S. Heinen, J. Oehm, D. Pham-Stabner, D. Seippel, D. Theil, S. V. Waasen, and E. Wagner, “The first very low-IF RX, 2-point modulation TX CMOS system on chip bluetooth solution,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., 2001, pp. 99–102. [7] W. Sheng, “Design and Implementation of CMOS Radio Frequency Receivers,” Ph.D. dissertation, Texas A&M University, 2002. 2Although Darabi et al. [4] reported a Bluetooth transceiver using a similar low-IF architecture, we independently also proposed the same architecture. Our silicon design was submitted in April 2001.
Bo Xia received the B.S. degree in electrical engineering from Shanghai Jiao Tong University, China, in 1997. He is currently working toward the Ph.D. degree in electrical engineering at Texas A&M University, College Station. From 1997 to 1998, he worked as a Staff Engineer at Hewlett Packard Co., Ltd. Since 1998, he has been a Research Assistant in the Analog and Mixed Signal Center, Texas A&M University. He held an internship at AGERE, Allentown, PA, from July 2002 to September 2002. His research includes RF transceiver systems and circuits design, ADC and AGC circuits design. Mr. Xia is a corecipient of the Best Student Paper Award on IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2002.
Ahmed A. Emira (S’00) was born in Cairo, Egypt, in 1974. He received the B.Sc. and M.Sc. degrees from Cairo University, Cairo, in 1997 and 1999, respectively. He is currently working toward the Ph.D. degree at Texas A&M University, College Station. He worked as a Teaching Assistant in the Department of Electrical and Computer Engineering, Cairo University, from July 1997 until December 1999. He has held an internship at Motorola, Austin, TX, from September 2001 to August 2002. His current interests include mixed-signal circuits, analog filter design, and communication system architectures. Mr. Emira received the third best student paper award in RFIC, Seattle, WA, 2002.
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Chunyu Xin (S’01) was born in Tianjin, China, in 1974. He received the M.S. degree from Nankai University, Tianjin, China, in 1999. He is currently working toward the Ph.D degree at Texas A&M University, College Station. His current research interests are integrated RF and IF circuits designs. Mr. Xin is a coauthor of the best conference student paper award received in Seattle, WA, June 2002.
Ari Yakov Valero-López (S’00) was born in Mexico City, Mexico, in 1972. He received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico, in 1996, and the M.Sc. degree from the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico, in 1998. He is currently working toward the Ph.D. degree at Texas A&M University, College Station. His current field of research is in the design and fabrication of analog and mixed-signal circuits and frequency synthesizers for communication systems. Mr. Valero-Lopez is a corecipient of the third best student paper award in RFIC, Seattle, WA, 2002.
Sung Tae Moon (S’00) was born in Busan, Korea, in 1974. He received the Bachelor of Engineering Degree from the Seoul National University, Seoul, Korea, in 1997. He is currently working toward the Ph.D. degree at Texas A&M University, College Station. His current interest of research is in the design and fabrication of analog and mixed-signal circuits and RF/MW oscillators for communication systems. Mr. Moon is a corecipient of the third best student paper award in RFIC, Seattle, WA, 2002.
Edgar Sánchez-Sinencio (S’72–M’74–SM’83– F’92) was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, in 1966, the M.S.E.E. degree from Stanford University, Stanford, CA, in 1970, and the Ph.D. degree from the University of Illinois at Urbana-Champaign in 1973. In 1974, he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983, he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983–1984. He is currently the TI J. Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He is coauthor of the book Switched Capacitor Circuits (New York: Van Nostrand-Reinhold, 1984) and coeditor of the book Low Voltage/Low-Power Integrated Circuits and Systems (Piscataway, NJ: IEEE Press, 1999). His present interests are in the area of RF-communication circuits and analog and mixed-mode circuit design. Dr. Sánchez-Sinencio was an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS (1985–1987) and an Associate Editor for the IEEE TRANSACTIONS ON NEURAL NETWORKS. He is the former Editor-in-Chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II. He is a former President of the IEEE Circuits and Systems Technical Committee on Neural Systems and Applications and CAS Technical Committee on Analog Signal Processing. In November 1995, he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico, the first honorary degree awarded for Microelectronic Circuit Design contributions. He received the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the corecipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He is currently the IEEE Circuits and Systems Society representative to the Solid-State Circuits Society (2000–2002). He is currently a member of the IEEE Solid-State Circuits Award Committee.
