midterm winter 2010
Student Name:
McGILL UNIVERSITY Electrical and Computer Engineering Department ECSE-323 DIGITAL SYSTEM DESIGN Winter 2010
MIDTERM EXAM Question
Maximum Points
1
15
2
10
3
10
4
15
5
20
6
5
Total
75
Points Attained
Please write down your name: __________________________________ Please write your student ID number: ___________________________ ______________________________________________________________ Instructions/Please read carefully! This is a closed book quiz. No books or notes are allowed. You may use a standard calculator. All work is to be done on the attached sheets and under no circumstance are booklets or loose sheets to be used. Write your name at the top of every sheet. Read the question carefully. If something appears ambiguous, write down your assumption. The points have been assigned according to the formula that 1 point = 1 exam minute, so please pace yourself accordingly.
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Question 1: Boolean Logic Theory (15 marks) Consider the following Boolean function: f(b,d,f,g,e) = bdg+b’dfg+b’d’g+bd’eg. a) Find the minimal SoP form of function f using the Quine-McCluskey method. Clearly state which are the essential prime implicants and prime implicants. b) Perform the factorization of the minimized SoP from part b). Try to get as small a form as possible. c) Perform the decomposition of the minimized function from part b). Solution a) We need to express f in terms of minterms. f(b,d,f,g,e) = bdg+b’dfg+b’d’g+bd’eg = bd(f+f’)g(e+e’) + b’dfg(e+e’) + b’d’(f+f’)g(e+e’) +bd’(f+f’)ge = bdfg(e+e’) + bdf’g(e+e’) + b’dfge + b’dfge’ + b’d’fg(e+e’) + b’d’f’g(e+e’) +bd’fge + bd’f’ge = bdfge + bdfge’ + bdf’ge + bdf’ge’ + b’dfge + b’dfge’ + b’d’fge + b’d’fge’ + b’d’f’ge + b’d’f’ge’ +bd’fge + bd’f’ge = Σ m(11111, 11110, 11011, 11010, 01111, 01110, 00111, 00110, 00011, 00010, 10111, 10011) = Σ m(00010, 00011, 00110, 00111, 01110, 01111, 10011, 10111,11010, 11011, 11110, 11111) Σ m(2, 3, 6, 7, 14, 15, 19, 23, 26, 27, 30, 31) 2 00010 ✔ -------------3 00011 ✔ 6 00110 ✔ -------------7 00111 ✔ 14 01110 ✔ 19 10011✔ 26 11010 ✔ -------------15 01111 ✔ 23 10111 ✔ 27 11011 ✔ 30 11110 ✔ ------------31 11111 ✔
(2,3) (2,6)
0001_✔ 00_10 ✔
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Student Name: ------------------(3,7) 00_11 ✔ (3,19) _0011 (6,7) 0011_ ✔ (6,14) 0_110 -----------------(7,15) 0_111 (7,23) _0111 (14,15) 0111_ (14,30) _1110 (19,23) 10_11 (19,27) 1_011 (26,27) 1101_ (26,30) 11_10 -----------------(15,31) _1111 (23,31) 1_111 (27,31) 11_11 (30,31) 1111_ (2,3,6,7) 00_1_ ------------------------(3,7,19,23) _0_11 (6,7,14,15) 0_11_ -------------------------(7,15,23,31) _ _111 (14,15,30,31) _ 111 _ (19,23,27,31) 1 _ _ 11 (26,27,30,31) 11_ 1_
Prime implicants are: {b’d’g, d’ge, b’fg, fge, dfg, bge, bdg}
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Implicant table: f(b,d,f,g,e) = Σ m(00010, 00011, 00110, 00111, 01110, 01111, 10011, 10111,11010, 11011, 11110, 11111) 00_1_ _0_11 0_11_ __111 _ 111_ 1 __11 11_ 1_
00010 ✔
00011 ✔ ✔
00110 ✔ ✔
00111 ✔ ✔ ✔ ✔
01110
01111
✔
✔ ✔ ✔
✔
10011
10111
✔
✔
11010
✔ ✔
b) Factored form is: g(d(b+f)+d’(b’+e)) c) Decomposition: f = gx x = d(b+f)+d’(b’+e)
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11110
11111
✔
✔ ✔ ✔
✔ ✔
Essential prime implicants are: 00_1_ and 11_1_. Minimal cover is: f(b,d,f,g,e) = b’d’g + d’ge + dfg + bdg
11011
✔ ✔
✔
Student Name:
Question 2: Application of Boolean Theory (10 marks)
€ €
Consider the following three Boolean functions: F(a,b,c,d) = ∑ m(2,3,5,7,8,9,10,11,13,15) , G(a,b,c,d) = ∑ m(2,3,5,6,7,10,11,14,15) and H(a,b,c,d) = ∑ m(6,7,8,9,13,14,15). a) While considering each of the functions individually, find their minimal cover using Karnaugh Maps. How many logic gates you would need to use to € implement the minimal covers of F, G and H? b) Again, minimize the three functions F, G and H using K-Maps. However, this time treat the problem as a 4-input (a,b,c,d) and three output (F,G,H) system. How many gates would you need to implement the system now? Hint: In the three individual K-Maps of functions F, G and H try to identify as common terms to at least two and possibly all three functions, and then share these terms in the covers of F, G and H.
Solution a) The solution requires 10 gates and 25 gate inputs.
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c) The 4-input (A,B,C,D) and three output (F,G,H) system requires 8 gates and 22 gate inputs.
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(Question 2 continued…)
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Question 3: CMOS Circuit Technology Design (10 marks)
€
Design a CMOS logic gate that implements the function: F = (A + C)(A + D)(B + D)(C + D) . First manipulate the original Boolean expression of the function F, such that the resulting implementation will have the minimal number of transistors. Draw the schematic, indicating which transistors belong to the pull-up and which to the pull-down network. Solution F = (A + C)(A + D)(B + D)(C + D) =(A + C) + (A + D) + (B + D) + (C + D) = AC + AD + BD + CD = A(C + D) + D(B + C).
€
Figure 1: CMOS Implementation
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(Question 3 continued…)
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Question 4: VHDL (10 marks) Consider a logic operator that can be either a buffer or an inverter. If a mode select line called MODE_CNTRL is set to ‘0’, then the output SIG_OUT equals the inverse of the input SIG_IN. If MODE_CNTRL is set to ‘1’, then the output SIG_OUT equals the input SIG_IN. a) Write a complete VHDL description using concurrent signal assignments of your choice. b) Rewrite the VHDL code. This time, create components describing a buffer, an inverter, and other needed hardware elements. Then write the complete description using your components.
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(Question 4 continued…)
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Question 5: Circuit Implementation Strategies (15 marks)
€
Consider the two functions F and G, given in the form of a minimal SoP: F(W , X,Y,Z) = W Y + XYZ and G(W , X,Y,Z) = W XY + XZ + W YZ . a) Implement the above two functions using ROM. b) Implement F and G with PLA using no more than four terms. c) Implement F and € G with PAL.
Solution a) The function is not in the form of the sum of minterms. First, we need to find its minterm representation. F(W , X,Y,Z) = ∑ m(5,8,9,12,13), G(W , X,Y,Z) = ∑ m(1,3,5,8,9,11), € €
Figure 2: ROM Implementation For PAL, we need to find a sum of products solution that uses only four different terms. The map below shows such a solution.
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The PAL below implements this four-term solution.
Figure 3: PLA Implementation PAL implementation is straight forward, as there are no restrictions on the hardware. For the implementation we use the minimized functions from part b).
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(question 5 continued…)
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Question 6: Circuit Implementation Strategies – LUT (5 marks) Implement the following 6-variable function Z(a,b,c,d,e, f ) = abcde f + abcde f + bcde f using 4-input LUTs. List inside each LUT the truth table it realizes. Solution € As the original function is of 6 variables we need to perform the Shannon decomposition to reduce the variable count. The first variable of the decomposition is a: Z = a’Z0 + aZ1.
Z0 = 0bcd’ef’ + 1b’c’def’ + b’cde’f = b’c’def’ + b’cde’f. Z1 = 1bcd’ef’ + 0b’c’def’ + b’cde’f = bcd’ef’ + b’cde’f . Next, Z0 and Z1 are expanded around variable b. Z00 is obtained by substituting 0 for b in Z0 Z00 = 1c’def’ + 1cde’f = c’def’ + cde’f. Z01 is obtained by substituting 1 for b in Z0: Z01 = 0c’def’ + 0cde’f = 0. Z10 is obtained by substituting 0 for b in Z1: Z10 = 0cd’ef’ + 1cde’f = cde’f. Z11 is obtained by substituting 1 for b in Z1: Z11 = 1cd’ef’ + 0cde’f = cd’ef’. Now Z can be written as: Z = a’Z0 + aZ1, Z0 = b’Z00 + bZ01, Z1 = b’Z10 + bZ11.
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Figure 4: LUT Implementation Note that each LUT implements the AND functions, so the contents of each LUT is 15 “0” and last “1”.
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(question 6 continued…)
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McGILL UNIVERSITY Electrical and Computer Engineering Department ECSE-323 DIGITAL SYSTEM DESIGN Winter 2010
MIDTERM EXAM Question
Maximum Points
1
15
2
10
3
10
4
15
5
20
6
5
Total
75
Points Attained
Please write down your name: __________________________________ Please write your student ID number: ___________________________ ______________________________________________________________ Instructions/Please read carefully! This is a closed book quiz. No books or notes are allowed. You may use a standard calculator. All work is to be done on the attached sheets and under no circumstance are booklets or loose sheets to be used. Write your name at the top of every sheet. Read the question carefully. If something appears ambiguous, write down your assumption. The points have been assigned according to the formula that 1 point = 1 exam minute, so please pace yourself accordingly.
Page 1 of 17
Student Name:
Question 1: Boolean Logic Theory (15 marks) Consider the following Boolean function: f(b,d,f,g,e) = bdg+b’dfg+b’d’g+bd’eg. a) Find the minimal SoP form of function f using the Quine-McCluskey method. Clearly state which are the essential prime implicants and prime implicants. b) Perform the factorization of the minimized SoP from part b). Try to get as small a form as possible. c) Perform the decomposition of the minimized function from part b). Solution a) We need to express f in terms of minterms. f(b,d,f,g,e) = bdg+b’dfg+b’d’g+bd’eg = bd(f+f’)g(e+e’) + b’dfg(e+e’) + b’d’(f+f’)g(e+e’) +bd’(f+f’)ge = bdfg(e+e’) + bdf’g(e+e’) + b’dfge + b’dfge’ + b’d’fg(e+e’) + b’d’f’g(e+e’) +bd’fge + bd’f’ge = bdfge + bdfge’ + bdf’ge + bdf’ge’ + b’dfge + b’dfge’ + b’d’fge + b’d’fge’ + b’d’f’ge + b’d’f’ge’ +bd’fge + bd’f’ge = Σ m(11111, 11110, 11011, 11010, 01111, 01110, 00111, 00110, 00011, 00010, 10111, 10011) = Σ m(00010, 00011, 00110, 00111, 01110, 01111, 10011, 10111,11010, 11011, 11110, 11111) Σ m(2, 3, 6, 7, 14, 15, 19, 23, 26, 27, 30, 31) 2 00010 ✔ -------------3 00011 ✔ 6 00110 ✔ -------------7 00111 ✔ 14 01110 ✔ 19 10011✔ 26 11010 ✔ -------------15 01111 ✔ 23 10111 ✔ 27 11011 ✔ 30 11110 ✔ ------------31 11111 ✔
(2,3) (2,6)
0001_✔ 00_10 ✔
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Student Name: ------------------(3,7) 00_11 ✔ (3,19) _0011 (6,7) 0011_ ✔ (6,14) 0_110 -----------------(7,15) 0_111 (7,23) _0111 (14,15) 0111_ (14,30) _1110 (19,23) 10_11 (19,27) 1_011 (26,27) 1101_ (26,30) 11_10 -----------------(15,31) _1111 (23,31) 1_111 (27,31) 11_11 (30,31) 1111_ (2,3,6,7) 00_1_ ------------------------(3,7,19,23) _0_11 (6,7,14,15) 0_11_ -------------------------(7,15,23,31) _ _111 (14,15,30,31) _ 111 _ (19,23,27,31) 1 _ _ 11 (26,27,30,31) 11_ 1_
Prime implicants are: {b’d’g, d’ge, b’fg, fge, dfg, bge, bdg}
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Implicant table: f(b,d,f,g,e) = Σ m(00010, 00011, 00110, 00111, 01110, 01111, 10011, 10111,11010, 11011, 11110, 11111) 00_1_ _0_11 0_11_ __111 _ 111_ 1 __11 11_ 1_
00010 ✔
00011 ✔ ✔
00110 ✔ ✔
00111 ✔ ✔ ✔ ✔
01110
01111
✔
✔ ✔ ✔
✔
10011
10111
✔
✔
11010
✔ ✔
b) Factored form is: g(d(b+f)+d’(b’+e)) c) Decomposition: f = gx x = d(b+f)+d’(b’+e)
Page 4 of 17
11110
11111
✔
✔ ✔ ✔
✔ ✔
Essential prime implicants are: 00_1_ and 11_1_. Minimal cover is: f(b,d,f,g,e) = b’d’g + d’ge + dfg + bdg
11011
✔ ✔
✔
Student Name:
Question 2: Application of Boolean Theory (10 marks)
€ €
Consider the following three Boolean functions: F(a,b,c,d) = ∑ m(2,3,5,7,8,9,10,11,13,15) , G(a,b,c,d) = ∑ m(2,3,5,6,7,10,11,14,15) and H(a,b,c,d) = ∑ m(6,7,8,9,13,14,15). a) While considering each of the functions individually, find their minimal cover using Karnaugh Maps. How many logic gates you would need to use to € implement the minimal covers of F, G and H? b) Again, minimize the three functions F, G and H using K-Maps. However, this time treat the problem as a 4-input (a,b,c,d) and three output (F,G,H) system. How many gates would you need to implement the system now? Hint: In the three individual K-Maps of functions F, G and H try to identify as common terms to at least two and possibly all three functions, and then share these terms in the covers of F, G and H.
Solution a) The solution requires 10 gates and 25 gate inputs.
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c) The 4-input (A,B,C,D) and three output (F,G,H) system requires 8 gates and 22 gate inputs.
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(Question 2 continued…)
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Question 3: CMOS Circuit Technology Design (10 marks)
€
Design a CMOS logic gate that implements the function: F = (A + C)(A + D)(B + D)(C + D) . First manipulate the original Boolean expression of the function F, such that the resulting implementation will have the minimal number of transistors. Draw the schematic, indicating which transistors belong to the pull-up and which to the pull-down network. Solution F = (A + C)(A + D)(B + D)(C + D) =(A + C) + (A + D) + (B + D) + (C + D) = AC + AD + BD + CD = A(C + D) + D(B + C).
€
Figure 1: CMOS Implementation
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(Question 3 continued…)
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Question 4: VHDL (10 marks) Consider a logic operator that can be either a buffer or an inverter. If a mode select line called MODE_CNTRL is set to ‘0’, then the output SIG_OUT equals the inverse of the input SIG_IN. If MODE_CNTRL is set to ‘1’, then the output SIG_OUT equals the input SIG_IN. a) Write a complete VHDL description using concurrent signal assignments of your choice. b) Rewrite the VHDL code. This time, create components describing a buffer, an inverter, and other needed hardware elements. Then write the complete description using your components.
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(Question 4 continued…)
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Question 5: Circuit Implementation Strategies (15 marks)
€
Consider the two functions F and G, given in the form of a minimal SoP: F(W , X,Y,Z) = W Y + XYZ and G(W , X,Y,Z) = W XY + XZ + W YZ . a) Implement the above two functions using ROM. b) Implement F and G with PLA using no more than four terms. c) Implement F and € G with PAL.
Solution a) The function is not in the form of the sum of minterms. First, we need to find its minterm representation. F(W , X,Y,Z) = ∑ m(5,8,9,12,13), G(W , X,Y,Z) = ∑ m(1,3,5,8,9,11), € €
Figure 2: ROM Implementation For PAL, we need to find a sum of products solution that uses only four different terms. The map below shows such a solution.
Page 12 of 17
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The PAL below implements this four-term solution.
Figure 3: PLA Implementation PAL implementation is straight forward, as there are no restrictions on the hardware. For the implementation we use the minimized functions from part b).
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(question 5 continued…)
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Question 6: Circuit Implementation Strategies – LUT (5 marks) Implement the following 6-variable function Z(a,b,c,d,e, f ) = abcde f + abcde f + bcde f using 4-input LUTs. List inside each LUT the truth table it realizes. Solution € As the original function is of 6 variables we need to perform the Shannon decomposition to reduce the variable count. The first variable of the decomposition is a: Z = a’Z0 + aZ1.
Z0 = 0bcd’ef’ + 1b’c’def’ + b’cde’f = b’c’def’ + b’cde’f. Z1 = 1bcd’ef’ + 0b’c’def’ + b’cde’f = bcd’ef’ + b’cde’f . Next, Z0 and Z1 are expanded around variable b. Z00 is obtained by substituting 0 for b in Z0 Z00 = 1c’def’ + 1cde’f = c’def’ + cde’f. Z01 is obtained by substituting 1 for b in Z0: Z01 = 0c’def’ + 0cde’f = 0. Z10 is obtained by substituting 0 for b in Z1: Z10 = 0cd’ef’ + 1cde’f = cde’f. Z11 is obtained by substituting 1 for b in Z1: Z11 = 1cd’ef’ + 0cde’f = cd’ef’. Now Z can be written as: Z = a’Z0 + aZ1, Z0 = b’Z00 + bZ01, Z1 = b’Z10 + bZ11.
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Figure 4: LUT Implementation Note that each LUT implements the AND functions, so the contents of each LUT is 15 “0” and last “1”.
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(question 6 continued…)
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