Mipro2012 Proceedings - Semantic Scholar
The simple CMOS negative capacitance with improved frequency response Boško Mrković*, Martina Ašenbrener** *
Tehnoalarm d.o.o. Zagreb, Croatia University of Rijeka/Department of Informatics, Rijeka, Croatia E-mail: [email protected], [email protected]
**
Abstract - The negative capacitance circuits are very interesting analog building blocks with many possible applications like the compensation of undesired parasitic capacitance, bandwidth enhancement of amplifiers, equalization filters design without passive inductors, etc. This paper presents a method for improving and controlling CMOS floating negative capacitance frequency response. Since the negative capacitance is generated by the simple and known negative impedance converter (NIC), the proposed method is applicable for negative inductance and resistance also. The proposed method is simulated and verified using standard 0.35µm and 0.18µm CMOS processes.
I.
INTRODUCTION
The negative capacitance circuits or negative capacitance generators (NCG) are very useful analogue building blocks, used for numerous different applications enabling: •
•
The improvement of existing structures, through the compensation of undesired parasitic capacitance, like bandwidth enhancement of various kind of amplifiers [6], [7], speed enhancement of some DAC architectures, improvement of ESD protection circuits [3], improvement of active inductor design [1], [4], etc. The design of new circuit architectures like the new compact equalization filters, new RC and LC oscillator structures etc.
There are many different possibilities for grounded or floating negative capacitance generation, mostly known for decays. Generally, any well known negative impedance converter (NIC), which employs operational amplifiers or current conveyors, can be used. Negative capacitance generated using such an approach is accurate, with a large allowed signal swing. The disadvantages are that such an approach requires a large area and increased power, especially for floating capacitor generation, and mostly performs with poor higher frequency limit. There are also several known simple structures which can be used as a floating NCG, like a common source amplifier with cross-coupled capacitors and source’s parallel R-C pairs [2]; or a very effective NCG known as
MIPRO 2012/MEET
the relaxation generator, with cross-coupled MOSFETs, described in [3]. Although the last structure generates a negative resistance as well as a negative capacitance and performs with an inevitable noise figure and some linearity degradation, it is quite simple, offers great possibilities for improvements and control and was therefore chosen for the presented analysis and design. II.
IMPLEMENTATION
A. A Generalized Negative Capacitance As it is mentioned previously, a simple way to generate a floating negative capacitor is by using a crosscoupled pair of transistors in order to create a positive feedback. v1
Zeq
v2
i1
i2
M1
M2 C
I
I
Figure 1. The simple negative capacitance generator
The positive feedback loop formed by transistors M1 and M2 makes a difference in the output currents to have an opposite polarity to the differential voltage. Thus, the equivalent output impedance has a negative value. From the small signal analysis of the proposed circuit, after disregarding the channel length modulation, the equivalent impedance is given by
Z equ = −
1 g m + s (CGS + 2C ) sC g m − sCGS
(1)
As long as f
Tehnoalarm d.o.o. Zagreb, Croatia University of Rijeka/Department of Informatics, Rijeka, Croatia E-mail: [email protected], [email protected]
**
Abstract - The negative capacitance circuits are very interesting analog building blocks with many possible applications like the compensation of undesired parasitic capacitance, bandwidth enhancement of amplifiers, equalization filters design without passive inductors, etc. This paper presents a method for improving and controlling CMOS floating negative capacitance frequency response. Since the negative capacitance is generated by the simple and known negative impedance converter (NIC), the proposed method is applicable for negative inductance and resistance also. The proposed method is simulated and verified using standard 0.35µm and 0.18µm CMOS processes.
I.
INTRODUCTION
The negative capacitance circuits or negative capacitance generators (NCG) are very useful analogue building blocks, used for numerous different applications enabling: •
•
The improvement of existing structures, through the compensation of undesired parasitic capacitance, like bandwidth enhancement of various kind of amplifiers [6], [7], speed enhancement of some DAC architectures, improvement of ESD protection circuits [3], improvement of active inductor design [1], [4], etc. The design of new circuit architectures like the new compact equalization filters, new RC and LC oscillator structures etc.
There are many different possibilities for grounded or floating negative capacitance generation, mostly known for decays. Generally, any well known negative impedance converter (NIC), which employs operational amplifiers or current conveyors, can be used. Negative capacitance generated using such an approach is accurate, with a large allowed signal swing. The disadvantages are that such an approach requires a large area and increased power, especially for floating capacitor generation, and mostly performs with poor higher frequency limit. There are also several known simple structures which can be used as a floating NCG, like a common source amplifier with cross-coupled capacitors and source’s parallel R-C pairs [2]; or a very effective NCG known as
MIPRO 2012/MEET
the relaxation generator, with cross-coupled MOSFETs, described in [3]. Although the last structure generates a negative resistance as well as a negative capacitance and performs with an inevitable noise figure and some linearity degradation, it is quite simple, offers great possibilities for improvements and control and was therefore chosen for the presented analysis and design. II.
IMPLEMENTATION
A. A Generalized Negative Capacitance As it is mentioned previously, a simple way to generate a floating negative capacitor is by using a crosscoupled pair of transistors in order to create a positive feedback. v1
Zeq
v2
i1
i2
M1
M2 C
I
I
Figure 1. The simple negative capacitance generator
The positive feedback loop formed by transistors M1 and M2 makes a difference in the output currents to have an opposite polarity to the differential voltage. Thus, the equivalent output impedance has a negative value. From the small signal analysis of the proposed circuit, after disregarding the channel length modulation, the equivalent impedance is given by
Z equ = −
1 g m + s (CGS + 2C ) sC g m − sCGS
(1)
As long as f
