Modeling and simulation of a new Bridgeless ... - Semantic Scholar
Simulation Modelling Practice and Theory 19 (2011) 599–611
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Modeling and simulation of a new Bridgeless SEPIC power factor correction circuit Mohd Rodhi Sahid ⇑, Abdul Halim Mohd Yatim Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Malaysia
a r t i c l e
i n f o
Article history: Received 13 May 2010 Received in revised form 20 September 2010 Accepted 20 September 2010 Available online 8 October 2010 Keywords: Bridgeless PFC SEPIC DCM Small-signal model Large-signal model
a b s t r a c t A new Bridgeless PFC circuit based on Single-Ended Primary Inductance Converter (SEPIC) is proposed in this paper. The new topology has less component count and less conducted component during each mode of operation within one switching period. The small-signal and steady-state model of the circuit operated in Discontinuous Conduction Mode (DCM) is derived using the Current Injected Equivalent Circuit Approach (CIECA). The large-signal model based on state-space and switch model are also developed to verify the large-signal behavior. The simulation results of the proposed converter show that the output voltage of the proposed converter is successfully regulated to its desired value while the input current regulation is inherent. Ó 2010 Elsevier B.V. All rights reserved.
1. Introduction Power Factor Correction (PFC) circuits are usually comprised of an AC to DC converter with the capability to improve the power factor at the mains. Normally, the PFC circuit is performed by means of a bridge rectifier circuit and a DC–DC converter but some circuit performs this solution without the full-bridge rectifier circuit. This kind of circuit topology is known as the Bridgeless PFC circuit which proposed by Mitchell [1] in 1983 based on the conventional Boost PFC circuit. As shown in Fig. 1a, the Bridgeless PFC circuit consists of two MOSFETs; M1 and M2, two diodes; D1 and D2, an input inductor; L, and output capacitor; C. On the other hand, Fig. 1b shows the circuit topology for the conventional Boost PFC circuit which consist of a full-bridge rectifier and a Boost DC–DC converter. It is obvious that the Bridgeless topology is developed by replacing the lower-part diode rectifier circuit in the conventional Boost PFC circuit with two MOSFETs. As a result, the MOSFET and the output diode in the Boost converter can be eliminated, while the Boost inductor is relocated at the input side. In the Bridgeless PFC, both MOSFETs are sharing the same control signal and the detail operation of this converter can be obtained in [1]. The Bridgeless PFC circuit is also known as dual-Boost converter due to the similarity of its equivalent circuit with the DC–DC Boost converter during positive and negative half-line cycle. It is found that the number of diodes in Bridgeless PFC (i.e. during ON and OFF state) is less compared to the conventional Boost PFC topology, thus would result in lower conduction losses and hence giving higher efficiency to the whole circuit. Several modifications to this topology have been performed in order to improve the performance of the Bridgeless topology such as reducing the common-mode noise existing in conventional bridgeless PFC [2–5]. Thus, due to the above mentioned characteristics, the Bridgeless PFC circuit is a good candidate for a high-efficiency converter. Beside the bridgeless Boost converter, it is found that other types of converter topologies can also be used to perform the bridgeless PFC such as SEPIC [6,11], Buck [7] and Half-Bridge [8] converter. Among these three topologies, only the SEPIC topology has an inductor at the input side, similar to Boost topology, which is the main ⇑ Corresponding author. Tel.: +60 75535829; fax: +60 75566272. E-mail address: [email protected] (M.R. Sahid). 1569-190X/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.simpat.2010.09.004
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Fig. 1. Schematic diagram of (a) the Bridgeless PFC circuit and (b) the conventional Boost PFC circuit.
factor to obtain high power factor and low current distortion. As reported by Texas Instruments [9], it is found that the performance of SEPIC converter surpasses the Flyback converter in several key issues such as the overall circuit efficiency, switching stress and capability to operate in Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). In DCM, the SEPIC converter has two significant advantages as PFC circuits [10] which are: (a) input current will naturally follow the input voltage, thus no current loop is required and (b) isolation can be achieved easily through the second inductor. Recently, a new Bridgeless PFC based on SEPIC converter has been proposed in [11]. This topology is a combination of two DC–DC SEPIC converters to operate as a single-phase single-stage PFC circuit without input bridge rectifier. The two MOSFETs can be triggered using the same control signal and thus, it is classified as a single-stage converter [12]. However, a gatedrive circuit with transformer isolation is required to drive the two MOSFETs due to its high-side driving characteristics. In addition, two output capacitors at two different terminals are required to filter out the output voltage ripple. As a result, the resistive load is floating which means that both output terminals are not referred to a common ground node of the converter. This feature at the output terminal is not preferred for most application. It is also found that the number of components conducted at each half-line cycle is eleven which is considered high. In this paper, a new Single-phase Single-stage Bridgeless PFC based on SEPIC converter is proposed. The proposed converter is simpler compared to the Bridgeless SEPIC PFC circuit proposed in [11] while improving several key aspects such as: (a) only one output capacitor is required and the resistive load is not floating, (b) driving the MOSFETs gate terminal is simpler due to low-side driver capability in which a gate-drive with transformer is not required, and (c) less number of components operated at each half-line cycle of input voltage. First, the subinterval modes of the proposed converter are identified with the aid of equivalent circuit and voltage/current waveforms. Then, based on these two results, the small-signal model is developed using Current Injected Equivalent Circuit Approach (CIECA) [14,15] in order to design the closed-loop Proportional–Integral (PI) controller. At the same time, PLECS/Matlab is used to verify the small-signal model obtained from CIECA method. Finally, large-signal switch models based on state-space equations are developed using MATLAB/Simulink and SABER simulator to verify the large-signal behavior. 2. Operating principles of the proposed Bridgeless PFC converter The proposed Bridgeless PFC circuit diagram is depicted in Fig. 2a. The equivalent circuit during positive and negative half-line cycle is shown in Fig. 2b and c respectively. At positive half-line cycle, all components will conduct except Ds1, S2, C2, L3 and Do2, while at negative half-line cycle Ds2, S1, C1, L2 and Do1 will not conduct. Accumulatively, only eight components will be conducted at each half-line cycle compared to eleven in the bridgeless SEPIC converter proposed in [11]. From this point of view, the proposed circuit will have greater possibilities to perform better in terms of efficiency due to less conducted components. Although two sets of circuit exist for a complete input voltage cycle, analysis will be carried out only for its positive halfline cycle due to the fact that the same analysis can be carried out during the negative half-line cycle. For high-frequency model, it is assumed that the input voltage is constant within each switching period although it is a well known fact that the magnitude of the sinusoidal input voltage is varied from zero to its peak value and goes back to zero within each half-line cycle. This assumption is made due to the difference between the input mains period and the switching period is very large such that the input voltage seems to be a constant value within each switching period. However, this assumption will only valid for the high-frequency model which will be derived in the next section. The lowfrequency model which is vital in modeling PFC circuit will take into account the sinusoidal wave-shape of the input voltage. On top of that, the analysis will be done with all the inductors operated in DCM. As discussed in [13], the capability of any PFC converter to correct the power factor (i.e. to reshape the input current to sinusoidal and in-phase with the input voltage)
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Fig. 2. (a) The proposed Bridgeless SEPIC PFC circuit, operated at (b) positive half-line cycle, and (c) negative half-line cycle.
is inherent if the circuit is fully operated in DCM. As a consequence, the Voltage Follower control method is the most suitable control method for this new converter due to its simplicity which are: (1) only voltage mode control at the output is required and (2) no input current sensor is needed. Throughout the analysis, by assuming that all components are ideal, three modes of subinterval operations within one switching period, TS, have been identified. The equivalent circuit of each mode and the key waveforms of several important components are shown in Figs. 3 and 4 respectively. The operation of each mode can be detailed as follows: (a) MODE 1 (d1TS): At the beginning of this mode, the two MOSFETs are turned on. Although both MOSFETs are driven by the same control signal, only S1 and Ds2 will conduct to create a current path for the circuit. Then, L1 and L2 will be charged linearly by the input voltage, Vg and the intermediate capacitor, Cb1 respectively through S1 and Ds2. Within this period, the output diode, Do1 will not conduct and the output voltage remains constant and can be represented as, vO = iOR.
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Fig. 3. (a) Equivalent circuit during MODE 1 (d1TS), (b) equivalent circuit during MODE 2 (d2TS), and (c) equivalent circuit during MODE 3 (d3TS).
(b) MODE 2 (d2TS): As can be seen, the two MOSFETs are turned off while the output diode Do1 will conduct. Both inductors (L1 and L2) and Vg will transfer its energy to the output capacitor, Co and the load. Meanwhile, the intermediate capacitor will be charged as well. The diode Ds2 will continue to conduct to create the current path to the mains. At the beginning of this point, the voltage and current stress at each component can be calculated easily by referring to slope equation in Fig. 4. (c) MODE 3 (d3TS): Finally, all semiconductor devices will turn off except Ds2 due to small amount of DC current still flowing through it. Since this DC current amount is very small, it can be simply neglected throughout the analysis. On top of that, this DC current does not contribute to the small-signal modeling that intended to be developed in this work. On the load side, the voltage and current characteristic is similar with MODE 1.
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Fig. 4. The theoretical waveforms within one switching period.
3. Small-signal and steady-state model Small-signal and steady-state modeling are vital in designing the closed-loop control and to determine the required parameters of the proposed converter. As mentioned earlier, the proposed circuit will operate in DCM. Therefore, the CIECA method is used to obtain the small-signal model of the proposed converter as well as the steady-state model. This method is very much suitable to model any power converters operated in DCM. In order to perform the small-signal analysis, the average input inductor current and the output diode current equation within one switching period, TS, is our main concern. As shown in Fig. 4, the analysis starts by obtaining the mathematical representation of the current slope for several key components namely, L1, Cb1, L2 and Co. From these currents, as far as the CIECA method is concerned, the average current within each switching period injected inward and outward the converter is obtained. In this case, the input current is iL1 and the output current is iDo1. As depicted in Fig. 4, the average current for L1 within each switching period can be represented as,
iL1AVGTs ¼
v g ðd1 þ d2 Þd1 T S
ð3:1Þ
2L1
while for the output diode, iDo1, the average current is 2
iDo1AVGTs ¼
d2 T S 2
v Cb1 þ v 0 v g v O L1
þ
L2
ð3:2Þ
where d1 is the duty cycle or the ON time of the MOSFETs, d2 is the time where the inductor current ascending and falls to zero and TS is switching period. Again, by examining the inductor current at L1, it is found that the ripple current during d1TS and d1TS are equal. Thus,
DiL1ðd1TsÞ ¼ DiL1ðd2TsÞ vg ðv Cb1 þ v O v g Þ ðd1 T S Þ ðd2 T S Þ ¼ 0 L1 L1 and this equation can be further rearranged to
d2 ¼
vg ðv Cb1 þ v O v g Þ
d1
ð3:3Þ
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Within one switching cycle, it is found that v Cb1 ¼ v g , and the average voltage or the volt-second value across L1 and L2 are equal to zero. Therefore, the average voltage within Ts for both inductors are equal, (i.e. v L1AVG ¼ v L2AVG ). Thus, Eq. (3.3) can be further simplified to
d2 ¼
vg d vO 1
ð3:4Þ
and, by substituting Eq. (3.4) to (3.1) and (3.2), the average input and output equations within half-line period without the d2 terms are 2
iL1AVGTs ¼
d1 T S 2
v g ðv O þ v g Þ v O L1
; and
ð3:5Þ
2
iDo1AVGTs ¼
d1 T S v 2g 2v 0 La
ð3:6Þ
where La = L1//L2. Furthermore, since the converter performs as a PFC converter, the low-frequency model is our main concern which shows the small-signal characteristic at input mains frequency. From this point of view, the input voltage, vg is not a constant value anymore whereas it now becomes a sinusoidal waveform represented as, v g ¼ v m j sinðxtÞj within each half-line period (TL = p rad). Thus, by integrating both input and output average current equations (Eqs. (3.5) and (3.6)), within half-line period, it is found that
iL1AVGTL ¼
1
p
iDo1AVGTL ¼
Z p 2 d1 T S v g ðv O þ v g Þ v m d21 T S v O v m dxt ¼ þ 2 v O L1 v O L1 p 4 0
1
p
Z p 2 d1 T S v 2g v 2 d2 T S dxt ¼ m 1 : 2v 0 La 4v O La 0
ð3:7Þ
ð3:8Þ
In order to derive the small-signal model, small perturbations are introduced to the variables in Eqs. (3.7) and (3.8) such ^1 , iL1 ¼ IL1 þ ^iL1 ; v O ¼ V O þ v ^ m ; d1 ¼ D1 þ d ^ O and iDo1 ¼ IDo1 þ ^iDo1 . Then, by eliminating the nonlinear terms, that v m ¼ V m þ v the ac small-signal equations become,
^ ^iL1 ¼ 1 v^ m þ j d ^ 1 1 g1v O r1
ð3:9Þ
1 ^ ^iDo1 ¼ g v^ m þ j d v^ O 2 2 1 þ r2
ð3:10Þ
where 1 r1
¼ 4pTVSO L1 ð4D21 V O þ 2pD21 V m Þ;
j1 ¼ 4pTL1S V O ð8V m D1 V O þ 2pV 2m D1 Þ; 2 D2 T g 1 ¼ 4L1 1S VVmO ; D2 T g 2 ¼ 2L1 aS VVmO ; 2 Vm S D1 j2 ¼ T2L ; VO a 2 D2 T 1 ¼ 4L1 aS VVmO r2
ð3:11Þ
These equations are then used to configure the small-signal equivalent circuit of the proposed converter for positive half-line cycle, as shown in Fig. 5. By referring to the figure, the input-to-output and the control-to-output transfer function for the proposed converter can be further derived as
Fig. 5. Small-signal equivalent circuit for the proposed converter.
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v^ O g2 ¼ v^ m d^ ¼0 sC O þ 1 þ 1 1
R
ð3:12Þ
r2
v^ O
j2 ¼ ^1 1 d sC þ þ r12 O v^ m ¼0 R
ð3:13Þ
On the other hand, another important parameter in any DC–DC converter is the voltage conversion ratio, M, which represents the relationship between output voltage and the input voltage. From Eq. (3.6), it is found that the average value of the output diode current is equal to the output current. Thus, 2
iDo1AVGTs ¼
d1 T S v 2g ¼ i0 2v 0 La
in which the output load current is iO ¼ vRO . Therefore, by substituting iO to Eq. (3.6), it is found that
vO R
2
¼
d1 T S v 2g 2v 0 La
and further, the voltage conversion ratio, M, can be represented as
vO M¼ ¼d vg 1
sffiffiffiffiffiffiffiffi RT S 2La
ð3:14Þ
With full DCM operation of the circuit, the summation of duty ratio values should satisfy
d1 þ d2 < 1
ð3:15Þ
throughout the complete half-line cycle. Then, by substituting (3.4)–(3.15),
d1 þ
vg ðv Cb1 þ v O v g Þ
d1 < 1
and can be further simplified to
d1
K
ð3:18Þ
qffiffiffiffiffiffi
2La and KCRIT = 1 d1. As a conclusion, Eq. (3.18) should be satisfied in all condition to ensure DCM operation. where K ¼ RT S Other important parameter that should be taken care of is the components stress especially for the MOSFETs and the diodes. By evaluating the peak current flowing through L1 and L2, it is found that
iL1peak ¼
d1 T S v m L1
ð3:19Þ
iL2peak ¼
d1 T S v CB1 L2
ð3:20Þ
Again, by analyzing Figs. 3 and 4, the peak current through the MOSFET and output diode can be easily obtained as the summation of peak current at both inductors,
iS1peak ¼ iDo1peak ¼ iL1peak þ iL2peak ¼ d1 T S
v m v CB1 L1
þ
L2
ð3:21Þ
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M.R. Sahid, A.H.M. Yatim / Simulation Modelling Practice and Theory 19 (2011) 599–611 Table 1 Design parameters for the proposed circuit. Parameters
Values
Input peak voltage, Vm L1 L2 and L3 Bulk capacitor, CB1 and CB2 Output voltage, Vout Switching frequency, fS Duty ratio, D1 Rated output power, Po Output capacitor, CO
140–340 V 150 lH 70 lH 1 lF 50 V DC 50 kHz 0.1–0.25 100 W 1410 lF
Bode Diagram 60
Vm=340V Vm=240V Vm=160V Vm=100V
Magnitude (dB)
50 40 30 20 10
Phase (deg)
0 0
Vm=340V Vm=240V Vm=160V Vm=100V -45
-90 -1 10
0
1
10
2
10
3
10
10
Frequency (Hz) Fig. 6. Variations of the magnitude and the phase plot with input voltage changes.
60
A1 40
Amplitude / dB Phase / degree
20
B1
0 -20
A2 -40 -60 -80 -100 0 10
B2 1
2
10
10
3
10
Frequency (Hz) Fig. 7. Control-to-output bode-plot obtained using CIECA (A1 &A2) and using Matlab/PLECS simulator (B1&B2).
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1 rL1 Dot Product4 2 Vin
1 s
diL1/dt
3 L1
1 iL1
iL1
Integrator
Divide2
5 rL2
0 Switch
const
Dot Product1
4 d
3 iL2
1 s Switch2
8 L2
iL2
Integrator2
Divide1
-1 Gain1
1 s
Switch3
9 CB1
Divide4
vCB1
Integrator3 2 vCo 1 s
Switch1 Divide3
-1
Gain
Vco
Integrator1
Vco
6 Cout 7 Rload
Divide Fig. 8. Large-signal model of the proposed converter.
8
Vg
6 4 2 0 -2 -4
IL1
-6 -8 0.3
0.31
0.32
0.33
0.34
0.35
0.36
0.37
0.38
0.39
0.4
Time [sec] Fig. 9. Simulation results for input current, IL1 (1A/div) and input voltage, Vg (50 V/div), waveforms.
4. Simulation results In order to obtain the design parameters for the proposed circuit, Eqs. (3.14) and (3.17) are used. All the circuit parameters should be determined at first place such that it will suit the requirement of the input and output of the converter. Thus, only the duty ratio and inductors value will be the unknown parameters for the circuit. However, since we have these two equations, the value of desired duty ratio and inductors can be easily calculated and are shown in Table 1. The input voltage
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is simulated with two values which are 140 V (100 Vrms) and 340 V (240 Vrms) to represent the capability of the proposed converter working with universal input voltage, while the output voltage should be regulated at fixed 50 V DC. The control-to-output transfer function of the proposed converter represented in Eq. (3.13) is used to observe the openloop bode-plot which is vital in designing the closed-loop control. Fig. 6 shows the variation of the control-to-output bodeplot when the amplitude of the sinusoidal input voltage (vm) is varied from 4 V to 340 V using the quasi-steady-state approach. In PFC, the quasi-steady-state approach is very important in order to determine the variation of magnitude and phase plot with the changes of the input voltage. From Fig. 6, it is found that the only different of the several magnitude plots is only on the gain. For larger input voltage, the gain is slightly bigger. However, the phase plots are all similar. In order to verify the small-signal model in Eq. (3.13), Matlab/PLECS is used. As depicted in Fig. 7, the control-to-output bode-plot generated from Matlab/PLECS (B1&B2) is obtained using the switch model and control-to-output blockset. It can be seen that the amplitude and phase plot for both results shows a good agreement. It is a rule of thumb for PFC circuit to have the output voltage controller bandwidth to be lower than twice the line frequency, namely 100 Hz, in order to avoid input current distortion. Thus, the bandwidth of the controller must be designed
(a) 12 10 8
Vout IL1
6 4 2 0 -2 -4 -6 0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time [sec]
(b)
5
4
3
2
1
0
-1 0.605
0.605
0.605
0.6051
0.6051
0.6051
0.6051
0.6051
0.6052
0.6052
0.6052
Time [sec] Fig. 10. Simulation results of the (a) input current, IL1 (1A/div), and output voltage, Vout (5 V/div) response with load variations (50 W–100 W–50 W) and (b) the input current waveforms for each switching period with Vm = 340 V.
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below this frequency for better performance. By using PI controller, the zero is located at 34 Hz with 27 Hz bandwidth and 80° phase margin such that the transfer function of the PI controller with output voltage divider gain becomes
v C ðsÞ 1:044ðs þ 212:77Þ : ¼ s v ERR ðsÞ
ð4:1Þ
On the other hand, the state equations and the output equations of the proposed converter are used to develop the largesignal model of the proposed converter. These equations can be derived from Fig. 3 and are used to obtain the current slope in Fig. 4. Only state equations for MODE 1 and MODE 2 are used to develop the large-signal model while MODE 3 is inherent due to DCM operations. Thus, the state equations and output equation for MODE 1 are,
diL1 v g diL2 v Cb1 diCb1 v Cb1 vO ; and iO ¼ ¼ ; ¼ ¼ dt L1 dt L2 dt L2 R while for MODE 2,
diL1 diL1 v g v Cb1 v O diL2 vO diCO v g v Cb1 v O v O ; and : ¼ ¼ ¼ ¼ dt dt L1 dt L2 dt L1 L2 By using these equations, the large-signal model is constructed using MATLAB/Simulink as shown in Fig. 8. This particular method used to develop the large-signal model in this work is discussed in detail in [16]. In large-signal model, the input current and output voltage response of the converter with the designed PI controller are observed. The PI controller will sense and compare the output voltage with the reference value and further generate the desired control signal to the MOSFETs. In order to verify the model proposed in this work, a complete switch model is also developed using SABER simulator. The simulation result of the input current with respect to the input voltage is shown in Fig. 9. It is obvious that besides having in-phase with the input voltage, the input current is also rigidly follows the wave-shape of the input voltage. The input current and output voltage response is depicted in Fig. 10a when a set of step load change from 50 W to 100 W and switch back to 50 W at t = 0.4 s and 0.8 s respectively, is applied to the circuit. It can be seen that the capability to reshape and regulate the input current is inherent when the PFC circuit operates in DCM. At the same time, the output voltage is regulated at 50 V DC with 0.1 s settling time for both load disturbances. The output voltage ripple is 5% for 50 W load and
Fig. 11. Simulation results of the (a) input current and (b) output voltage response with load variations (50 W–100 W–50 W) using SABER simulator for Vm = 340 V.
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ascending to 8% for 100 W load. Fig. 10b shows the input current waveform within each switching period operated in DCM with its peak value recorded slightly less than 4 A. For comparison, a switch model for the proposed converter is developed in SABER with similar parameters. The result in SABER as shown in Fig. 11 justifies the capability of the converter to reshape the input current and regulate the output voltage at 50 V DC. Fig. 12a shows the input current and output voltage response with the same load changes (50 W–100 W–50 W) at 140 V peak input voltage. It shows that the circuit is capable to cater with universal input voltage. As can be seen, the current response also shows a good regulation and comparable with the current response shown in Fig. 10a. The same goes to the output voltage waveform whereby it is successfully being regulated at 50 V DC with almost the same response as Fig. 10a but with slightly bigger overshoot. However, as shown in Fig. 12b, the width of input current waveform within each switching period is almost twice compared to the current shown in Fig. 10c. This is due to the fact that in order to maintain the same input power, larger input current should be drawn from the mains if the input peak voltage is reduced from 340 V to 140 V. Again, the results in SABER for 140 V peak, as depicted in Fig. 13, shows a good agreement between the developed model and the switch model.
(a) 12 10 8
Vout IL1
6 4 2 0 -2 -4 -6 0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time [sec]
(b)
5
4
3
2
1
0
-1 0.605
0.605
0.605
0.6051
0.6051
0.6051
0.6051
0.6051
0.6052
0.6052
0.6052
Time [sec] Fig. 12. Simulation results of the (a) input current, IL1 (1A/div), and output voltage, Vout (5 V/div) response with load variations (50 W–100 W–50 W) and (b) the input current waveforms for each switching period with Vm = 140 V.
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Fig. 13. Simulation results of the (a) input current and (b) output voltage response with load variations (50 W–100 W–50 W) using SABER simulator for Vm = 140 V.
5. Conclusion The small-signal and steady state analysis of the proposed converter has been derived using CIECA method. It is found that these models are vital in knowing the dynamic characteristics and the appropriate parameters of the proposed converter operated in DCM. The simulation results show that the proposed converter is able to work as a simple PFC circuit with the capability to regulate the output voltage over a wide range of load values and with universal input voltage conditions. The SABER simulator is used to obtain the results in a complete switch model and further verify the model developed in SIMULINK using CIECA approach. References [1] D.M. Mitchell, AC–DC converter having an improved power factor, US Patent 4412277, 1983. [2] Bin Su, Zhengyu Lu, An interleaved totem-pole boost bridgeless rectifier with reduced reverse-recovery problems for power factor correction, IEEE Transactions on Power Electronics 25 (6) (2010) 1406–1415. [3] K. Mino, H. Matsumoto, S. Fujita, Y. Nemoto, D. Kawasaki, R. Yamada, N. Tawada, Novel bridgeless PFC converters with low inrush current stress and high efficiency, in: International Power Electronics Conference (IPEC), 2010, pp. 1733–1739. [4] L. Huber, Y. Jang, M.M. Jovanovic, Performance evaluation of Bridgeless PFC Boost rectifiers, IEEE Transactions on Power Electronics 23 (3) (2008) 1381– 1390. [5] W.Y. Choi, J.M. Kwon, E.H. Kim, J.J. Lee, B.H. Kwon, Bridgeless Boost rectifier with low conduction losses and reduced diode reverse-recovery problems, IEEE Transactions on Industrial Electronics 54 (2) (2007) 769–780. [6] A.J. Sabzali , E.H. Ismail, M.A. Al-Saffar, A.A. Fardoun, A new bridgeless PFC Sepic and Cuk rectifiers with low conduction and switching losses, in: International Conference on Power Electronics and Drive Systems, 2009, pp. 550–556. [7] Yungtaek Jang, M.M. Jovanovic, Bridgeless buck PFC rectifier, in: Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010, pp. 23–29. [8] Woo-Young Choi, Wen-Song Yu, Jih-Sheng Lai, A novel bridgeless single-stage half-bridge AC/DC converter, in: Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010, pp. 42–46. [9] J. Betten, R. Kollman, Converter face-off: SEPIC vs Flyback, in: EE Times Asia Magazine, 2007. [10] D.S.L. Simonetti, J. Sebastian, J. Uceda, The discontinuous conduction mode Sepic and Cuk power factor preregulators: analysis and design, IEEE Transactions on Industrial Electronics 44 (5) (1997) 630–637. [11] E.H. Ismail, Bridgeless SEPIC rectifier with unity power factor and reduced conduction losses, IEEE Transactions on Industrial Electronics 56 (4) (2009) 1147–1157. [12] C.K. Tse, Circuit theory of power factor correction in switching converters, International Journal of Circuit Theory and Applications 31 (2) (2003) 157– 198. [13] W. Huai, I. Batarseh I, Comparison of basic converter topologies for power factor correction, in: IEEE Proceedings Southeastcon, 1998, pp. 348–353. [14] P.R.K. Chetty, Current injected equivalent circuit approach to modeling switching DC–DC converters, IEEE Transactions on Aerospace and Electronic Systems 17 (6) (1981) 802–808. [15] P.R.K. Chetty, Current injected equivalent circuit approach to modeling of switching DC–DC converters in discontinuous inductor conduction mode, IEEE Transactions on Industrial Electronics 29 (3) (1982) 230–234. [16] J.H. Su, J.J. Chen, D.S. Wu, Learning feedback controller design of switching converters via MATLAB/SIMULINK, IEEE Transactions on Education 45 (4) (2002) 307–315.
Contents lists available at ScienceDirect
Simulation Modelling Practice and Theory journal homepage: www.elsevier.com/locate/simpat
Modeling and simulation of a new Bridgeless SEPIC power factor correction circuit Mohd Rodhi Sahid ⇑, Abdul Halim Mohd Yatim Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Skudai, Malaysia
a r t i c l e
i n f o
Article history: Received 13 May 2010 Received in revised form 20 September 2010 Accepted 20 September 2010 Available online 8 October 2010 Keywords: Bridgeless PFC SEPIC DCM Small-signal model Large-signal model
a b s t r a c t A new Bridgeless PFC circuit based on Single-Ended Primary Inductance Converter (SEPIC) is proposed in this paper. The new topology has less component count and less conducted component during each mode of operation within one switching period. The small-signal and steady-state model of the circuit operated in Discontinuous Conduction Mode (DCM) is derived using the Current Injected Equivalent Circuit Approach (CIECA). The large-signal model based on state-space and switch model are also developed to verify the large-signal behavior. The simulation results of the proposed converter show that the output voltage of the proposed converter is successfully regulated to its desired value while the input current regulation is inherent. Ó 2010 Elsevier B.V. All rights reserved.
1. Introduction Power Factor Correction (PFC) circuits are usually comprised of an AC to DC converter with the capability to improve the power factor at the mains. Normally, the PFC circuit is performed by means of a bridge rectifier circuit and a DC–DC converter but some circuit performs this solution without the full-bridge rectifier circuit. This kind of circuit topology is known as the Bridgeless PFC circuit which proposed by Mitchell [1] in 1983 based on the conventional Boost PFC circuit. As shown in Fig. 1a, the Bridgeless PFC circuit consists of two MOSFETs; M1 and M2, two diodes; D1 and D2, an input inductor; L, and output capacitor; C. On the other hand, Fig. 1b shows the circuit topology for the conventional Boost PFC circuit which consist of a full-bridge rectifier and a Boost DC–DC converter. It is obvious that the Bridgeless topology is developed by replacing the lower-part diode rectifier circuit in the conventional Boost PFC circuit with two MOSFETs. As a result, the MOSFET and the output diode in the Boost converter can be eliminated, while the Boost inductor is relocated at the input side. In the Bridgeless PFC, both MOSFETs are sharing the same control signal and the detail operation of this converter can be obtained in [1]. The Bridgeless PFC circuit is also known as dual-Boost converter due to the similarity of its equivalent circuit with the DC–DC Boost converter during positive and negative half-line cycle. It is found that the number of diodes in Bridgeless PFC (i.e. during ON and OFF state) is less compared to the conventional Boost PFC topology, thus would result in lower conduction losses and hence giving higher efficiency to the whole circuit. Several modifications to this topology have been performed in order to improve the performance of the Bridgeless topology such as reducing the common-mode noise existing in conventional bridgeless PFC [2–5]. Thus, due to the above mentioned characteristics, the Bridgeless PFC circuit is a good candidate for a high-efficiency converter. Beside the bridgeless Boost converter, it is found that other types of converter topologies can also be used to perform the bridgeless PFC such as SEPIC [6,11], Buck [7] and Half-Bridge [8] converter. Among these three topologies, only the SEPIC topology has an inductor at the input side, similar to Boost topology, which is the main ⇑ Corresponding author. Tel.: +60 75535829; fax: +60 75566272. E-mail address: [email protected] (M.R. Sahid). 1569-190X/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.simpat.2010.09.004
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Fig. 1. Schematic diagram of (a) the Bridgeless PFC circuit and (b) the conventional Boost PFC circuit.
factor to obtain high power factor and low current distortion. As reported by Texas Instruments [9], it is found that the performance of SEPIC converter surpasses the Flyback converter in several key issues such as the overall circuit efficiency, switching stress and capability to operate in Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). In DCM, the SEPIC converter has two significant advantages as PFC circuits [10] which are: (a) input current will naturally follow the input voltage, thus no current loop is required and (b) isolation can be achieved easily through the second inductor. Recently, a new Bridgeless PFC based on SEPIC converter has been proposed in [11]. This topology is a combination of two DC–DC SEPIC converters to operate as a single-phase single-stage PFC circuit without input bridge rectifier. The two MOSFETs can be triggered using the same control signal and thus, it is classified as a single-stage converter [12]. However, a gatedrive circuit with transformer isolation is required to drive the two MOSFETs due to its high-side driving characteristics. In addition, two output capacitors at two different terminals are required to filter out the output voltage ripple. As a result, the resistive load is floating which means that both output terminals are not referred to a common ground node of the converter. This feature at the output terminal is not preferred for most application. It is also found that the number of components conducted at each half-line cycle is eleven which is considered high. In this paper, a new Single-phase Single-stage Bridgeless PFC based on SEPIC converter is proposed. The proposed converter is simpler compared to the Bridgeless SEPIC PFC circuit proposed in [11] while improving several key aspects such as: (a) only one output capacitor is required and the resistive load is not floating, (b) driving the MOSFETs gate terminal is simpler due to low-side driver capability in which a gate-drive with transformer is not required, and (c) less number of components operated at each half-line cycle of input voltage. First, the subinterval modes of the proposed converter are identified with the aid of equivalent circuit and voltage/current waveforms. Then, based on these two results, the small-signal model is developed using Current Injected Equivalent Circuit Approach (CIECA) [14,15] in order to design the closed-loop Proportional–Integral (PI) controller. At the same time, PLECS/Matlab is used to verify the small-signal model obtained from CIECA method. Finally, large-signal switch models based on state-space equations are developed using MATLAB/Simulink and SABER simulator to verify the large-signal behavior. 2. Operating principles of the proposed Bridgeless PFC converter The proposed Bridgeless PFC circuit diagram is depicted in Fig. 2a. The equivalent circuit during positive and negative half-line cycle is shown in Fig. 2b and c respectively. At positive half-line cycle, all components will conduct except Ds1, S2, C2, L3 and Do2, while at negative half-line cycle Ds2, S1, C1, L2 and Do1 will not conduct. Accumulatively, only eight components will be conducted at each half-line cycle compared to eleven in the bridgeless SEPIC converter proposed in [11]. From this point of view, the proposed circuit will have greater possibilities to perform better in terms of efficiency due to less conducted components. Although two sets of circuit exist for a complete input voltage cycle, analysis will be carried out only for its positive halfline cycle due to the fact that the same analysis can be carried out during the negative half-line cycle. For high-frequency model, it is assumed that the input voltage is constant within each switching period although it is a well known fact that the magnitude of the sinusoidal input voltage is varied from zero to its peak value and goes back to zero within each half-line cycle. This assumption is made due to the difference between the input mains period and the switching period is very large such that the input voltage seems to be a constant value within each switching period. However, this assumption will only valid for the high-frequency model which will be derived in the next section. The lowfrequency model which is vital in modeling PFC circuit will take into account the sinusoidal wave-shape of the input voltage. On top of that, the analysis will be done with all the inductors operated in DCM. As discussed in [13], the capability of any PFC converter to correct the power factor (i.e. to reshape the input current to sinusoidal and in-phase with the input voltage)
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Fig. 2. (a) The proposed Bridgeless SEPIC PFC circuit, operated at (b) positive half-line cycle, and (c) negative half-line cycle.
is inherent if the circuit is fully operated in DCM. As a consequence, the Voltage Follower control method is the most suitable control method for this new converter due to its simplicity which are: (1) only voltage mode control at the output is required and (2) no input current sensor is needed. Throughout the analysis, by assuming that all components are ideal, three modes of subinterval operations within one switching period, TS, have been identified. The equivalent circuit of each mode and the key waveforms of several important components are shown in Figs. 3 and 4 respectively. The operation of each mode can be detailed as follows: (a) MODE 1 (d1TS): At the beginning of this mode, the two MOSFETs are turned on. Although both MOSFETs are driven by the same control signal, only S1 and Ds2 will conduct to create a current path for the circuit. Then, L1 and L2 will be charged linearly by the input voltage, Vg and the intermediate capacitor, Cb1 respectively through S1 and Ds2. Within this period, the output diode, Do1 will not conduct and the output voltage remains constant and can be represented as, vO = iOR.
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Fig. 3. (a) Equivalent circuit during MODE 1 (d1TS), (b) equivalent circuit during MODE 2 (d2TS), and (c) equivalent circuit during MODE 3 (d3TS).
(b) MODE 2 (d2TS): As can be seen, the two MOSFETs are turned off while the output diode Do1 will conduct. Both inductors (L1 and L2) and Vg will transfer its energy to the output capacitor, Co and the load. Meanwhile, the intermediate capacitor will be charged as well. The diode Ds2 will continue to conduct to create the current path to the mains. At the beginning of this point, the voltage and current stress at each component can be calculated easily by referring to slope equation in Fig. 4. (c) MODE 3 (d3TS): Finally, all semiconductor devices will turn off except Ds2 due to small amount of DC current still flowing through it. Since this DC current amount is very small, it can be simply neglected throughout the analysis. On top of that, this DC current does not contribute to the small-signal modeling that intended to be developed in this work. On the load side, the voltage and current characteristic is similar with MODE 1.
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Fig. 4. The theoretical waveforms within one switching period.
3. Small-signal and steady-state model Small-signal and steady-state modeling are vital in designing the closed-loop control and to determine the required parameters of the proposed converter. As mentioned earlier, the proposed circuit will operate in DCM. Therefore, the CIECA method is used to obtain the small-signal model of the proposed converter as well as the steady-state model. This method is very much suitable to model any power converters operated in DCM. In order to perform the small-signal analysis, the average input inductor current and the output diode current equation within one switching period, TS, is our main concern. As shown in Fig. 4, the analysis starts by obtaining the mathematical representation of the current slope for several key components namely, L1, Cb1, L2 and Co. From these currents, as far as the CIECA method is concerned, the average current within each switching period injected inward and outward the converter is obtained. In this case, the input current is iL1 and the output current is iDo1. As depicted in Fig. 4, the average current for L1 within each switching period can be represented as,
iL1AVGTs ¼
v g ðd1 þ d2 Þd1 T S
ð3:1Þ
2L1
while for the output diode, iDo1, the average current is 2
iDo1AVGTs ¼
d2 T S 2
v Cb1 þ v 0 v g v O L1
þ
L2
ð3:2Þ
where d1 is the duty cycle or the ON time of the MOSFETs, d2 is the time where the inductor current ascending and falls to zero and TS is switching period. Again, by examining the inductor current at L1, it is found that the ripple current during d1TS and d1TS are equal. Thus,
DiL1ðd1TsÞ ¼ DiL1ðd2TsÞ vg ðv Cb1 þ v O v g Þ ðd1 T S Þ ðd2 T S Þ ¼ 0 L1 L1 and this equation can be further rearranged to
d2 ¼
vg ðv Cb1 þ v O v g Þ
d1
ð3:3Þ
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Within one switching cycle, it is found that v Cb1 ¼ v g , and the average voltage or the volt-second value across L1 and L2 are equal to zero. Therefore, the average voltage within Ts for both inductors are equal, (i.e. v L1AVG ¼ v L2AVG ). Thus, Eq. (3.3) can be further simplified to
d2 ¼
vg d vO 1
ð3:4Þ
and, by substituting Eq. (3.4) to (3.1) and (3.2), the average input and output equations within half-line period without the d2 terms are 2
iL1AVGTs ¼
d1 T S 2
v g ðv O þ v g Þ v O L1
; and
ð3:5Þ
2
iDo1AVGTs ¼
d1 T S v 2g 2v 0 La
ð3:6Þ
where La = L1//L2. Furthermore, since the converter performs as a PFC converter, the low-frequency model is our main concern which shows the small-signal characteristic at input mains frequency. From this point of view, the input voltage, vg is not a constant value anymore whereas it now becomes a sinusoidal waveform represented as, v g ¼ v m j sinðxtÞj within each half-line period (TL = p rad). Thus, by integrating both input and output average current equations (Eqs. (3.5) and (3.6)), within half-line period, it is found that
iL1AVGTL ¼
1
p
iDo1AVGTL ¼
Z p 2 d1 T S v g ðv O þ v g Þ v m d21 T S v O v m dxt ¼ þ 2 v O L1 v O L1 p 4 0
1
p
Z p 2 d1 T S v 2g v 2 d2 T S dxt ¼ m 1 : 2v 0 La 4v O La 0
ð3:7Þ
ð3:8Þ
In order to derive the small-signal model, small perturbations are introduced to the variables in Eqs. (3.7) and (3.8) such ^1 , iL1 ¼ IL1 þ ^iL1 ; v O ¼ V O þ v ^ m ; d1 ¼ D1 þ d ^ O and iDo1 ¼ IDo1 þ ^iDo1 . Then, by eliminating the nonlinear terms, that v m ¼ V m þ v the ac small-signal equations become,
^ ^iL1 ¼ 1 v^ m þ j d ^ 1 1 g1v O r1
ð3:9Þ
1 ^ ^iDo1 ¼ g v^ m þ j d v^ O 2 2 1 þ r2
ð3:10Þ
where 1 r1
¼ 4pTVSO L1 ð4D21 V O þ 2pD21 V m Þ;
j1 ¼ 4pTL1S V O ð8V m D1 V O þ 2pV 2m D1 Þ; 2 D2 T g 1 ¼ 4L1 1S VVmO ; D2 T g 2 ¼ 2L1 aS VVmO ; 2 Vm S D1 j2 ¼ T2L ; VO a 2 D2 T 1 ¼ 4L1 aS VVmO r2
ð3:11Þ
These equations are then used to configure the small-signal equivalent circuit of the proposed converter for positive half-line cycle, as shown in Fig. 5. By referring to the figure, the input-to-output and the control-to-output transfer function for the proposed converter can be further derived as
Fig. 5. Small-signal equivalent circuit for the proposed converter.
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v^ O g2 ¼ v^ m d^ ¼0 sC O þ 1 þ 1 1
R
ð3:12Þ
r2
v^ O
j2 ¼ ^1 1 d sC þ þ r12 O v^ m ¼0 R
ð3:13Þ
On the other hand, another important parameter in any DC–DC converter is the voltage conversion ratio, M, which represents the relationship between output voltage and the input voltage. From Eq. (3.6), it is found that the average value of the output diode current is equal to the output current. Thus, 2
iDo1AVGTs ¼
d1 T S v 2g ¼ i0 2v 0 La
in which the output load current is iO ¼ vRO . Therefore, by substituting iO to Eq. (3.6), it is found that
vO R
2
¼
d1 T S v 2g 2v 0 La
and further, the voltage conversion ratio, M, can be represented as
vO M¼ ¼d vg 1
sffiffiffiffiffiffiffiffi RT S 2La
ð3:14Þ
With full DCM operation of the circuit, the summation of duty ratio values should satisfy
d1 þ d2 < 1
ð3:15Þ
throughout the complete half-line cycle. Then, by substituting (3.4)–(3.15),
d1 þ
vg ðv Cb1 þ v O v g Þ
d1 < 1
and can be further simplified to
d1
K
ð3:18Þ
qffiffiffiffiffiffi
2La and KCRIT = 1 d1. As a conclusion, Eq. (3.18) should be satisfied in all condition to ensure DCM operation. where K ¼ RT S Other important parameter that should be taken care of is the components stress especially for the MOSFETs and the diodes. By evaluating the peak current flowing through L1 and L2, it is found that
iL1peak ¼
d1 T S v m L1
ð3:19Þ
iL2peak ¼
d1 T S v CB1 L2
ð3:20Þ
Again, by analyzing Figs. 3 and 4, the peak current through the MOSFET and output diode can be easily obtained as the summation of peak current at both inductors,
iS1peak ¼ iDo1peak ¼ iL1peak þ iL2peak ¼ d1 T S
v m v CB1 L1
þ
L2
ð3:21Þ
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M.R. Sahid, A.H.M. Yatim / Simulation Modelling Practice and Theory 19 (2011) 599–611 Table 1 Design parameters for the proposed circuit. Parameters
Values
Input peak voltage, Vm L1 L2 and L3 Bulk capacitor, CB1 and CB2 Output voltage, Vout Switching frequency, fS Duty ratio, D1 Rated output power, Po Output capacitor, CO
140–340 V 150 lH 70 lH 1 lF 50 V DC 50 kHz 0.1–0.25 100 W 1410 lF
Bode Diagram 60
Vm=340V Vm=240V Vm=160V Vm=100V
Magnitude (dB)
50 40 30 20 10
Phase (deg)
0 0
Vm=340V Vm=240V Vm=160V Vm=100V -45
-90 -1 10
0
1
10
2
10
3
10
10
Frequency (Hz) Fig. 6. Variations of the magnitude and the phase plot with input voltage changes.
60
A1 40
Amplitude / dB Phase / degree
20
B1
0 -20
A2 -40 -60 -80 -100 0 10
B2 1
2
10
10
3
10
Frequency (Hz) Fig. 7. Control-to-output bode-plot obtained using CIECA (A1 &A2) and using Matlab/PLECS simulator (B1&B2).
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1 rL1 Dot Product4 2 Vin
1 s
diL1/dt
3 L1
1 iL1
iL1
Integrator
Divide2
5 rL2
0 Switch
const
Dot Product1
4 d
3 iL2
1 s Switch2
8 L2
iL2
Integrator2
Divide1
-1 Gain1
1 s
Switch3
9 CB1
Divide4
vCB1
Integrator3 2 vCo 1 s
Switch1 Divide3
-1
Gain
Vco
Integrator1
Vco
6 Cout 7 Rload
Divide Fig. 8. Large-signal model of the proposed converter.
8
Vg
6 4 2 0 -2 -4
IL1
-6 -8 0.3
0.31
0.32
0.33
0.34
0.35
0.36
0.37
0.38
0.39
0.4
Time [sec] Fig. 9. Simulation results for input current, IL1 (1A/div) and input voltage, Vg (50 V/div), waveforms.
4. Simulation results In order to obtain the design parameters for the proposed circuit, Eqs. (3.14) and (3.17) are used. All the circuit parameters should be determined at first place such that it will suit the requirement of the input and output of the converter. Thus, only the duty ratio and inductors value will be the unknown parameters for the circuit. However, since we have these two equations, the value of desired duty ratio and inductors can be easily calculated and are shown in Table 1. The input voltage
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is simulated with two values which are 140 V (100 Vrms) and 340 V (240 Vrms) to represent the capability of the proposed converter working with universal input voltage, while the output voltage should be regulated at fixed 50 V DC. The control-to-output transfer function of the proposed converter represented in Eq. (3.13) is used to observe the openloop bode-plot which is vital in designing the closed-loop control. Fig. 6 shows the variation of the control-to-output bodeplot when the amplitude of the sinusoidal input voltage (vm) is varied from 4 V to 340 V using the quasi-steady-state approach. In PFC, the quasi-steady-state approach is very important in order to determine the variation of magnitude and phase plot with the changes of the input voltage. From Fig. 6, it is found that the only different of the several magnitude plots is only on the gain. For larger input voltage, the gain is slightly bigger. However, the phase plots are all similar. In order to verify the small-signal model in Eq. (3.13), Matlab/PLECS is used. As depicted in Fig. 7, the control-to-output bode-plot generated from Matlab/PLECS (B1&B2) is obtained using the switch model and control-to-output blockset. It can be seen that the amplitude and phase plot for both results shows a good agreement. It is a rule of thumb for PFC circuit to have the output voltage controller bandwidth to be lower than twice the line frequency, namely 100 Hz, in order to avoid input current distortion. Thus, the bandwidth of the controller must be designed
(a) 12 10 8
Vout IL1
6 4 2 0 -2 -4 -6 0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time [sec]
(b)
5
4
3
2
1
0
-1 0.605
0.605
0.605
0.6051
0.6051
0.6051
0.6051
0.6051
0.6052
0.6052
0.6052
Time [sec] Fig. 10. Simulation results of the (a) input current, IL1 (1A/div), and output voltage, Vout (5 V/div) response with load variations (50 W–100 W–50 W) and (b) the input current waveforms for each switching period with Vm = 340 V.
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609
below this frequency for better performance. By using PI controller, the zero is located at 34 Hz with 27 Hz bandwidth and 80° phase margin such that the transfer function of the PI controller with output voltage divider gain becomes
v C ðsÞ 1:044ðs þ 212:77Þ : ¼ s v ERR ðsÞ
ð4:1Þ
On the other hand, the state equations and the output equations of the proposed converter are used to develop the largesignal model of the proposed converter. These equations can be derived from Fig. 3 and are used to obtain the current slope in Fig. 4. Only state equations for MODE 1 and MODE 2 are used to develop the large-signal model while MODE 3 is inherent due to DCM operations. Thus, the state equations and output equation for MODE 1 are,
diL1 v g diL2 v Cb1 diCb1 v Cb1 vO ; and iO ¼ ¼ ; ¼ ¼ dt L1 dt L2 dt L2 R while for MODE 2,
diL1 diL1 v g v Cb1 v O diL2 vO diCO v g v Cb1 v O v O ; and : ¼ ¼ ¼ ¼ dt dt L1 dt L2 dt L1 L2 By using these equations, the large-signal model is constructed using MATLAB/Simulink as shown in Fig. 8. This particular method used to develop the large-signal model in this work is discussed in detail in [16]. In large-signal model, the input current and output voltage response of the converter with the designed PI controller are observed. The PI controller will sense and compare the output voltage with the reference value and further generate the desired control signal to the MOSFETs. In order to verify the model proposed in this work, a complete switch model is also developed using SABER simulator. The simulation result of the input current with respect to the input voltage is shown in Fig. 9. It is obvious that besides having in-phase with the input voltage, the input current is also rigidly follows the wave-shape of the input voltage. The input current and output voltage response is depicted in Fig. 10a when a set of step load change from 50 W to 100 W and switch back to 50 W at t = 0.4 s and 0.8 s respectively, is applied to the circuit. It can be seen that the capability to reshape and regulate the input current is inherent when the PFC circuit operates in DCM. At the same time, the output voltage is regulated at 50 V DC with 0.1 s settling time for both load disturbances. The output voltage ripple is 5% for 50 W load and
Fig. 11. Simulation results of the (a) input current and (b) output voltage response with load variations (50 W–100 W–50 W) using SABER simulator for Vm = 340 V.
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ascending to 8% for 100 W load. Fig. 10b shows the input current waveform within each switching period operated in DCM with its peak value recorded slightly less than 4 A. For comparison, a switch model for the proposed converter is developed in SABER with similar parameters. The result in SABER as shown in Fig. 11 justifies the capability of the converter to reshape the input current and regulate the output voltage at 50 V DC. Fig. 12a shows the input current and output voltage response with the same load changes (50 W–100 W–50 W) at 140 V peak input voltage. It shows that the circuit is capable to cater with universal input voltage. As can be seen, the current response also shows a good regulation and comparable with the current response shown in Fig. 10a. The same goes to the output voltage waveform whereby it is successfully being regulated at 50 V DC with almost the same response as Fig. 10a but with slightly bigger overshoot. However, as shown in Fig. 12b, the width of input current waveform within each switching period is almost twice compared to the current shown in Fig. 10c. This is due to the fact that in order to maintain the same input power, larger input current should be drawn from the mains if the input peak voltage is reduced from 340 V to 140 V. Again, the results in SABER for 140 V peak, as depicted in Fig. 13, shows a good agreement between the developed model and the switch model.
(a) 12 10 8
Vout IL1
6 4 2 0 -2 -4 -6 0.2
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0.5
0.6
0.7
0.8
0.9
1
Time [sec]
(b)
5
4
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-1 0.605
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0.6051
0.6051
0.6051
0.6051
0.6051
0.6052
0.6052
0.6052
Time [sec] Fig. 12. Simulation results of the (a) input current, IL1 (1A/div), and output voltage, Vout (5 V/div) response with load variations (50 W–100 W–50 W) and (b) the input current waveforms for each switching period with Vm = 140 V.
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611
Fig. 13. Simulation results of the (a) input current and (b) output voltage response with load variations (50 W–100 W–50 W) using SABER simulator for Vm = 140 V.
5. Conclusion The small-signal and steady state analysis of the proposed converter has been derived using CIECA method. It is found that these models are vital in knowing the dynamic characteristics and the appropriate parameters of the proposed converter operated in DCM. The simulation results show that the proposed converter is able to work as a simple PFC circuit with the capability to regulate the output voltage over a wide range of load values and with universal input voltage conditions. The SABER simulator is used to obtain the results in a complete switch model and further verify the model developed in SIMULINK using CIECA approach. References [1] D.M. Mitchell, AC–DC converter having an improved power factor, US Patent 4412277, 1983. [2] Bin Su, Zhengyu Lu, An interleaved totem-pole boost bridgeless rectifier with reduced reverse-recovery problems for power factor correction, IEEE Transactions on Power Electronics 25 (6) (2010) 1406–1415. [3] K. Mino, H. Matsumoto, S. Fujita, Y. Nemoto, D. Kawasaki, R. Yamada, N. Tawada, Novel bridgeless PFC converters with low inrush current stress and high efficiency, in: International Power Electronics Conference (IPEC), 2010, pp. 1733–1739. [4] L. Huber, Y. Jang, M.M. Jovanovic, Performance evaluation of Bridgeless PFC Boost rectifiers, IEEE Transactions on Power Electronics 23 (3) (2008) 1381– 1390. [5] W.Y. Choi, J.M. Kwon, E.H. Kim, J.J. Lee, B.H. Kwon, Bridgeless Boost rectifier with low conduction losses and reduced diode reverse-recovery problems, IEEE Transactions on Industrial Electronics 54 (2) (2007) 769–780. [6] A.J. Sabzali , E.H. Ismail, M.A. Al-Saffar, A.A. Fardoun, A new bridgeless PFC Sepic and Cuk rectifiers with low conduction and switching losses, in: International Conference on Power Electronics and Drive Systems, 2009, pp. 550–556. [7] Yungtaek Jang, M.M. Jovanovic, Bridgeless buck PFC rectifier, in: Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010, pp. 23–29. [8] Woo-Young Choi, Wen-Song Yu, Jih-Sheng Lai, A novel bridgeless single-stage half-bridge AC/DC converter, in: Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010, pp. 42–46. [9] J. Betten, R. Kollman, Converter face-off: SEPIC vs Flyback, in: EE Times Asia Magazine, 2007. [10] D.S.L. Simonetti, J. Sebastian, J. Uceda, The discontinuous conduction mode Sepic and Cuk power factor preregulators: analysis and design, IEEE Transactions on Industrial Electronics 44 (5) (1997) 630–637. [11] E.H. Ismail, Bridgeless SEPIC rectifier with unity power factor and reduced conduction losses, IEEE Transactions on Industrial Electronics 56 (4) (2009) 1147–1157. [12] C.K. Tse, Circuit theory of power factor correction in switching converters, International Journal of Circuit Theory and Applications 31 (2) (2003) 157– 198. [13] W. Huai, I. Batarseh I, Comparison of basic converter topologies for power factor correction, in: IEEE Proceedings Southeastcon, 1998, pp. 348–353. [14] P.R.K. Chetty, Current injected equivalent circuit approach to modeling switching DC–DC converters, IEEE Transactions on Aerospace and Electronic Systems 17 (6) (1981) 802–808. [15] P.R.K. Chetty, Current injected equivalent circuit approach to modeling of switching DC–DC converters in discontinuous inductor conduction mode, IEEE Transactions on Industrial Electronics 29 (3) (1982) 230–234. [16] J.H. Su, J.J. Chen, D.S. Wu, Learning feedback controller design of switching converters via MATLAB/SIMULINK, IEEE Transactions on Education 45 (4) (2002) 307–315.
