Modeling Framework for Cross-point Resistive Memory ... - IEEE Xplore
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Modeling Framework for Cross-point Resistive Memory Design Emphasizing Reliability and Variability Issues Yang Zheng∗
Cong Xu∗
Yuan Xie∗†
Department of Computer Science and Engineering, Pennsylvania State University∗ Department of Electrical and Computer Engineering, University of California at Santa Barbara† [email protected]†
Abstract—Resistive RAM (ReRAM) cross-point memory technology is one of the most promising candidates for future memory designs as it offers small cell area, fast write latency, and excellent scalability. However, it also suffers from more severe reliability issues than other Non-volatile Memory (NVM) technologies. Due to the lack of access device, ReRAM cells cannot be turned off completely and thus write disturbance problem and hard errors can affect the memory array reliability. Moreover, ReRAM cell suffers from temporal variation caused by its stochastic nature, which results in the resistance change. In this paper, pseudo-hard error caused by temporal variation is defined for the first time as a unique type of error in ReRAM cross-point structure. A comprehensive model is proposed to numerically evaluate all kinds of reliability and variability issues including voltage drop, read/write disturbance, spatial/temporal variations, and hard errors. Detailed analysis are presented, and mitigation solutions including dualport write and test-and-flip strategy are proposed to shed light on reliable ReRAM cross-point memory design.
I.
I NTRODUCTION
Traditional memory technologies such as DRAM and SRAM are increasingly constrained by fundamental technology limits [1]. Emerging non-volatile memory (NVM) technologies such as spintransfer-torque RAM (STT-RAM), phase-change RAM (PCRAM), and resistive RAM (ReRAM) have been widely studied as potential candidates to meet the demand of high capacity, low power consumption, and low cost. Among all these NVM technologies, ReRAM is one of the most attractive successors to the current memory due to its unique characteristics, such as non-linearity, high resistance ratio, excellent scalability, and fast write latency. It has been reported that T aOx/T iO2 ReRAM can achieve 9μA SET current and 1μA RESET current for a 40nm-size cell, with a resistance ratio of larger than 100 and non-linearity of 100 [2]. Moreover, ReRAM can be implemented in a cross-point structure without any access device among all these memory technologies. Although the ReRAM cross-point structure offers high density and regularity, it also suffers from serious reliability problems. The parasitic leakage paths in unselected cells and series resistance of the interconnects [3] reduce the voltage bias on farther cells, making it harder to switch those cells that are far from the voltage driver. This voltage drop problem restricts the array size and thus eliminates the high density of cross-point structure. Besides, due to the absence of access transistor, the data stored in other ReRAM cells sharing the same wordline or bitline with selected cells (i.e. “half-selected cells”) may be affected by write operations, which refers to the write disturbance problem [4]. Also, the hard error has much more serious effect on cross-point structure since there is no isolation between cells. A half-selected cell with hard error will impact the entire wordline/bitline and thus seriously impact the read and write operations. Moreover, it will continuously impact the ReRAM array in every cycle after it first happens since it cannot be turned off completely. To address these problems, a common method is to This work was supported in part by NSF1218867, 1213052 and 1409798.
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leverage a memory selection device such as diode and transistor in the memory cell to turn off the cell [5], [6]. Although they reduce the sneak current effectively, the diode requires much higher programming voltage (>4V) and suffers from endurance problem (only 104 cycles). Therefore, implementing reliable cross-point ReRAM structure with high energy-efficiency, small cell area, and low cost, remains to be a problem. The variability of ReRAM in the switching parameters is different and much worse than that of STT-RAM and PCRAM because ReRAM suffers from both spatial variation (from device to device) and temporal variation (from cycle to cycle). The spatial variation results from the process variation, which also occurs in other NVM technologies. On the other hand, the temporal variation occurs in a single device due to the stochastic nature of the conductive filament formation or rupture [7]. The temporal variation impacts the distribution of the voltage bias on each cell, which in return enlarges the resistance difference between cells. This accumulating effect will seriously worsen the reliability of ReRAM cross-point structure over cycles. If the resistance in the on-state is too low or resistance in the off-state is too high, the same programming voltage may not be able to switch the ReRAM state, resulting in write failure. We shall define this new type of error as pseudo-hard error, as it seems to be a hard error but is also recoverable. Most of current cross-point models either do not consider the reliability issues at all or address only one of them, leading to inaccurate results and even design failure. The importance of considering all these reliability and variability issues lies in the following reasons: (1) the stochastic nature of ReRAM device renders the traditional worstcase design not always promising; (2) some unique issues caused by the intrinsic nature of ReRAM introduce extra constraints on memory design; (3) some of them work together to further worsen the array reliability. Moreover, most models are based on very simple assumptions which also lead to inaccuracy. For example, the voltage biases on ReRAM cells in the array are actually different from each other and thus the resistances of ReRAM cells are various rather than just two resistance values (high resistance value and low resistance value), which may affect the worst case voltage drop. Therefore a complete model is essential for comprehensive analysis on all these reliability and variability issues. The major contributions of this paper include: • We proposed a comprehensive ReRAM cross-point array model, which is able to simulate all kinds of reliability and variability issues including voltage drop, read/write disturbance, spatial/temporal variations, and hard error. We revealed the intrinsic switching mechanism of the ReRAM cell and show how the reliability issues impact the ReRAM cross-point array design. • For the first time, we introduce pseudo-hard error, a unique type of error in the ReRAM cell caused by temporal variation. We describe how it is different from hard error and soft error, and investigate how this novel type of error affects read/write operations in the ReRAM cross-point structure.
1C-3 • We proposed pseudo-hard error detection method and potential solutions to mitigate the reliability problems. Specifically, dual-port write method is used to mitigate the worst-case voltage drop problem, and test-and-flip strategy is proposed to reduce the probability of the occurrence of worst-case. II.
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where Ea is the activation energy for ions migration, a represents the average hopping distance, Z is the charge number, E is the average electric field, which is computed using the following equation (2) [11]: E = V /[L + (Ron /Rof f − 1)h] (2) The resistance is then calculated by equation (3) [11]: R = Rof f × h + Ron × (L − h)
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where Rof f refers to the resistance per unit length of the partially ruptured CFs region with a length of h, Ron refers to the resistance per unit length of the remaining CF region with a length of Lh, and L is the total thickness of oxides. Using equation (1), we can numerically calculate the h change after a certain programming condition is applied to a ReRAM cell, which means that we are able to know how much the CF length changes after the programming process. III.
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M ODELING OF R E RAM M EMORY
A. Overview Fig. 1 illustrates the schematic of an M by N cross-point array. The ReRAM cell Ri,j is located at the cross-point of the ith wordline and jth bitline. Rl refers to the resistance of the connecting wire between two ReRAM cells. Rv is the input resistance of each voltage driver on the wordline (VW L ) and bitline (VBL ), and Rs is the resistance of sense amplifier (used in read operation). The voltage at crosspoint (i,j) is Vi,j,r for wordline layer and Vi,j,c for bitline layer, and thus the voltage bias on each ReRAM device can be represented as Vi,j,r -Vi,j,c . The current equations can be built for each cell based on Kirchhoffs Current Law (KCL). Although most of the cells in the array have similar structure, the cells at the edges of the array have different resistance and voltage conditions. Table I shows the parameters used in the model. Rsense is used to sense the voltage difference (ΔV) during read operations. Although
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A typical ReRAM memory cell has a Metal-Insulator-Metal (MIM) structure and can be switched between high resistance state (HRS, representing ‘0’) and low resistance state (LRS, representing ‘1’) by applying an external voltage across the cell. Bipolar ReRAM needs different voltage polarities for LRS-to-HRS switching (RESET operation) and HRS-to-LRS switching (SET operation). Our work is based on bipolar ReRAM technology as it is commonly used in cross-point structure [8], [9]. A positive voltage is applied on the ReRAM cell in a SET process, which leads to the formation of one or several conductive filaments (CFs) made of oxygen vacancies between the top electrode and the bottom electrode [10]. The ReRAM cell is switched to LRS once the electrodes are connected by the CFs. In contrast, a negative voltage is applied on the cell during a RESET process. The oxygen ions are forced back to recombine with the oxygen vacancies, leading to the rupture of CFs. The ReRAM is switched back to HRS when the CFs are ruptured. The formation and rupture of CFs are related to both amplitude and duration of the programming voltage. The growth rate of the ruptured region length h is given by equation (1) [11]:
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BACKGROUND ON R E RAM T ECHNOLOGY
dh/dt = v0 exp(−Ea /kT )sinh(ZqaE/2kT )
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the ReRAM resistance changes over cycles, it is restricted between the maximum value (700kΩ) and the minimum value (10kΩ). Although the programming voltage of ±2V is able to switch the resistance state of a single cell, it has to be increased due to the voltage drop problem and other reliability concerns, which will be discussed in detail in Section IV. TABLE I. Metric Acell Rl Vwrite Vread Ron Rof f Rsense Rmin Rmax m,n
D ESIGN PARAMETERS
Description Cell Area Wire Resistance Programming Voltage Read Voltage LRS Resistance HRS Resistance Sensing Resistance Minimum Resistance Maximum Resistance Number of wordline/bitline
Typical Value 4F 2 0.65Ω ±2V 0.5V 20kΩ 500kΩ 20kΩ 10kΩ 700kΩ 2∼512
B. ReRAM Cell Modeling Most of current cross-point models consider the ReRAM device as a bi-state linear resistance with two distinct values (high and low). This simple assumption may lead to inaccuracy and even design failure in large-size array. As shown in section II, the resistance is actually changing over cycles with different programming voltages. Although the voltage bias on half-selected cells is not enough to switch the resistance state, it causes obvious change of CF length and thus results in resistance shift, which refers to write disturbance problem. In our model, the ReRAM device is modeled as a variable resistance based on equation (1)-(3). Different programming conditions impact the formation and rupture process of CF and thus impact the resistance of a ReRAM cell. The cell resistance is now a function of voltage amplitude and duration. We can therefore numerically simulate the resistance shift caused by reliability and variability issues. The write voltage duration is fixed as 100ns in the experiment so that a write failure can be determined if the resistance state of any cell is not switched under the programming voltage amplitude. The minimum required voltage refers to the voltage amplitude that is just able to switch the resistance state. When considering reliability and
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IV.
R ELIABILITY C ONCERNS
In this section, the impact of different reliability issues are discussed separately. Then the overall impact is evaluated combining all the reliability issues, and a detailed simulation considering the voltage, area, and energy overhead is provided. A. Worst Case Voltage Drop The worst-case write happens when writing the farthest cell and when other cells are all in LRS. Fig. 2(a) shows the worst-case voltage drop for different array sizes with fixed programming voltage (2V) and the resistance of the selected cell after programming. When the array is larger than 64×64, the voltage drop on the selected cell is less than 1.85V and thus the resistance state of the selected cell cannot be switched, which results in a write failure. The write voltage is not large enough to completely change the resistance state from HRS to LRS when the array size is larger than 8×8 due to the voltage drop, and the resistance almost remains the same when the array size is 128×128. Fig. 2(b) illustrates the minimum required programming voltages to guarantee successful and reliable write for different array sizes. We shall define a write as “successful” if the resistance state has been successfully switched after write, and “reliable” if the resistance has been shift to designed values (20k or 500k) after write. We simply define the upper limit of LRS and lower limit of HRS are both 200k. Although reliable write requires larger voltage, it is preferred in cross-point design as it reduces write failures caused by reliability and variability factors. In the following sections we use this higher programming voltage for each array size so that the effect of unreliable write can be eliminated. B. Read/Write Disturbance Write disturbance problem affects half-selected cells. During a write operation, a write voltage is applied on the selected cell and therefore the resistance state of the selected cell is changed. Due to the lack of isolation in the cross-point structure, half-selected cells
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A write voltage is applied on the selected wordline and bitline during a write operation. In order to guarantee a successful write, the applied write voltage must be larger than the switching threshold voltage. The voltage amplitude is a little complicated in cross-point structure due to the voltage drop problem. The voltage gradually decreases along the wordline and bitline due to the existence of wire resistance and sneak current generated by half-selected cells. Therefore the voltage across R1,n is much less than VW L1 , which may result in write failure. On the one hand, the input voltage must be large enough to guarantee that even the worst-case selected cell can be switched. The worst case is determined by not only the location of the cell but also the data pattern stored in the array. In Fig. 1, the worst-case selected cell refers to R1,n . It is the farthest cell from the voltage driver and thus sees the smallest voltage bias when applying write voltage at VW L1 . The worst case happens when all the other cells are in LRS, since this data pattern generates the most sneak current. On the other hand, the input voltage must be small enough to guarantee that all the unselected cells and half-selected cells will not be switched during the write operation. In Fig. 1, R1,1 is the nearest cell to voltage driver, thus it suffers from the largest voltage drop. The input voltage should be small enough so that R1,1 will not be switched. Read operation is similar with write operation.
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Fig. 3. Resistance of the worst-case half-selected cell after a SET operation (a) under different programming voltage in a 64 × 64 array. (b) for different array sizes.
and unselected cells cannot be turned off completely and thus they also have voltage bias. Take the Fig. 1 as an example again, when writing R1,n , the voltage drop on R1,1 is almost Vwrite /2 when using the half bias scheme, which changes the CF length significantly according to equation (2). The resistances of half-selected cells are shifted higher (lower) when writing HRS (LRS) to the selected cell. During the SET process, Fig. 3(a) shows the resistance shift of HRS R1,1 after switching R1,n from HRS to LRS in a 64×64 array. When the programming voltage is larger than 3.2V, R1,1 starts to decrease and it is also switched to LRS if the voltage is larger than 3.8V. On the other hand, if R1,1 is in LRS, the resistance will become even lower and thus will cause over-write problem [12], which will be illustrated in Section IV.C. Since the voltage drops on unselected cells are relatively small, their resistances will not have obvious changes. Write disturbance problem seriously restricts the array size (Fig. 3(b)). The resistance of half-selected cells after a worst-case write will not be affected in arrays smaller than 128×128, while the problem becomes increasingly serious in large size array (256×256), rendering the voltage bias on half-selected cell even larger than 2V and thus resulting in the state switch of half-selected cells. Read disturbance problem affects only the selected cell. During a read operation, a read voltage is applied on the selected cell. The read voltage is usually much smaller than write voltage, therefor it only slightly changes the resistance of the selected cell and the voltage drops on other cells are negligible. C. Pseudo-hard Error The variability issue in ReRAM cross-point structure is extremely severe as it suffers from both spatial and temporal variations. While the spatial variation typically comes from process variation and line edge roughness, which could be mitigated to some extent, the temporal variation results from the stochastic nature of the conductive filament formation and rupture, which results in large variations in a single device from cycle to cycle [7]. Device level analysis for bipolar
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margin (ΔV/V). Moreover, since the LRS resistance in type II also decreases over cycles, the worst case voltage drop becomes even worse and thus may introduces more pseudo-hard errors. Fig. 7(a) shows the read noise margin degradation. ΔV refers to the voltage difference of worst-case reading HRS and worst-case reading LRS. All types of hard error result in serious degradation of read noise margin after 105 cycles. Fig. 7(b) shows the worstcase voltage drop caused by type II error in half-selected cells in a 128×128 array. Fig. 7(c) evaluates the worst-case voltage drop for different array sizes assuming half of half-selected cells suffer from type II hard error. In order to exclude any other reliability factors, we choose the programming voltage that guarantees reliable write. Fig. 7(d) demonstrates that larger programming voltage is required to guarantee successful or reliable write.
Normalized Read Noise Margin
ReRAM devices has been proposed in [13], while seldom work talks about its impact on memory design. The importance of considering the impact of temporal variation lies in the fact that this phenomenon introduces a new type of write error which is unique in ReRAM array and it is observed in all ReRAMs reported so far. The black curves in Fig. 4 illustrate the resistance distribution of both resistance states. Initially the ReRAM device was in LRS (HRS) state. It was biased under the same switching voltage (∓2V) for hundreds of times. Each time after it was switched to HRS (LRS), its resistance was measured and then it was SET (RESET) to LRS (HRS) again. This process was done in real devices [14] and the result demonstrates that both HRS and LRS resistance obey Log-normal distribution respectively. The impact of temporal variation lies in two aspects. If the LRS (HRS) resistance is not low (high) enough, the sensing margin shrinks, resulting in longer read latency and worse endurance. On the other hand, if the LRS (HRS) resistance is too low (high) (so-called overwrite [12]), write failure may happen in the next write cycle since the same programming condition cannot switch it anymore. However it should not be considered as a hard error since it is recoverable. Either increasing the voltage amplitude or the write pulse width can eliminate this error. Therefore, we define this error as pseudo-hard error, which is unique in the ReRAM technology. Pseudo-hard error can also be caused by temporal variation of halfselected cells (rather than selected cells). It is quite possible that most of half-selected cells shift to lower resistance in the same cycle, resulting in larger sneak current in the array. Thus the voltage drop on the selected cell becomes even smaller, which may not be enough to switch the resistance state and thus causes write failure. This failure is also recoverable in the following cycles if the resistances of halfselected cells become higher again. Different from traditional voltage drop problem, it cannot be eliminated by worst-case design since this stochastic variation is not predictable. To evaluate the impact of over-write problem, Fig. 5(a) shows the resistance of the worst-case selected cell after applying a SET voltage on it in a 64×64 cross-point array. We simulate a relatively bad case in which the resistance of the selected cell always shifts to a higher resistance. When applying a 2V SET voltage (successful write), the resistance cannot be successfully changed after 32 cycles and thus a pseudo-hard error occurs. On the other hand, pseudo-hard errors will not occur until 128 cycles when applying 2.2V SET voltage (reliable write). Fig. 5(b) evaluates the impact of temporal variation on the worst case voltage drop in a 64*64 cross-point array.
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Fig. 5. (a) Resistance of the worst-case selected cell after a SET operation. (b) Worst case voltage drop under different write schemes and resistances of half-selected cells.
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D. Hard Error Three types of hard errors in ReRAM cells have been observed in ReRAM devices [15]. Fig. 6 illustrates the R-t fitting curve for different types of hard errors, which correspond with fabricated devices in [14]. All the error types result in the reduction of resistance difference of HRS and LRS and therefore the reduction of read noise
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Fig. 8. (a) Worst case voltage drop and minimum required programming voltage. (b) Area overhead in a 64×64 array. (c) Energy overhead in a 64×64 array. (d) energy overhead for different array sizes after 105 cycles.
E. Overall Impact This section proposed a detailed analysis on the overall effect of reliability and variability issues. The combined effect is more complicated than simply adding their effect together. Some reliability and variability issues may mitigate the impact of other issues on crosspoint array, while some work together to further harm the cross-point array. For example, when half-selected cells suffer from type I error, the worst-case voltage drop is mitigated since LRS resistances go up. On the other hand, temporal variation and type II hard error further worsens the worst-case voltage drop. Fig. 8(a) illustrates the worst-case voltage drop of two different array sizes. In order to guarantee the array endurance to be longer than 105 cycles, 2.5V is the minimum programming voltage for 64×64 array while 3.8V is needed for 128×128 array. The area and energy overhead of a 64×64 array are illustrated in Fig. 8(b)-(c). In the first few cycles the temporal variation is not obvious and hard error seldom appears in the array. 2.2V can guarantee a successful write, and thus the area of voltage driver is only half of the array area. However the minimum required programming voltage increases gradually over cycles, resulting the increasing driver area and also energy consumption. Fig. 8(d) illustrates the energy overhead for different array sizes after 105 cycles. The energy-per-bit is used rather than total energy to fairly compare the energy consumption. For each array size, the right column refers to the energy consumption without considering all the reliability concerns, and the left column refers to the energy consumption after 105 cycles. Larger size array suffers from more severe reliability and variability problems, and thus has more energy overhead. V.
M ITIGATION S OLUTIONS
In this section, we propose a multi-P&V method to detect pseudohard error. Dual-port write scheme and test-and-flip strategy are proposed to mitigate the reliability concerns.
the selected cell right after the programming process to verify if the write is successful. Similar method is used in distinguishing different error types. As shown in Fig. 9, two extra P&V processes are used for each unsuccessful write: the first P&V rules out the possibility of soft error which is caused by data retention failure and is recoverable in the next cycle; the second P&V applies larger programming voltage (or longer programming duration) on the cell, in which a pseudohard error is able to be recovered. If the cell is still not programmed successfully, it suffers from hard error. The soft error must be ruled out and corrected first. Otherwise, larger voltage in the third P&V process will cause a new pseudo-hard error. Although this approach pays the penalty of longer write latency, it is still worthwhile since (1) ReRAM cells in the array may suffer from different types of hard errors which behave quite different, and thus a general detection method is not practical; (2) In contrast to STT-RAM and PCRAM, ReRAM shows continuous improvement on the write latency (0.3ns [12]) which is no longer a bottleneck in the ReRAM memory design. B. Dual-port Write Voltage drop problem seriously restricts array size. When the number of wordline/bitline becomes larger, the sneak current and voltage drop on wire resistance is larger as well. One possible solution is to add another set of voltage drivers in the other side of wordline/bitline. As shown in Fig. 1, when selecting the 1st wordline, both VW L1 and VW L1 are set to write voltage now (rather than leaving the VW L1 floating). The worst-case selected cell is now R1,(n/2) or R1,(n/2+1) , which have a distance of n/2 with the driver rather than n. Thus writing a 64 × 64 array is just like writing two 32 × 32 arrays (Fig. 10(a)). For the double-port array, a programming voltage of 2.2V is large enough to guarantee the endurance of 106 cycles (2.9V for single-port array) and the array consumes only 73.3% energy of that for single-port array (Fig. 10(b)). On the other hand, one major disadvantage of double-port method is that the area and energy of voltage driver doubles. Although the energy consumed by voltage driver is relatively small in small arrays, it could dominate for multi-bit write in large arrays. C. Test-and-flip
A. Pseudo-hard Error Detection Program-and-verify (P&V) method is commonly used in programming Non-volatile Memory cells [16]. A read voltage is applied on
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Multiple cells in a single row can be selected during a read/write operation. The number of selected cells in a row is determined by the hardware. Fig. 11 illustrates a 64×64 array in which 8 bits in
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a single row are selected in one read/write operation. 64 cells are divided into 8 groups, and 1 bit in each group is selected during a read/write operation. Since multiple cells are programmed at one time, the worst-case voltage drop is more severe than writing a single bit. Fig. 12 shows the worst-case voltage drop of writing 1 bit and 8 bits in a row. The worst case happens when all the half-selected cells are in LRS. Usually the selected cells are read before writing new data into them to mitigate endurance problem. Our Test-and-flip strategy also applies a read on the data that are being written into the cells. If the new data contains more than half LRS (‘1’), all the bits in the new data are flipped and then written into the cells. This Test-and-flip process guarantees that the number of LRS cells is always less than half of the number of wordline/bitlines. Fig. 13 compares the worst case voltage drop with and without Test-and-flip process when considering all the reliability and variability issues. An extra bit is used for each cache block to record whether this block contains flipped data or not. In Fig. 11, each wordline has 64 bits and 8 bits are selected each time, thus 8 bits are needed for each wordline. If the redundant bit is ‘1’, it means the corresponding bits are flipped. The redundant bits for a 64×64 array is 8×64 = 512 bits. In other words, Test-and-flip strategy brings 12.5% area overhead. As the number of selected cells increase, the number of redundant bits decreases and thus the area overhead also decreases.
[8]
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C ONCLUSION
In this paper, a comprehensive model is provided to numerically evaluate the impact of reliability and variability issues on ReRAM cross-point array design. The simulation results show that the combined effect of multiple reliability issues is even more severe. Besides, temporal variation causes a unique type of error in ReRAM array, which is defined for the first time as pseudo-hard error. To improve the endurance, larger programming voltage is applied with area and energy overhead. The high device density and high energy-efficiency are offset by the severe reliability issues. Based on the simulation result, several detection and mitigation methods are proposed.
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Y. Xie. Modeling, architecture, and applications for emerging memory technologies. Design & Test of Computers, 28(1):44–51, 2011. B. Govoreanu, A. Redolfi, L. Zhang, C. Adelmann, M. Popovici, S. Clima, H. Hody, V. Paraschiv, I.P. Radu, A. Franquet, J.-C. Liu, J. Swerts, O. Richard, H. Bender, L. Altimime, and M. Jurczak. Vacancy-modulated conductive oxide resistive ram (vmco-rram): An area-scalable switching current, self-compliant, highly nonlinear and wide on/off-window resistive switching cell. In International Electron Devices Meeting (IEDM), pages 10.2.1–10.2.4, 2013. A Flocke and T.G. Noll. Fundamental analysis of resistive nanocrossbars for the use in hybrid nano/cmos-memory. In Solid State Circuits Conference, pages 328–331, 2007. D. Niu, C. Xu, N. Muralimanohar, N. Jouppi, and Y. Xie. Design tradeoffs for high density cross-point resistive memory. In International Symposium on Low Power Electronics and Design (ISLPED), pages 209–214, 2012. M.-J. Lee, Y. Park, B.-S. Kang, S.-E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.-H. Lee, S.-J. Chung, Y.-H. Kim, C.-S. Lee, J.-B. Park, and I.-K. Yoo. 2-stack 1d-1r cross-point structure with oxide diodes as switch elements for high density resistance ram applications. In International Electron Devices Meeting (IEDM), page 771C774, 2007. Y. Zhang, K. SangBum, J. P. McVittie, H. Jagannathan, J. B. Ratchford, C. E. D. Chidsey, Y. Nishi, and H. S. P.Wong. An integrated phase change memory cell with ge nanowire diode for cross-point memory. In VLSI Technology, page 98C99, 2007. X. Guan, S. Yu, and H.-S.P. Wong. On the switching parameter variation of metal-oxide rramłpart i: Physical modeling and simulation methodology. IEEE Trans. on Electron Devices, 59(4):1172–1182, 2012. S. Sheu, M. Chang, K. Lin, C. Wu, Y. Chen, P. Chiu, C. Kuo, Y. Yang, P. Chiang, W. Lin, C. Lin, H. Lee, P. Gu, S. Wang, F. Chen, K. Su, C. Lien, K. Cheng, H. Wu, T. Ku, M. Kao, and M.J. Tsai. A 4mb embedded slc resistive-ram macro with 7.2ns read-write randomaccess time and 160ns mlc-access capability. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 200–202, 2011. W. Otsuka, K. Miyata, M. Kitagawa, K. Tsutsui, T. Tsushima, H. Yoshihara, T. Namise, Y. Terao, and K. Ogata. A 4mb conductive-bridge resistive memory with 2.3gb/s read-throughput and 216mb/s programthroughput. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 210–211, 2011. H.-S.P. Wong, H. Lee, S. Yu, Y. Chen, Y. Wu, P. Chen, B. Lee, F. Chen, and M.J. Tsai. Metalcoxide rram. Proceedings of the IEEE, 100(6):1951–1970, 2012. S. Yu and H.-S. P. Wong. Modeling the switching dynamics of programmable-metallization cell (pmc) memory and its application as synapse device for a neuromorphic computation system. In International Electron Devices Meeting (IEDM), pages 520–523, 2010. H.Y. Lee, Y.S. Chen, P.S. Chen, P.Y. Gu, Y.Y. Hsu, S.M. Wang, W.H. Liu, C.H. Tsai, S.S. Sheu, P.C. Chiang, W.P. Lin, C.H. Lin, W.S. Chen, F.T. Chen, C.H. Lien, and M.-J. Tsai. Evidence and solution of overreset problem for hfox based resistive memory with sub-ns switching speed and high endurance. In International Electron Devices Meeting (IEDM), pages 19.7.1–19.7.4, 2010. X. Guan, S. Yu, and H.-S. P. Wong. A spice compact model of metal oxide resistive switching memory with variations. Electron Device Letters, 33(10):1405–1407, 2012. S. Yu, B. Gao, Z. Fang, H. Yu, J. Kang, and H.-S. P. Wong. A low energy oxide-based electronic synaptic device for neuromorphic visual systems with tolerance to device variation. Advanced Materials, 25(12):1774–1779, 2013. B. Chen, Y. Lu, B. Gao, Y. H. Fu, F. Zhang, P. Huang, Y. Chen, L. Liu, X. Liu, J. Kang, Y. Y. Wang, Z. Fang, H.Y. Yu, X. Li, X. Wang, N. Singh, G.Q. Lo, and D.-L. Kwong. Physical mechanisms of endurance degradation in tmo-rram. In International Electron Devices Meeting (IEDM), pages 12.3.1–12.3.4, 2011. X. Dong and Y. Xie. Adams: Adaptive mlc/slc phase-change memory design for file storage. In Asia and South Pacific Design Automation Conference (ASP-DAC), pages 31–36, 2011.
Modeling Framework for Cross-point Resistive Memory Design Emphasizing Reliability and Variability Issues Yang Zheng∗
Cong Xu∗
Yuan Xie∗†
Department of Computer Science and Engineering, Pennsylvania State University∗ Department of Electrical and Computer Engineering, University of California at Santa Barbara† [email protected]†
Abstract—Resistive RAM (ReRAM) cross-point memory technology is one of the most promising candidates for future memory designs as it offers small cell area, fast write latency, and excellent scalability. However, it also suffers from more severe reliability issues than other Non-volatile Memory (NVM) technologies. Due to the lack of access device, ReRAM cells cannot be turned off completely and thus write disturbance problem and hard errors can affect the memory array reliability. Moreover, ReRAM cell suffers from temporal variation caused by its stochastic nature, which results in the resistance change. In this paper, pseudo-hard error caused by temporal variation is defined for the first time as a unique type of error in ReRAM cross-point structure. A comprehensive model is proposed to numerically evaluate all kinds of reliability and variability issues including voltage drop, read/write disturbance, spatial/temporal variations, and hard errors. Detailed analysis are presented, and mitigation solutions including dualport write and test-and-flip strategy are proposed to shed light on reliable ReRAM cross-point memory design.
I.
I NTRODUCTION
Traditional memory technologies such as DRAM and SRAM are increasingly constrained by fundamental technology limits [1]. Emerging non-volatile memory (NVM) technologies such as spintransfer-torque RAM (STT-RAM), phase-change RAM (PCRAM), and resistive RAM (ReRAM) have been widely studied as potential candidates to meet the demand of high capacity, low power consumption, and low cost. Among all these NVM technologies, ReRAM is one of the most attractive successors to the current memory due to its unique characteristics, such as non-linearity, high resistance ratio, excellent scalability, and fast write latency. It has been reported that T aOx/T iO2 ReRAM can achieve 9μA SET current and 1μA RESET current for a 40nm-size cell, with a resistance ratio of larger than 100 and non-linearity of 100 [2]. Moreover, ReRAM can be implemented in a cross-point structure without any access device among all these memory technologies. Although the ReRAM cross-point structure offers high density and regularity, it also suffers from serious reliability problems. The parasitic leakage paths in unselected cells and series resistance of the interconnects [3] reduce the voltage bias on farther cells, making it harder to switch those cells that are far from the voltage driver. This voltage drop problem restricts the array size and thus eliminates the high density of cross-point structure. Besides, due to the absence of access transistor, the data stored in other ReRAM cells sharing the same wordline or bitline with selected cells (i.e. “half-selected cells”) may be affected by write operations, which refers to the write disturbance problem [4]. Also, the hard error has much more serious effect on cross-point structure since there is no isolation between cells. A half-selected cell with hard error will impact the entire wordline/bitline and thus seriously impact the read and write operations. Moreover, it will continuously impact the ReRAM array in every cycle after it first happens since it cannot be turned off completely. To address these problems, a common method is to This work was supported in part by NSF1218867, 1213052 and 1409798.
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leverage a memory selection device such as diode and transistor in the memory cell to turn off the cell [5], [6]. Although they reduce the sneak current effectively, the diode requires much higher programming voltage (>4V) and suffers from endurance problem (only 104 cycles). Therefore, implementing reliable cross-point ReRAM structure with high energy-efficiency, small cell area, and low cost, remains to be a problem. The variability of ReRAM in the switching parameters is different and much worse than that of STT-RAM and PCRAM because ReRAM suffers from both spatial variation (from device to device) and temporal variation (from cycle to cycle). The spatial variation results from the process variation, which also occurs in other NVM technologies. On the other hand, the temporal variation occurs in a single device due to the stochastic nature of the conductive filament formation or rupture [7]. The temporal variation impacts the distribution of the voltage bias on each cell, which in return enlarges the resistance difference between cells. This accumulating effect will seriously worsen the reliability of ReRAM cross-point structure over cycles. If the resistance in the on-state is too low or resistance in the off-state is too high, the same programming voltage may not be able to switch the ReRAM state, resulting in write failure. We shall define this new type of error as pseudo-hard error, as it seems to be a hard error but is also recoverable. Most of current cross-point models either do not consider the reliability issues at all or address only one of them, leading to inaccurate results and even design failure. The importance of considering all these reliability and variability issues lies in the following reasons: (1) the stochastic nature of ReRAM device renders the traditional worstcase design not always promising; (2) some unique issues caused by the intrinsic nature of ReRAM introduce extra constraints on memory design; (3) some of them work together to further worsen the array reliability. Moreover, most models are based on very simple assumptions which also lead to inaccuracy. For example, the voltage biases on ReRAM cells in the array are actually different from each other and thus the resistances of ReRAM cells are various rather than just two resistance values (high resistance value and low resistance value), which may affect the worst case voltage drop. Therefore a complete model is essential for comprehensive analysis on all these reliability and variability issues. The major contributions of this paper include: • We proposed a comprehensive ReRAM cross-point array model, which is able to simulate all kinds of reliability and variability issues including voltage drop, read/write disturbance, spatial/temporal variations, and hard error. We revealed the intrinsic switching mechanism of the ReRAM cell and show how the reliability issues impact the ReRAM cross-point array design. • For the first time, we introduce pseudo-hard error, a unique type of error in the ReRAM cell caused by temporal variation. We describe how it is different from hard error and soft error, and investigate how this novel type of error affects read/write operations in the ReRAM cross-point structure.
1C-3 • We proposed pseudo-hard error detection method and potential solutions to mitigate the reliability problems. Specifically, dual-port write method is used to mitigate the worst-case voltage drop problem, and test-and-flip strategy is proposed to reduce the probability of the occurrence of worst-case. II.
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where Ea is the activation energy for ions migration, a represents the average hopping distance, Z is the charge number, E is the average electric field, which is computed using the following equation (2) [11]: E = V /[L + (Ron /Rof f − 1)h] (2) The resistance is then calculated by equation (3) [11]: R = Rof f × h + Ron × (L − h)
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where Rof f refers to the resistance per unit length of the partially ruptured CFs region with a length of h, Ron refers to the resistance per unit length of the remaining CF region with a length of Lh, and L is the total thickness of oxides. Using equation (1), we can numerically calculate the h change after a certain programming condition is applied to a ReRAM cell, which means that we are able to know how much the CF length changes after the programming process. III.
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A. Overview Fig. 1 illustrates the schematic of an M by N cross-point array. The ReRAM cell Ri,j is located at the cross-point of the ith wordline and jth bitline. Rl refers to the resistance of the connecting wire between two ReRAM cells. Rv is the input resistance of each voltage driver on the wordline (VW L ) and bitline (VBL ), and Rs is the resistance of sense amplifier (used in read operation). The voltage at crosspoint (i,j) is Vi,j,r for wordline layer and Vi,j,c for bitline layer, and thus the voltage bias on each ReRAM device can be represented as Vi,j,r -Vi,j,c . The current equations can be built for each cell based on Kirchhoffs Current Law (KCL). Although most of the cells in the array have similar structure, the cells at the edges of the array have different resistance and voltage conditions. Table I shows the parameters used in the model. Rsense is used to sense the voltage difference (ΔV) during read operations. Although
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A typical ReRAM memory cell has a Metal-Insulator-Metal (MIM) structure and can be switched between high resistance state (HRS, representing ‘0’) and low resistance state (LRS, representing ‘1’) by applying an external voltage across the cell. Bipolar ReRAM needs different voltage polarities for LRS-to-HRS switching (RESET operation) and HRS-to-LRS switching (SET operation). Our work is based on bipolar ReRAM technology as it is commonly used in cross-point structure [8], [9]. A positive voltage is applied on the ReRAM cell in a SET process, which leads to the formation of one or several conductive filaments (CFs) made of oxygen vacancies between the top electrode and the bottom electrode [10]. The ReRAM cell is switched to LRS once the electrodes are connected by the CFs. In contrast, a negative voltage is applied on the cell during a RESET process. The oxygen ions are forced back to recombine with the oxygen vacancies, leading to the rupture of CFs. The ReRAM is switched back to HRS when the CFs are ruptured. The formation and rupture of CFs are related to both amplitude and duration of the programming voltage. The growth rate of the ruptured region length h is given by equation (1) [11]:
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the ReRAM resistance changes over cycles, it is restricted between the maximum value (700kΩ) and the minimum value (10kΩ). Although the programming voltage of ±2V is able to switch the resistance state of a single cell, it has to be increased due to the voltage drop problem and other reliability concerns, which will be discussed in detail in Section IV. TABLE I. Metric Acell Rl Vwrite Vread Ron Rof f Rsense Rmin Rmax m,n
D ESIGN PARAMETERS
Description Cell Area Wire Resistance Programming Voltage Read Voltage LRS Resistance HRS Resistance Sensing Resistance Minimum Resistance Maximum Resistance Number of wordline/bitline
Typical Value 4F 2 0.65Ω ±2V 0.5V 20kΩ 500kΩ 20kΩ 10kΩ 700kΩ 2∼512
B. ReRAM Cell Modeling Most of current cross-point models consider the ReRAM device as a bi-state linear resistance with two distinct values (high and low). This simple assumption may lead to inaccuracy and even design failure in large-size array. As shown in section II, the resistance is actually changing over cycles with different programming voltages. Although the voltage bias on half-selected cells is not enough to switch the resistance state, it causes obvious change of CF length and thus results in resistance shift, which refers to write disturbance problem. In our model, the ReRAM device is modeled as a variable resistance based on equation (1)-(3). Different programming conditions impact the formation and rupture process of CF and thus impact the resistance of a ReRAM cell. The cell resistance is now a function of voltage amplitude and duration. We can therefore numerically simulate the resistance shift caused by reliability and variability issues. The write voltage duration is fixed as 100ns in the experiment so that a write failure can be determined if the resistance state of any cell is not switched under the programming voltage amplitude. The minimum required voltage refers to the voltage amplitude that is just able to switch the resistance state. When considering reliability and
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R ELIABILITY C ONCERNS
In this section, the impact of different reliability issues are discussed separately. Then the overall impact is evaluated combining all the reliability issues, and a detailed simulation considering the voltage, area, and energy overhead is provided. A. Worst Case Voltage Drop The worst-case write happens when writing the farthest cell and when other cells are all in LRS. Fig. 2(a) shows the worst-case voltage drop for different array sizes with fixed programming voltage (2V) and the resistance of the selected cell after programming. When the array is larger than 64×64, the voltage drop on the selected cell is less than 1.85V and thus the resistance state of the selected cell cannot be switched, which results in a write failure. The write voltage is not large enough to completely change the resistance state from HRS to LRS when the array size is larger than 8×8 due to the voltage drop, and the resistance almost remains the same when the array size is 128×128. Fig. 2(b) illustrates the minimum required programming voltages to guarantee successful and reliable write for different array sizes. We shall define a write as “successful” if the resistance state has been successfully switched after write, and “reliable” if the resistance has been shift to designed values (20k or 500k) after write. We simply define the upper limit of LRS and lower limit of HRS are both 200k. Although reliable write requires larger voltage, it is preferred in cross-point design as it reduces write failures caused by reliability and variability factors. In the following sections we use this higher programming voltage for each array size so that the effect of unreliable write can be eliminated. B. Read/Write Disturbance Write disturbance problem affects half-selected cells. During a write operation, a write voltage is applied on the selected cell and therefore the resistance state of the selected cell is changed. Due to the lack of isolation in the cross-point structure, half-selected cells
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A write voltage is applied on the selected wordline and bitline during a write operation. In order to guarantee a successful write, the applied write voltage must be larger than the switching threshold voltage. The voltage amplitude is a little complicated in cross-point structure due to the voltage drop problem. The voltage gradually decreases along the wordline and bitline due to the existence of wire resistance and sneak current generated by half-selected cells. Therefore the voltage across R1,n is much less than VW L1 , which may result in write failure. On the one hand, the input voltage must be large enough to guarantee that even the worst-case selected cell can be switched. The worst case is determined by not only the location of the cell but also the data pattern stored in the array. In Fig. 1, the worst-case selected cell refers to R1,n . It is the farthest cell from the voltage driver and thus sees the smallest voltage bias when applying write voltage at VW L1 . The worst case happens when all the other cells are in LRS, since this data pattern generates the most sneak current. On the other hand, the input voltage must be small enough to guarantee that all the unselected cells and half-selected cells will not be switched during the write operation. In Fig. 1, R1,1 is the nearest cell to voltage driver, thus it suffers from the largest voltage drop. The input voltage should be small enough so that R1,1 will not be switched. Read operation is similar with write operation.
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and unselected cells cannot be turned off completely and thus they also have voltage bias. Take the Fig. 1 as an example again, when writing R1,n , the voltage drop on R1,1 is almost Vwrite /2 when using the half bias scheme, which changes the CF length significantly according to equation (2). The resistances of half-selected cells are shifted higher (lower) when writing HRS (LRS) to the selected cell. During the SET process, Fig. 3(a) shows the resistance shift of HRS R1,1 after switching R1,n from HRS to LRS in a 64×64 array. When the programming voltage is larger than 3.2V, R1,1 starts to decrease and it is also switched to LRS if the voltage is larger than 3.8V. On the other hand, if R1,1 is in LRS, the resistance will become even lower and thus will cause over-write problem [12], which will be illustrated in Section IV.C. Since the voltage drops on unselected cells are relatively small, their resistances will not have obvious changes. Write disturbance problem seriously restricts the array size (Fig. 3(b)). The resistance of half-selected cells after a worst-case write will not be affected in arrays smaller than 128×128, while the problem becomes increasingly serious in large size array (256×256), rendering the voltage bias on half-selected cell even larger than 2V and thus resulting in the state switch of half-selected cells. Read disturbance problem affects only the selected cell. During a read operation, a read voltage is applied on the selected cell. The read voltage is usually much smaller than write voltage, therefor it only slightly changes the resistance of the selected cell and the voltage drops on other cells are negligible. C. Pseudo-hard Error The variability issue in ReRAM cross-point structure is extremely severe as it suffers from both spatial and temporal variations. While the spatial variation typically comes from process variation and line edge roughness, which could be mitigated to some extent, the temporal variation results from the stochastic nature of the conductive filament formation and rupture, which results in large variations in a single device from cycle to cycle [7]. Device level analysis for bipolar
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margin (ΔV/V). Moreover, since the LRS resistance in type II also decreases over cycles, the worst case voltage drop becomes even worse and thus may introduces more pseudo-hard errors. Fig. 7(a) shows the read noise margin degradation. ΔV refers to the voltage difference of worst-case reading HRS and worst-case reading LRS. All types of hard error result in serious degradation of read noise margin after 105 cycles. Fig. 7(b) shows the worstcase voltage drop caused by type II error in half-selected cells in a 128×128 array. Fig. 7(c) evaluates the worst-case voltage drop for different array sizes assuming half of half-selected cells suffer from type II hard error. In order to exclude any other reliability factors, we choose the programming voltage that guarantees reliable write. Fig. 7(d) demonstrates that larger programming voltage is required to guarantee successful or reliable write.
Normalized Read Noise Margin
ReRAM devices has been proposed in [13], while seldom work talks about its impact on memory design. The importance of considering the impact of temporal variation lies in the fact that this phenomenon introduces a new type of write error which is unique in ReRAM array and it is observed in all ReRAMs reported so far. The black curves in Fig. 4 illustrate the resistance distribution of both resistance states. Initially the ReRAM device was in LRS (HRS) state. It was biased under the same switching voltage (∓2V) for hundreds of times. Each time after it was switched to HRS (LRS), its resistance was measured and then it was SET (RESET) to LRS (HRS) again. This process was done in real devices [14] and the result demonstrates that both HRS and LRS resistance obey Log-normal distribution respectively. The impact of temporal variation lies in two aspects. If the LRS (HRS) resistance is not low (high) enough, the sensing margin shrinks, resulting in longer read latency and worse endurance. On the other hand, if the LRS (HRS) resistance is too low (high) (so-called overwrite [12]), write failure may happen in the next write cycle since the same programming condition cannot switch it anymore. However it should not be considered as a hard error since it is recoverable. Either increasing the voltage amplitude or the write pulse width can eliminate this error. Therefore, we define this error as pseudo-hard error, which is unique in the ReRAM technology. Pseudo-hard error can also be caused by temporal variation of halfselected cells (rather than selected cells). It is quite possible that most of half-selected cells shift to lower resistance in the same cycle, resulting in larger sneak current in the array. Thus the voltage drop on the selected cell becomes even smaller, which may not be enough to switch the resistance state and thus causes write failure. This failure is also recoverable in the following cycles if the resistances of halfselected cells become higher again. Different from traditional voltage drop problem, it cannot be eliminated by worst-case design since this stochastic variation is not predictable. To evaluate the impact of over-write problem, Fig. 5(a) shows the resistance of the worst-case selected cell after applying a SET voltage on it in a 64×64 cross-point array. We simulate a relatively bad case in which the resistance of the selected cell always shifts to a higher resistance. When applying a 2V SET voltage (successful write), the resistance cannot be successfully changed after 32 cycles and thus a pseudo-hard error occurs. On the other hand, pseudo-hard errors will not occur until 128 cycles when applying 2.2V SET voltage (reliable write). Fig. 5(b) evaluates the impact of temporal variation on the worst case voltage drop in a 64*64 cross-point array.
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Fig. 5. (a) Resistance of the worst-case selected cell after a SET operation. (b) Worst case voltage drop under different write schemes and resistances of half-selected cells.
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E. Overall Impact This section proposed a detailed analysis on the overall effect of reliability and variability issues. The combined effect is more complicated than simply adding their effect together. Some reliability and variability issues may mitigate the impact of other issues on crosspoint array, while some work together to further harm the cross-point array. For example, when half-selected cells suffer from type I error, the worst-case voltage drop is mitigated since LRS resistances go up. On the other hand, temporal variation and type II hard error further worsens the worst-case voltage drop. Fig. 8(a) illustrates the worst-case voltage drop of two different array sizes. In order to guarantee the array endurance to be longer than 105 cycles, 2.5V is the minimum programming voltage for 64×64 array while 3.8V is needed for 128×128 array. The area and energy overhead of a 64×64 array are illustrated in Fig. 8(b)-(c). In the first few cycles the temporal variation is not obvious and hard error seldom appears in the array. 2.2V can guarantee a successful write, and thus the area of voltage driver is only half of the array area. However the minimum required programming voltage increases gradually over cycles, resulting the increasing driver area and also energy consumption. Fig. 8(d) illustrates the energy overhead for different array sizes after 105 cycles. The energy-per-bit is used rather than total energy to fairly compare the energy consumption. For each array size, the right column refers to the energy consumption without considering all the reliability concerns, and the left column refers to the energy consumption after 105 cycles. Larger size array suffers from more severe reliability and variability problems, and thus has more energy overhead. V.
M ITIGATION S OLUTIONS
In this section, we propose a multi-P&V method to detect pseudohard error. Dual-port write scheme and test-and-flip strategy are proposed to mitigate the reliability concerns.
the selected cell right after the programming process to verify if the write is successful. Similar method is used in distinguishing different error types. As shown in Fig. 9, two extra P&V processes are used for each unsuccessful write: the first P&V rules out the possibility of soft error which is caused by data retention failure and is recoverable in the next cycle; the second P&V applies larger programming voltage (or longer programming duration) on the cell, in which a pseudohard error is able to be recovered. If the cell is still not programmed successfully, it suffers from hard error. The soft error must be ruled out and corrected first. Otherwise, larger voltage in the third P&V process will cause a new pseudo-hard error. Although this approach pays the penalty of longer write latency, it is still worthwhile since (1) ReRAM cells in the array may suffer from different types of hard errors which behave quite different, and thus a general detection method is not practical; (2) In contrast to STT-RAM and PCRAM, ReRAM shows continuous improvement on the write latency (0.3ns [12]) which is no longer a bottleneck in the ReRAM memory design. B. Dual-port Write Voltage drop problem seriously restricts array size. When the number of wordline/bitline becomes larger, the sneak current and voltage drop on wire resistance is larger as well. One possible solution is to add another set of voltage drivers in the other side of wordline/bitline. As shown in Fig. 1, when selecting the 1st wordline, both VW L1 and VW L1 are set to write voltage now (rather than leaving the VW L1 floating). The worst-case selected cell is now R1,(n/2) or R1,(n/2+1) , which have a distance of n/2 with the driver rather than n. Thus writing a 64 × 64 array is just like writing two 32 × 32 arrays (Fig. 10(a)). For the double-port array, a programming voltage of 2.2V is large enough to guarantee the endurance of 106 cycles (2.9V for single-port array) and the array consumes only 73.3% energy of that for single-port array (Fig. 10(b)). On the other hand, one major disadvantage of double-port method is that the area and energy of voltage driver doubles. Although the energy consumed by voltage driver is relatively small in small arrays, it could dominate for multi-bit write in large arrays. C. Test-and-flip
A. Pseudo-hard Error Detection Program-and-verify (P&V) method is commonly used in programming Non-volatile Memory cells [16]. A read voltage is applied on
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Multiple cells in a single row can be selected during a read/write operation. The number of selected cells in a row is determined by the hardware. Fig. 11 illustrates a 64×64 array in which 8 bits in
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Fig. 11. Test-and-flip strategy. The data is read before programming the selected cells. If the data contains more than half LRS, all the bits in the new data are flipped and written into the cells. 8 redundant bits are used for each wordline to store whether the data is flipped.
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a single row are selected in one read/write operation. 64 cells are divided into 8 groups, and 1 bit in each group is selected during a read/write operation. Since multiple cells are programmed at one time, the worst-case voltage drop is more severe than writing a single bit. Fig. 12 shows the worst-case voltage drop of writing 1 bit and 8 bits in a row. The worst case happens when all the half-selected cells are in LRS. Usually the selected cells are read before writing new data into them to mitigate endurance problem. Our Test-and-flip strategy also applies a read on the data that are being written into the cells. If the new data contains more than half LRS (‘1’), all the bits in the new data are flipped and then written into the cells. This Test-and-flip process guarantees that the number of LRS cells is always less than half of the number of wordline/bitlines. Fig. 13 compares the worst case voltage drop with and without Test-and-flip process when considering all the reliability and variability issues. An extra bit is used for each cache block to record whether this block contains flipped data or not. In Fig. 11, each wordline has 64 bits and 8 bits are selected each time, thus 8 bits are needed for each wordline. If the redundant bit is ‘1’, it means the corresponding bits are flipped. The redundant bits for a 64×64 array is 8×64 = 512 bits. In other words, Test-and-flip strategy brings 12.5% area overhead. As the number of selected cells increase, the number of redundant bits decreases and thus the area overhead also decreases.
[8]
[9]
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VI.
C ONCLUSION
In this paper, a comprehensive model is provided to numerically evaluate the impact of reliability and variability issues on ReRAM cross-point array design. The simulation results show that the combined effect of multiple reliability issues is even more severe. Besides, temporal variation causes a unique type of error in ReRAM array, which is defined for the first time as pseudo-hard error. To improve the endurance, larger programming voltage is applied with area and energy overhead. The high device density and high energy-efficiency are offset by the severe reliability issues. Based on the simulation result, several detection and mitigation methods are proposed.
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[15]
[16]
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