morphological image processing using custom instructions on ...
MORPHOLOGICAL IMAGE PROCESSING USING CUSTOM INSTRUCTIONS ON DISTRIBUTED NIOS PROCESSORS Haichen Ren and David J. Jackson Electrical and Computer Engineering The University of Alabama Tuscaloosa, AL 35487-0286 USA [email protected] Abstract As a fundamental image processing block, morphological processing involves intensive computation and contributes significantly to an image processing system overhead. Depending on only spatially local data, several morphological operations can be implemented with parallel hardware to reduce the computation overhead. In this paper, we implement morphological image operations, which include dilation, erosion, and edge detection based on a 3x3 mask, on a distributed Altera NIOS® soft core system. We also implement custom instructions to improve the system performance. Compared with a non-distributed system without custom instructions, the speedup of several morphological operations based upon the distributed system with custom instructions can reach 11.8. The system architecture and implementation details are presented. Keywords: image processing, morphological operation, embedded processor, programmable logic, soft core. 1
INTRODUCTION
Embedded programmable processors give a system designer unprecedented freedom in determining which functions should be executed in software and which would benefit the most from dedicated hardware implementation in the form of custom peripherals or coprocessor elements. This flexibility allows a designer to not only rapidly prototype new designs and easily integrate different digital components into one design, fully realize, in hardware, several iterations of a system in a shorter amount of time, but also to explore different options for partitioning to deliver the best possible combination in that product while still meeting the design's functionality and performance requirements [1]. Based upon the Altera ExcaliburTM embedded processor solution, we design a distributed hardware implementation of several morphological operations, and custom instructions for the Altera NIOS soft core processor.
morphological image processing. In Section 4 a distributed NIOS hardware implementation with custom instructions using the ORD-4C algorithm is detailed. Section 5 presents test results and Section 6 presents conclusions. 2
One of the more popular solutions of combinations of embedded processors and programmable logic is the use of soft core microprocessors. Soft core processors are a recent digital design method that combines the advantages of programmable logic devices with those of conventional hard core processors. Soft core processors function like hard core processors but are implemented on programmable logic devices (PLD) such as Field Programmable Gate Arrays (FPGA). Scalability and flexibility are the two main advantages of soft core processors. Custom defined logic can be easily integrated to the processor with minimal interfacing requirements. Some soft core processors even allow their internal architecture to be changed to suit a particular design. And, more than one processor can be implemented in a particular design, but this is limited by the capacity and resources of the PLD used. 2.1
NIOS soft core processor
Altera Excalibur solutions include both soft core and hard core embedded processors. As part of Altera Excalibur embedded processor solutions and based on Altera APEX 20K200EFC484-2x, the NIOS soft core embedded processor is a configurable, general-purpose RISC microprocessor with a 16-bit instruction set, userselectable 32- or 16-bit datapath, and configurable register file and barrel shifter size. It can provide up to 50 MIPS performance while being optimized for area in a PLD and can easily fit into an Altera APEX device, leaving most of the logic available for peripherals and custom logic functions. Figure 1 shows the structure of the NIOS embedded processor [2]. 2.2
This paper is organized as follows. Section 2 presents the Altera Excalibur embedded processor solution. Section 3 reviews several morphological image operations and details an algorithm, ORD-4C, for
ALTERA NIOS SOFT CORE PROCESSOR
Custom Instructions
NIOS processor is one of a few types of soft core processors that allow custom instructions. Custom instructions consist of a custom logic block and software
macro. The custom logic block is the hardware that performs the operation. The NIOS processor can include up to five user-defined custom logic blocks. The blocks become part of the NIOS microprocessor’s ALU, as shown in Figure 2. A software macro is the user-interface that allows the system designer to access the custom logic through software code [3]. PBM
SRAM FLASH
Timer
Serial Port
UART
IRQ
CPU
Morphological operations on an input image are a kind of convolution between the input image and SE. For example, with a 3x3 all 1’s SE, a block of nine pixels is covered by the SE in each step, and the maximum value or minimum value among the nine pixels is picked for the dilation or erosion operation output of the central pixel. After the current operation is complete, the SE will move to the right by one pixel, or move down to the beginning of the next row if at the end of the current row. 3.2
Area Available For Customization
NIOS
APEX Device
Figure 1. The NIOS embedded programmable processor. To FIFO, Memory, or Other Logic A B
Optional FIFO, Memory, or Other Logic
Custom Logic
32 dataa
A
± >>
INTRODUCTION
Embedded programmable processors give a system designer unprecedented freedom in determining which functions should be executed in software and which would benefit the most from dedicated hardware implementation in the form of custom peripherals or coprocessor elements. This flexibility allows a designer to not only rapidly prototype new designs and easily integrate different digital components into one design, fully realize, in hardware, several iterations of a system in a shorter amount of time, but also to explore different options for partitioning to deliver the best possible combination in that product while still meeting the design's functionality and performance requirements [1]. Based upon the Altera ExcaliburTM embedded processor solution, we design a distributed hardware implementation of several morphological operations, and custom instructions for the Altera NIOS soft core processor.
morphological image processing. In Section 4 a distributed NIOS hardware implementation with custom instructions using the ORD-4C algorithm is detailed. Section 5 presents test results and Section 6 presents conclusions. 2
One of the more popular solutions of combinations of embedded processors and programmable logic is the use of soft core microprocessors. Soft core processors are a recent digital design method that combines the advantages of programmable logic devices with those of conventional hard core processors. Soft core processors function like hard core processors but are implemented on programmable logic devices (PLD) such as Field Programmable Gate Arrays (FPGA). Scalability and flexibility are the two main advantages of soft core processors. Custom defined logic can be easily integrated to the processor with minimal interfacing requirements. Some soft core processors even allow their internal architecture to be changed to suit a particular design. And, more than one processor can be implemented in a particular design, but this is limited by the capacity and resources of the PLD used. 2.1
NIOS soft core processor
Altera Excalibur solutions include both soft core and hard core embedded processors. As part of Altera Excalibur embedded processor solutions and based on Altera APEX 20K200EFC484-2x, the NIOS soft core embedded processor is a configurable, general-purpose RISC microprocessor with a 16-bit instruction set, userselectable 32- or 16-bit datapath, and configurable register file and barrel shifter size. It can provide up to 50 MIPS performance while being optimized for area in a PLD and can easily fit into an Altera APEX device, leaving most of the logic available for peripherals and custom logic functions. Figure 1 shows the structure of the NIOS embedded processor [2]. 2.2
This paper is organized as follows. Section 2 presents the Altera Excalibur embedded processor solution. Section 3 reviews several morphological image operations and details an algorithm, ORD-4C, for
ALTERA NIOS SOFT CORE PROCESSOR
Custom Instructions
NIOS processor is one of a few types of soft core processors that allow custom instructions. Custom instructions consist of a custom logic block and software
macro. The custom logic block is the hardware that performs the operation. The NIOS processor can include up to five user-defined custom logic blocks. The blocks become part of the NIOS microprocessor’s ALU, as shown in Figure 2. A software macro is the user-interface that allows the system designer to access the custom logic through software code [3]. PBM
SRAM FLASH
Timer
Serial Port
UART
IRQ
CPU
Morphological operations on an input image are a kind of convolution between the input image and SE. For example, with a 3x3 all 1’s SE, a block of nine pixels is covered by the SE in each step, and the maximum value or minimum value among the nine pixels is picked for the dilation or erosion operation output of the central pixel. After the current operation is complete, the SE will move to the right by one pixel, or move down to the beginning of the next row if at the end of the current row. 3.2
Area Available For Customization
NIOS
APEX Device
Figure 1. The NIOS embedded programmable processor. To FIFO, Memory, or Other Logic A B
Optional FIFO, Memory, or Other Logic
Custom Logic
32 dataa
A
± >>
